Add a generic QEMU API for PCI MMIO reads/writes.
The functions access little endian memory and returns
the result in host cpu endianness.
Signed-off-by: Farhan Ali
---
include/qemu/pci-mmio.h | 116
1 file changed, 116 insertions(+)
create mode 100644 i
On 3/21/25 10:26, Jamin Lin wrote:
Added "HACE_HASH_SRC_HI" and "HACE_HASH_DIGEST_HI", "HACE_HASH_KEY_BUFF_HI"
registers to store upper 32 bits.
Updated "write_regs" to handle 64-bit source and digest addresses.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
te
From: Prasad Pandit
Move MULTIFD_ macros to the header file so that
they are accessible from other source files.
Reviewed-by: Fabiano Rosas
Signed-off-by: Prasad Pandit
---
migration/multifd.c | 5 -
migration/multifd.h | 5 +
2 files changed, 5 insertions(+), 5 deletions(-)
v7: no c
Live migration should be terminated if the vhost-user backend crashes
before the migration completes.
Specifically, since the vhost device will be stopped when VM is stopped
before the end of the live migration, in current implementation if the
backend crashes, vhost-user device set_status() won't
Signed-off-by: Pierrick Bouvier
---
hw/arm/xlnx-zynqmp.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index d6022ff2d3d..ec2b3a41eda 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -22,9 +22,7 @@
#include "hw/intc/arm_gic_common
Register ppc_cpu_list() as CPUClass:list_cpus callback.
Reduce its scope and remove the cpu_list definition.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
---
target/ppc/cpu.h | 4
target/ppc/cpu_init.c | 3 ++-
2 files changed, 2 inser
On 3/19/25 11:22, Alex Bennée wrote:
Signed-off-by: Alex Bennée
---
include/gdbstub/commands.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/gdbstub/commands.h b/include/gdbstub/commands.h
index 40f0514fe9..bff3674872 100644
--- a/include/gdbstub/commands.h
+++ b
Polling in I/O functions can lead to nested read_from_fuse_export()
calls, overwriting the request buffer's content. The only function
affected by this is fuse_write(), which therefore must use a bounce
buffer or corruption may occur.
Note that in addition we do not know whether libfuse-internal
bibo mao writes:
On 2025/3/19 下午2:50, Markus Armbruster wrote:
>> Bibo Mao writes:
>>
>>> There is NULL pointer checking function error_propagate() already,
>>> it is not necessary to add checking for function parameter. Here remove
>>> NULL pointer checking with function parameter.
>>
>> I be
According to the v spec, a vector register cannot be used to provide source
operands with more than one EEW for a single instruction.
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvv.c.inc | 29 +
1 file changed, 29 insertions(+)
diff --git a/target/riscv/in
On 3/31/25 16:42, Pierrick Bouvier wrote:
Nothing prevent plugins to be enabled on this platform for user
binaries, only the option in the driver is missing.
Signed-off-by: Pierrick Bouvier
---
bsd-user/main.c | 12
1 file changed, 12 insertions(+)
diff --git a/bsd-user/main.c
On Mär 18 2025, Helge Deller wrote:
> My current (unreliable) way to detect it is using uname.
> The kernel string and arch name don't match:
>
> (sid_hppa)root@paq:/# uname -a
> Linux paq 6.1.0-31-amd64 #1 SMP PREEMPT_DYNAMIC Debian 6.1.128-1 (2025-02-07)
> parisc GNU/Linux
>
> (sid_hppa)root@pa
From: Mads Ynddal
hv_vcpu_set_sys_reg should only be called from the owning thread of the
vCPU, so to avoid crashes, the call to hvf_update_guest_debug is
dispatched to the individual threads.
Tested-by: Daniel Gomez
Signed-off-by: Mads Ynddal
---
accel/hvf/hvf-all.c | 7 ++-
1 file chang
From: Heinrich Schuchardt
Currently resetting the leads to resynchronizing the Goldfish RTC
with the system clock of the host. In real hardware an RTC reset
would not change the wall time. Other RTCs like pl031 do not show
this behavior.
Move the synchronization of the RTC with the system clock
Implement the Service-Call Logical Processor (SCLP) event
type Control-Program Identification (CPI) in QEMU.
Changed since v2:
- Add SPDX license tag in the new file hw/s390x/sclpcpi.c
- Store the control-program Identification data in the sclpcpi device
- Update the description of CPI attributes
Rename riscv_cpu_mmu_index() -> rx_cpu_mmu_index().
Fixes: ef5cc166da1 ("target/rx: Populate CPUClass.mmu_index")
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/rx/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/rx/cpu.c b/ta
Signed-off-by: Philippe Mathieu-Daudé
---
target/m68k/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 0065e1c1ca5..4409d8941ce 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -592,6 +592,7 @@ static const TCGCPUOps m6
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Gerd Hoffmann
Message-ID: <20250319141159.1461621-7-kra...@redhat.com>
---
docs/interop/firmware.json | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/docs/interop/firmware.json b/docs/interop/firmware.json
index 57f5
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/sparc/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 1bf00407af7..072d5da5736 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -1005
IPMI drivers use p/k suffix in variable names depending on bt or kcs.
The pci bt driver must have come from the kcs driver because it's
still using k suffixes in some cases. Rename.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Nicholas Piggin
---
hw/ipmi/pci_ipmi_bt.c | 38 +++
On Wed, Mar 26, 2025 at 08:51:20AM +0100, Cédric Le Goater wrote:
> "hw/vfio/vfio-common.h" has been emptied of most of its declarations
> by the previous changes and the only declarations left are related to
> VFIODevice. Rename it to "hw/vfio/vfio-device.h" and make the
> necessary adjustments.
Relatively few objects in qemu care about watchpoints, so split
out to a new header. Removes an instance of CONFIG_USER_ONLY
from hw/core/cpu.h.
Signed-off-by: Richard Henderson
---
include/exec/watchpoint.h | 41 +
include/hw/core/cpu.h | 30
On 23/3/25 18:37, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/avr/cpu.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index e4011004b4..538fcbc215 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -
The break in the QEMU_OPTION_machine case is mis-placed.
Not a big deal, since producing the same outcome, but
suspicious, so put it in the correct place.
Signed-off-by: Philippe Mathieu-Daudé
---
system/vl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/system/vl.c b/syst
GIC ITS can be disabled at runtime using '-M its=off',
which sets VirtMachineState::its = false. Check this
field to avoid advertising the ITS in the MADT table.
Reported-by: Udo Steinberg
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2886
Signed-off-by: Philippe Mathieu-Daudé
---
hw/
Also set the vill bit if vill was 1 beforehand.
See
https://github.com/riscv/riscv-isa-manual/blob/main/src/v-st-ext.adoc#avl-encoding
According to the spec, the above use cases are reserved, and
"Implementations may set vill in either case."
There is probably a more elegant way to handle this.
On Wed, Mar 19, 2025 at 12:30:34PM +0100, Gerd Hoffmann wrote:
> On Wed, Mar 19, 2025 at 11:07:05AM +, Daniel P. Berrangé wrote:
> > On Wed, Mar 19, 2025 at 12:01:51PM +0100, Gerd Hoffmann wrote:
> > > Signed-off-by: Gerd Hoffmann
> > > ---
> > > docs/interop/firmware.json | 5 -
> > > 1
On 3/21/25 05:57, Philippe Mathieu-Daudé wrote:
We only require the TCG_GUEST_DEFAULT_MO for MTTCG-enabled
frontends, otherwise we use a default value of TCG_MO_ALL.
In order to simplify, require the definition for all targets,
defining it for hexagon, m68k, rx, sh4 and tricore.
Signed-off-by:
On Tue, Mar 18, 2025 at 10:53:52AM +0100, Cédric Le Goater wrote:
> Gather all VFIOIOMMUFD related declarations into "iommufd.h" to
> reduce exposure of VFIO internals in "hw/vfio/vfio-common.h".
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: John Levon
regards
john
On 4/1/25 10:02, Richard Henderson wrote:
On 4/1/25 09:43, Philippe Mathieu-Daudé wrote:
Be sure to allocate the temp frame if it wasn't.
Fixes: c896fe29d6c ("TCG code generator")
Reported-by: Michael Tokarev
Reported-by: Helge Konetzka
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/
On 3/24/25 11:58, Philippe Mathieu-Daudé wrote:
Register s390_cpu_list() as CPUClass:list_cpus callback
and remove the cpu_list definition.
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/cpu.h | 3 ---
target/s390x/cpu.c | 1 +
2 files changed, 1 insertion(+), 3 deletions(-)
I rea
On 3/20/25 15:29, Pierrick Bouvier wrote:
Directly condition associated calls in target/arm/helper.c for now.
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.h| 8
target/arm/helper.c | 6 ++
2 files changed, 6 insertions(+), 8 deletions(-)
Reviewed-by: Richard Henders
On Sat, Mar 22, 2025 at 2:32 PM Sunil V L wrote:
>
> RISC-V IO Mapping Table (RIMT) is a new static ACPI table used to
> communicate IOMMU and topology information to the OS. Add support for
> creating this table when the IOMMU is present. The specification is
> frozen and available at [1].
>
> [1
Bibo Mao writes:
> Enable bios-tables-test for LoongArch virt machine, it passes to run
> with command "make check-qtest-loongarch64".
>
> Signed-off-by: Bibo Mao
> ---
> tests/qtest/meson.build | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/tests/qtest/meson.build b
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
hw/intc/armv7m_nvic.c | 2 +-
target/arm/cpu-features.h | 16
target/arm/cpu.c | 13 +
target/arm/cpu.h |
On 3/21/25 10:26, Jamin Lin wrote:
Added "src_hi" and "dest_hi" fields to "AspeedMasks" for 64-bit addresses test.
Updated "aspeed_test_addresses" to validate "HACE_HASH_SRC_HI" and
"HACE_HASH_DIGEST_HI".
Ensured correct masking of 64-bit addresses by checking both lower and upper
32-bit register
Hi Zhao,
On 3/21/25 11:43 AM, Zhao Liu wrote:
Hi Shaoqin,
Thank you very much for testing!
I tried your series on ARM64, but it reports error at compile time, here is
the error output:
qapi/kvm.json:59:Unexpected indentation.
I guess this is caused by my invalid format and sphinx complains
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 2 --
linux-user/qemu.h | 3 +++
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index d2895fb55b1..74017a5ce7c 100644
--- a/include/exe
On 4/2/25 14:23, Philippe Mathieu-Daudé wrote:
Instead of having a compile-time TARGET_SUPPORTS_MTTCG definition,
have each target set the 'mttcg_supported' field in the TCGCPUOps
structure.
Since so far we only emulate one target architecture at a time,
tcg_init_machine() gets whether MTTCG is
On 3/24/25 18:07, Pierrick Bouvier wrote:
A simple nit, maybe we could define constant for register names. This way, it can be used
in the two switch for read/access.
Which constant?
- The absolute address (0x58-0x5f)
- The i/o port address (0x38-0x3f)
- or the region offset (0-7)
? Th
On 20/03/2025 13:18, Joao Martins wrote:
External email: Use caution opening links or attachments
On 20/03/2025 11:13, Avihai Horon wrote:
On 19/03/2025 14:21, Joao Martins wrote:
External email: Use caution opening links or attachments
On 18/03/2025 09:54, Cédric Le Goater wrote:
Rename
On Tue, Apr 01, 2025 at 03:36:40PM -0500, Eric Blake wrote:
> On Thu, Mar 27, 2025 at 11:55:57AM -0400, Stefan Hajnoczi wrote:
> > On Tue, Mar 25, 2025 at 05:06:54PM +0100, Hanna Czenczek wrote:
> > > FUSE allows creating multiple request queues by "cloning" /dev/fuse FDs
> > > (via open("/dev/fuse
On 25/03/29 06:42PM, Philippe Mathieu-Daudé wrote:
> Hi Aditya,
>
> On 29/3/25 15:26, Aditya Gupta wrote:
> > <...snip...>
> >
> > --- a/target/ppc/cpu-models.c
> > +++ b/target/ppc/cpu-models.c
> > @@ -32,17 +32,22 @@
> > /* PowerPC CPU definitions
On Fri, 2025-02-07 at 14:37 +, David Woodhouse wrote:
> From: David Woodhouse
>
> At the time kvm_xen_init() is called, hyperv_enabled() doesn't yet work, so
> the correct MSR index to use for the hypercall page isn't known.
>
> Rather than setting it to the default and then shifting it late
Since we removed all definitions of cpu_list, the #ifdef
check is always true. Remove it, inlining cpu_list().
Signed-off-by: Philippe Mathieu-Daudé
---
cpu-target.c | 19 ++-
1 file changed, 6 insertions(+), 13 deletions(-)
diff --git a/cpu-target.c b/cpu-target.c
index 5947ca3
Add a unit test for vmstate_validate, which corresponds to the C version
macro: VMSTATE_VALIDATE.
Signed-off-by: Zhao Liu
---
rust/qemu-api/tests/vmstate_tests.rs | 91 +++-
1 file changed, 89 insertions(+), 2 deletions(-)
diff --git a/rust/qemu-api/tests/vmstate_tests.r
On Tue, Mar 18, 2025 at 12:11:02PM +0100, Gerd Hoffman wrote:
> Open questions:
>
> - Does the idea to use igvm parameters for the kernel hashes makes
>sense? Are parameters part of the launch measurement?
Parameters itself are fully measured, their presence is, but not their
data. This is
The digest_addr is set to "src_addr + 0x100", where src_addr is the DRAM
base address. However, the value 0x100 (16MB) is too large because the
AST1030 does not support DRAM, and its SRAM size is only 768KB.
A range size of 0x1000 (64KB) is sufficient for HACE test cases, as the test
vecto
On 3/18/25 15:19, Richard Henderson wrote:
On 3/17/25 21:51, Pierrick Bouvier wrote:
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index f89568bfa39..28de3990699 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
@@ -13,6 +13,10 @@
*
*/
+#ifdef TARGET_AARCH64
+#defi
Hi,
In this series we replace the TCG_GUEST_DEFAULT_MO definition
from "cpu-param.h" by a 'guest_default_memory_order' field in
TCGCPUOps.
Since tcg_req_mo() now accesses tcg_ctx, this impact the
cpu_req_mo() calls in accel/tcg/{cputlb,user-exec}.c.
The long term goal is to be able to use target
On Fri, Mar 21, 2025 at 3:26 PM Peter Maydell wrote:
> Tested-by: Peter Maydell
> Reviewed-by: Peter Maydell
>
> If I understand the code correctly I think you could also
> write this as "addr & 0x1f" which might be a little nicer
> as it then lines up with the "/ 0x20".
Yeah, I was undecided b
On 31/3/25 20:48, Philippe Mathieu-Daudé wrote:
On 25/3/25 23:43, Richard Henderson wrote:
Richard Henderson (11):
target/avr: Fix buffer read in avr_print_insn
>>hw/core/cpu: Use size_t for memory_rw_debug len argument
Patch 1 queued for 10.1, thanks!
Also patch 3 ;)
On 23/3/25 19:08, Richard Henderson wrote:
On 3/21/25 08:59, Philippe Mathieu-Daudé wrote:
Multi-threaded TCG only concerns system emulation.
That's not really true. User emulation simply has no option to
run in a single-threaded context.
I really don't think we should allow RV128 in user-mo
On 3/21/25 10:26, Jamin Lin wrote:
1. Disabled by default. Uncomment "#define DEBUG_HACE 1" to enable it.
2. Uses the "qemu_hexdump" API to dump the digest result.
3. Uses the "iov_hexdump" API to dump the source vector, which contains the
source plaintext.
Signed-off-by: Jamin Lin
---
hw
On Wed, Mar 26, 2025 at 07:14:31PM +0100, Eric Auger wrote:
>
>
> On 3/11/25 3:10 PM, Shameer Kolothum wrote:
> > Now that we can have multiple user-creatable smmuv3-accel devices,
> > each associated with different pci buses, update IORT ID mappings
> > accordingly.
> >
> > Signed-off-by: Shamee
On Fri, Mar 21, 2025 at 11:08:11AM +0100, Gerd Hoffman wrote:
> Hi,
>
> > > While digging around in the igvm spec I've seen there is the
> > > concept of 'parameters'. Can this be used to pass on the memory
> > > location of kernel + initrd + cmdline? Maybe the kernel hashes too
+Valentin
On 23/3/25 22:35, Daan De Meyer wrote:
We have to make sure the array of bytes read from the path= file
is null-terminated, otherwise we run into a buffer overrun later on.
Fixes: bb99f4772f54017490e3356ecbb3df25c5d4537f ("hw/smbios: support loading OEM
strings values from a file")
R
At present, Rust side has a timer binding "timer::Timer", so the vmstate
for timer should base on that binding instead of the raw
"binding::QEMUTimer".
It's possible to apply impl_vmstate_transparent for cell::Opaque and
then impl_vmstate_forward for timer::Timer. But binding::QEMUTimer
shouldn't
Dear Peter Maydell,
Thank you for your detailed response.
We will take a closer look at why, when using WFI, the affected cores still
appear to be at 100% utilization in htop. Additionally, we will investigate
whether implementing WFE in QEMU would be necessary to achieve proper CPU core
shutd
On 21.03.25 17:08, Philippe Mathieu-Daudé wrote:
Hi Heinrich,
On 21/3/25 09:12, Heinrich Schuchardt wrote:
Currently resetting leads to resynchronizing the Goldfish RTC with the
system clock of the host. In real hardware an RTC reset would not change
the wall time. Other RTCs like pl031 do not
vfio_group_list is only used in file "container.c".
Signed-off-by: Cédric Le Goater
---
include/hw/vfio/vfio-common.h | 2 --
hw/vfio/container.c | 3 ++-
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h
index
On 4/2/25 06:54, Zhang Chen wrote:
Because of the CONFIG_TCG auto enabled, the cpu type "cortex-a15"
is mistakenly set to the default AARCH64 target.
This is the correct backward compatible setting.
In essence, it means that you *must* supply a -cpu argument.
r~
Signed-off-by: Zhang Chen
On 4/3/25 15:04, Philippe Mathieu-Daudé wrote:
Instead of having a compile-time TARGET_SUPPORTS_MTTCG definition,
have each target set the 'mttcg_supported' field in the TCGCPUOps
structure.
Since so far we only emulate one target architecture at a time,
tcg_init_machine() gets whether MTTCG is
On 3/29/25 11:44 AM, Max Chou wrote:
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard
Co-authored-by: Max Chou
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --
On 3/29/25 11:44 AM, Max Chou wrote:
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard
Co-authored-by: Max Chou
Signed-off-by: Max Chou
---
With your co-authored-by tag removed:
Reviewed-by: Daniel Henrique Barboza
target/riscv/insn_trans/
On 3/29/25 11:44 AM, Max Chou wrote:
Handle the overlap of source registers with different EEWs.
The vd of vector widening mul-add instructions is one of the input
operands.
Co-authored-by: Anton Blanchard
Co-authored-by: Max Chou
Signed-off-by: Max Chou
---
With your co-authored-by tag
On 3/29/25 11:44 AM, Max Chou wrote:
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard
Co-authored-by: Max Chou
Signed-off-by: Max Chou
---
With your co-authored-by tag removed:
Reviewed-by: Daniel Henrique Barboza
target/riscv/insn_trans/
On 3/29/25 11:44 AM, Max Chou wrote:
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard
Co-authored-by: Max Chou
Signed-off-by: Max Chou
---
With your co-authored-by tag removed:
Reviewed-by: Daniel Henrique Barboza
target/riscv/insn_trans/
On 3/29/25 11:44 AM, Max Chou wrote:
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard
Co-authored-by: Max Chou
Signed-off-by: Max Chou
---
With your co-authored-by tag removed:
Reviewed-by: Daniel Henrique Barboza
target/riscv/insn_trans/
On 3/29/25 11:44 AM, Max Chou wrote:
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard
Co-authored-by: Max Chou
Signed-off-by: Max Chou
---
With your co-authored-by tag removed:
Reviewed-by: Daniel Henrique Barboza
target/riscv/insn_trans/t
On 3/29/25 11:44 AM, Max Chou wrote:
According to the v spec, the encodings of vcomoress.vm and vector
mask-register logical instructions with vm=0 are reserved.
Signed-off-by: Max Chou
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/insn32.decode | 18 +-
1 fil
The dwc3 hardware requires the ERSTBA address to be written in
high-low order.
>From information found in the Linux kernel:
[Synopsys]- The host controller was design to support ERST setting
during the RUN state. But since there is a limitation in controller
in supporting separate ERSTBA_HI and E
According to the XHCI specification, ERSTBA should be written in Low-High
order. The Linux kernel writes the high word first. This results in an
initialization failure.
The following information is found in the Linux kernel commit log.
[Synopsys]- The host controller was design to support ERST se
This series is needed to support the USB interface on imx8mp-evk when
booting the Linux kernel.
According to the XHCI specification, ERSTBA should be written in Low-High
order. The Linux kernel writes the high word first. This results in an
initialization failure.
The following information is fou
Move the TCG-specific cpu-ldst*.h headers to
the accel/tcg/ namespace.
Philippe Mathieu-Daudé (3):
exec: Restrict 'cpu-ldst-common.h' to accel/tcg/
exec: Restrict 'cpu_ldst.h' to accel/tcg/
exec: Do not include 'accel/tcg/cpu-ldst.h' in 'exec-all.h'
bsd-user/qemu.h
On 2/4/25 23:22, Daniel Henrique Barboza wrote:
On 4/2/25 5:51 PM, Philippe Mathieu-Daudé wrote:
As Richard mentioned:
We should allow RV128 in user-mode at all until there's a
kernel abi for it.
By the context I suppose Richard said 'We shouldn't allow RV128 ...'.
If this was said i
On 3/23/25 10:37, Richard Henderson wrote:
Communicate the offset of io within the first page between the
board, the cpu, and the translator. So far this is always 0.
This will be used to optimize memory layout.
Signed-off-by: Richard Henderson
---
target/avr/cpu.h | 2 ++
hw/avr/atme
Currently resetting leads to resynchronizing the Goldfish RTC with the
system clock of the host. In real hardware an RTC reset would not change
the wall time. Other RTCs like pl031 do not show this behavior.
Move the synchronization of the RTC with the system clock to the instance
realization.
Re
On Mon, Mar 31, 2025 at 01:14:33PM +0100, Daniel P. Berrangé wrote:
> On Mon, Mar 31, 2025 at 07:52:33AM -0400, Stefan Hajnoczi wrote:
> > On Mon, Mar 31, 2025 at 6:39 AM Alex Bennée wrote:
> > > So what do people think? Where would be a good place for common test
> > > repository to live?
> >
>
On 4/3/25 12:31, Philippe Mathieu-Daudé wrote:
On 3/4/25 20:22, Pierrick Bouvier wrote:
On 4/2/25 15:23, Philippe Mathieu-Daudé wrote:
This series is more useful for heterogeneous emulation preparation
than single binary, because it allows non-ARM hw/ code to configure
ARM cores, so not using t
Currently, users define multiple local variables within different if-statements.
To improve readability and maintain consistency in variable naming, rename the
variables accordingly.
Introduced "sg_addr" to clearly indicate the scatter-gather mode buffer address.
Signed-off-by: Jamin Lin
---
hw/
The comment about not being able to define a field with
zero bits is out of date since 94597b6146f3
("decodetree: Allow !function with no input bits").
This fixes the missing load of imm in the disassembler.
Cc: qemu-sta...@nongnu.org
Fixes: 9d8caa67a24 ("target/avr: Add support for disassembling
On 3/25/25 08:40, Philippe Mathieu-Daudé wrote:
Replace the single ldtul_p() call by a generic ldn_p() one.
No logical change.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/gdbstub.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/mips/gdbstub.c b/
Rename these routines :
vfio_devices_all_device_dirty_tracking_started ->
vfio_dirty_tracking_devices_is_started_all
vfio_devices_all_dirty_tracking_started->
vfio_dirty_tracking_devices_is_started
vfio_devices_all_device_dirty_tracking ->
vfio_dirty_tracking_devices_is_su
On 24/03/2025 17.32, Philippe Mathieu-Daudé wrote:
On 24/3/25 10:30, Thomas Huth wrote:
On 23/03/2025 23.40, Philippe Mathieu-Daudé wrote:
Register sparc_cpu_list() as CPUClass:list_cpus callback
and remove the cpu_list definition.
Copy-n-paste error in both, subject and patch description: Th
Add a unit test to cover some patterns accepted by vmstate_of and
vmstate_struct macros, which correspond to the following C version
macros:
* VMSTATE_BOOL_V
* VMSTATE_U64
* VMSTATE_STRUCT_VARRAY_UINT8
* (no C version) MULTIPLY variant of VMSTATE_STRUCT_VARRAY_UINT32
* VMSTATE_ARRAY
Signed-o
This patch captures the error of vhost_virtqueue_stop() in vhost_dev_stop()
and returns the error upward.
Specifically, if QEMU is disconnected from the vhost backend, some actions
in vhost_dev_stop() will fail, such as sending vhost-user messages to the
backend (GET_VRING_BASE, SET_VRING_ENABLE)
On 4/1/25 01:09, Philippe Mathieu-Daudé wrote:
Since commits 32a8ea12fab..90b7022e698 (target: "Split out
TARGET_env_mmu_index"), target's memory_rw_debug() callbacks
use the target's TARGET_env_mmu_index(), not the generic
CPUClass::mmu_index() callback. Update the documentation.
Signed-off-by:
Hiya, this series turns on automated linting for scripts/qapi,
docs/sphinx/qapidoc.py and docs/sphinx/qapi_domain.py.
This includes flake8/isort/pylint/mypy for scripts/qapi, but omits mypy
from the Sphinx plugins owing to my inability to strictly type the
extensions given the wide versions of Sph
Implement the Service-Call Logical Processor (SCLP) event
type Control-Program Identification (CPI) in QEMU. This
event is used to send CPI identifiers from the guest to the
host. The CPI identifiers are: system type, system name,
system level and sysplex name.
System type: operating system of the
Bibo Mao writes:
> This patch set solves errors reported by coccinelle tool with commands:
> spatch --sp-file scripts/coccinelle/*.cocci --dir target/loongarch/
> spatch --sp-file scripts/coccinelle/*.cocci --dir hw/loongarch/
>
> The main problem is that qemu should fail to run when feature
Hi,
On 3/26/25 5:38 PM, Eugenio Perez Martin wrote:
On Mon, Mar 24, 2025 at 3:00 PM Sahil Siddiq wrote:
[...]
Link: https://lists.nongnu.org/archive/html/qemu-devel/2024-10/msg05106.html
Link: https://lore.kernel.org/r/20210602021536.39525-4-jasow...@redhat.com
Link: 1225c216d954 ("vp_vdpa: al
On 24/3/25 19:46, Philippe Mathieu-Daudé wrote:
Register s390_cpu_list() as CPUClass:list_cpus callback
and remove the cpu_list definition.
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
Am 5. April 2025 17:26:14 UTC schrieb Guenter Roeck :
>On 4/5/25 07:25, Philippe Mathieu-Daudé wrote:
>> Hi Guenter,
>>
>> On 5/4/25 16:00, Guenter Roeck wrote:
>>> This series is needed to support the USB interface on imx8mp-evk when
>>> booting the Linux kernel.
>>>
>>> According to the XHCI
Introduced "test_sha384_ast2600" to validate SHA-384 hashing.
Added "test_sha384_sg_ast2600" for scatter-gather SHA-384 verification.
Implemented "test_sha384_accum_ast2600" to test SHA-384 accumulation.
Registered new test cases in "main" to ensure execution.
Signed-off-by: Jamin Lin
---
tests/
Signed-off-by: Pierrick Bouvier
---
accel/tcg/tb-internal.h | 1 -
include/exec/cpu-all.h | 22 --
include/hw/core/cpu.h | 2 +-
include/qemu/bswap.h| 2 +-
target/alpha/cpu.h | 2 --
target/arm/cpu.h| 2 --
target/avr/cpu.h| 2 --
target/hexa
At present qemu creates a device tree automatically with the 'virt' generic
virtual platform. This is very convenient in most cases but there is not
much control over what is generated.
Add a way to provide a device tree binary file with additional properties
to add before booting. This provides f
On 4/5/25 12:28, Bernhard Beschow wrote:
Am 5. April 2025 17:26:14 UTC schrieb Guenter Roeck :
On 4/5/25 07:25, Philippe Mathieu-Daudé wrote:
Hi Guenter,
On 5/4/25 16:00, Guenter Roeck wrote:
This series is needed to support the USB interface on imx8mp-evk when
booting the Linux kernel.
Ac
Full Unit Access (FUA) is an optimization where a disk write with the
flag set will be persisted to disk immediately instead of potentially
remaining in the disk's write cache.
This commit address the todo task
for using pwritev2() with RWF_DSYNC in the thread pool section of
raw_co_prw(), if pwri
From: Joel Stanley
Guest code was performing a byte load to the SCU MMIO region, leading
to the guest code crashing (it should be using proper accessors, but
that is not Qemu's bug). Hardware and the documentation[1] both agree
that byte loads are okay, so change all of the aspeed SCU devices to
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