On 3/11/25 09:28, Cornelia Huck wrote:
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 16
target/arm/cpu.c | 15 +--
target/arm/cpu.h | 2 --
target/arm/cpu64.c| 4 ++--
target
On 3/11/25 09:28, Cornelia Huck wrote:
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 74 +++
target/arm/cpu.h | 4 ---
target/arm/cpu64.c| 8 ++---
target/arm/helper.c | 8
On 3/11/25 17:44, Joao Martins wrote:
On 05/03/2025 13:13, Cédric Le Goater wrote:
Joao,
On 3/5/25 12:16, Joao Martins wrote:
On 14/02/2025 13:05, Cédric Le Goater wrote:
+Kirti
+Joao
On 2/13/25 22:45, Alex Williamson wrote:
+
+ /*
+ * Migration support
+ */
+ object_class_pro
Hi Phil and Bernhard,
I would like to apologize for not including you in the initial email regarding
the RTC PCF8563 patch. This was an oversight on my part, and I regret any
inconvenience this may have caused.
От: Ilya Chichkov
Отправлено: 10 марта 2025 г. 14:
On 3/4/25 10:13, Zhao Liu wrote:
-const fn as_mut_ptr(&self) -> *mut Self {
-self as *const Timer as *mut _
+/// Create a `Timer` struct without initializing it.
+///
+/// # Safety
+///
+/// The timer must be initialized before it is armed with
+/// [`modify`](
On Tue, Feb 25, 2025 at 10:55 AM Sebastian Huber
wrote:
>
> Mention that running the HSS no longer works. Document the changed boot
> options. Reorder documentation blocks. Update URLs.
>
> Signed-off-by: Sebastian Huber
Acked-by: Alistair Francis
Alistair
> ---
> docs/system/riscv/microc
Sphinx prior to v4.0 uses different classes for rendering elements of
documentation objects; add some compatibility classes to use the right
node classes conditionally.
Signed-off-by: John Snow
---
docs/sphinx/compat.py | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
dif
On 3/9/2025 8:44 PM, Michael S. Tsirkin wrote:
On Tue, Mar 04, 2025 at 06:37:47PM +, Suravee Suthikulpanit wrote:
The QEMU-emulated AMD IOMMU PCI device is implemented based on the AMD I/O
Virtualization Technology (IOMMU) Specification [1]. The PCI id for this
device is platform-specific
Signed-off-by: Pierrick Bouvier
---
system/memory.c| 22 +++---
system/meson.build | 2 +-
2 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/system/memory.c b/system/memory.c
index 4c829793a0a..b401be8b5f1 100644
--- a/system/memory.c
+++ b/system/memory.c
@@ -3
On 11/03/25 14:09, Nicholas Piggin wrote:
On Tue Mar 11, 2025 at 1:33 AM AEST, Cédric Le Goater wrote:
On 3/10/25 15:59, Aditya Gupta wrote:
On 10/03/25 17:15, Cédric Le Goater wrote:
On 3/10/25 11:31, Aditya Gupta wrote:
<...snip...>
pc-bios/skiboot.lid | Bin 2527328 -> 2527424 bytes
Hi,
On Tue, 11 Mar 2025 at 01:28, Fabiano Rosas wrote:
> They occur when cleanup code is allowed to run when resources have not
> yet been allocated or while the resources are still being accessed.
>
> Having the shutdown routine at a single point when it's clear everything
> else is ready for sh
Factor out duplicated code to a single helper. More users to come.
Signed-off-by: Greg Kurz
v2: - simplified local_fid_fd()
---
hw/9pfs/9p-local.c | 23 ++-
1 file changed, 10 insertions(+), 13 deletions(-)
diff --git a/hw/9pfs/9p-local.c b/hw/9pfs/9p-local.c
index 928523af
Add an ftruncate operation to the fs driver and use if when a fid has
a valid file descriptor. This is required to support more cases where
the client wants to do an action on an unlinked file which it still
has an open file decriptor for.
Only 9P2000.L was considered.
Reviewed-by: Christian Scho
Add an futimens operation to the fs driver and use if when a fid has
a valid file descriptor. This is required to support more cases where
the client wants to do an action on an unlinked file which it still
has an open file decriptor for.
Only 9P2000.L was considered.
Reviewed-by: Christian Schoe
QEMU 9.2 already fixed the long standing limitation of failing fstat() on
unlinked files. This series does something similar for ftruncate().
The following program can be straced inside the guest with a shared fs in
passthrough mode over 9p2000.L.
int main(void)
{
struct stat st;
v9fs_getattr() currently peeks into V9fsFidOpenState to know if a fid
has a valid file descriptor or directory stream. Even though the fields
are accessible, this is an implementation detail of the local backend
that should not be manipulated directly by the server code.
Abstract that with a new h
From: Christian Schoenebeck
Add and implement functions to 9pfs test client for sending a 9p2000.L
'Tsetattr' request and receiving its 'Rsetattr' response counterpart.
Signed-off-by: Christian Schoenebeck
Signed-off-by: Greg Kurz
---
tests/qtest/libqos/virtio-9p-client.c | 49 +++
On 11/03/2025 17:43, Cédric Le Goater wrote:
> On 3/11/25 17:44, Joao Martins wrote:
>> On 05/03/2025 13:13, Cédric Le Goater wrote:
>>> Joao,
>>>
>>> On 3/5/25 12:16, Joao Martins wrote:
On 14/02/2025 13:05, Cédric Le Goater wrote:
> +Kirti
> +Joao
>
> On 2/13/25 22:45, Alex W
The intent behind the x-device-dirty-page-tracking option is twofold:
1) development/testing in the presence of VFs with VF dirty page tracking
2) deliberately choosing platform dirty tracker over the VF one.
Item 2) scenario is useful when VF dirty tracker is not as fast as
IOMMU, or there's so
On 3/11/25 09:28, Cornelia Huck wrote:
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
hw/intc/armv7m_nvic.c | 12 ++--
target/arm/cpu-features.h | 36 +-
target/arm/cpu.c | 24 +++
target/arm/cpu.h | 7 --
target/arm/cpu64
On 3/11/25 09:28, Cornelia Huck wrote:
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 6 +++---
target/arm/cpu.h | 1 -
target/arm/cpu64.c| 7 ++-
target/arm/helper.c | 2 +-
target/arm/kvm.c | 3 +
On 3/10/25 21:08, Pierrick Bouvier wrote:
They are now accessible through exec/memory.h instead, and we make sure
all variants are available for common or target dependent code.
Move stl_phys_notdirty function as well.
Cached endianness agnostic version rely on st/ld*_p, which is available
throu
Add an ftruncate operation to the fs driver and use if when a fid has
a valid file descriptor. This is required to support more cases where
the client wants to do an action on an unlinked file which it still
has an open file decriptor for.
Only 9P2000.L was considered.
Signed-off-by: Greg Kurz
-
On 3/10/25 08:27, Philippe Mathieu-Daudé wrote:
On 10/3/25 15:09, BALATON Zoltan wrote:
On Mon, 10 Mar 2025, Philippe Mathieu-Daudé wrote:
The previous commit removed the single use of instance
setting the "endianness" property.
Since classes can register their io_ops with correct
endianness,
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250210133134.90879-5-phi...@linaro.org>
---
target/riscv/cpu.h | 2 +-
target/riscv/cpu.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 616c3
Signed-off-by: Mario Fleischmann
---
gdbstub/gdbstub.c | 7 ---
include/exec/gdbstub.h | 8 +++-
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index 282e13e163..8166510f06 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@
On 3/10/25 21:08, Pierrick Bouvier wrote:
Will allow to make system/memory.c common later.
Signed-off-by: Pierrick Bouvier
---
include/exec/memory.h | 16
1 file changed, 4 insertions(+), 12 deletions(-)
Reviewed-by: Richard Henderson
r~
diff --git a/include/exec/mem
On 3/10/25 21:08, Pierrick Bouvier wrote:
They are now accessible through exec/memory.h instead, and we make sure
all variants are available for common or target dependent code.
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 12
include/exec/memory_ldst.h.in
On 2/21/25 21:24, Vaibhav Jain wrote:
Add support for reporting Hostwide state counters for nested KVM pseries
guests running with 'cap-nested-papr' on Qemu-TCG acting as
L0-hypervisor. The Hostwide state counters are statistics about state that
L0-hypervisor maintains for the L2-guests and re
Am 7. März 2025 19:18:34 UTC schrieb Bernhard Beschow :
>
>
>Am 4. März 2025 18:53:10 UTC schrieb Bernhard Beschow :
>>
>>
>>Am 23. Februar 2025 11:47:08 UTC schrieb Bernhard Beschow :
>>>The implementation just allows Linux to determine date and time.
>>>
>>>Signed-off-by: Bernhard Beschow
>>>
On Tue Dec 10, 2024 at 10:05 AM AEST, Michael Kowal wrote:
> From: Glenn Miles
>
> END notification processing has an escalation path. The escalation is
> not always an END escalation but can be an ESB escalation.
>
> Also added a check for 'resume' processing which log a message stating it
> nee
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/s390x/s390-skeys.c | 39 +--
On 3/11/25 09:28, Cornelia Huck wrote:
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
hw/intc/armv7m_nvic.c | 5 +-
target/arm/cpu-features.h | 10 ++--
target/arm/cpu.c | 8 +--
target/arm/cpu.h | 3 -
target/arm/cpu64.c|
On 3/11/25 09:28, Cornelia Huck wrote:
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
hw/intc/armv7m_nvic.c | 2 +-
target/arm/cpu-features.h | 16
target/arm/cpu.c | 13 +
target/arm/cpu.h | 2 --
target/arm
On 3/11/25 09:28, Cornelia Huck wrote:
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
hw/intc/armv7m_nvic.c | 8 ++--
target/arm/cpu-features.h | 18
target/arm/cpu.h | 6 ---
target/arm/cpu64.c| 16 +++
target/arm/helper.c
Support asynchronous fencing feature of virglrenderer. It allows Qemu to
handle fence as soon as it's signalled instead of periodically polling
the fence status. This feature is required for enabling DRM context
support in Qemu because legacy fencing mode isn't supported for DRM
contexts in virglre
On Mon, Mar 10, 2025 at 02:31:18PM +0100, Philippe Mathieu-Daudé wrote:
> Reduce misc-target.json by one target specific command.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> qapi/machine.json | 18 ++
> qapi/misc-target.json | 19 ---
> hw/core
On 3/10/25 21:08, Pierrick Bouvier wrote:
Defining functions allows to use them from common code, by not depending
on TARGET_BIG_ENDIAN.
Remove previous macros from exec/cpu-all.h.
By moving them out of cpu-all.h, we'll be able to break dependency on
cpu.h for memory related functions coming in n
On 05/03/2025 17.59, Pierrick Bouvier wrote:
On 3/5/25 07:39, Philippe Mathieu-Daudé wrote:
Introduce an API to get information specific to a binary
from the binary name (argv[0]).
Initialize it from qemu_init() on system emulation.
What we want here is more a include/qemu/target_info.h, whi
John Snow writes:
> This series is a "minimum viable" version of the new QAPI documentation
> system. It does the bare minimum under the new framework, saving the
> fancy features like the inliner for later. This version does add
> cross-references for all QAPI definitions and a shiny new QAPI In
On 3/10/25 21:08, Pierrick Bouvier wrote:
we'll use it in system/memory.c.
Signed-off-by: Pierrick Bouvier
---
include/exec/memory.h | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson
r~
All instances of TYPE_IMX_USDHC set vendor=SDHCI_VENDOR_IMX.
No need to special-case it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: BALATON Zoltan
Reviewed-by: Bernhard Beschow
Message-Id: <20250308213640.13138-3-phi...@linaro.org>
---
include/hw/sd/sdhci.h | 1 -
hw/arm/fsl-imx25.c
Rather than checking ACPI availability at compile time by
checking the CONFIG_ACPI definition from CONFIG_DEVICES,
check at runtime via acpi_builtin().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: David Hildenbrand
Reviewed-by: Pierrick Bouvier
Message-Id: <20250307223949.54040-5-phi...@l
From: Peter Maydell
When the smc91c111 transmits a packet, it must read a control byte
which is at the end of the data area and CRC. However, we don't
sanitize the length field in the packet buffer, so if the guest sets
the length field to something large we will try to read past the end
of the
From: BALATON Zoltan
The interrupt enable registers are not reset to 0 on Freescale eSDHC
but some bits are enabled on reset. At least some U-Boot versions seem
to expect this and not initialise these registers before expecting
interrupts. Use existing vendor property for Freescale eSDHC and set
acpi_builtin() can be used to check at runtime whether
the ACPI subsystem is built in a qemu-system binary.
Reviewed-by: Ani Sinha
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20250307223949.54040-3-phi...@linaro.org>
---
include/hw/acpi/acpi.h | 3 +++
hw/acpi/acpi-stub.c| 5 +
h
On Tue, Mar 11, 2025 at 03:33:23PM +, Daniel P. Berrangé wrote:
> On Tue, Mar 11, 2025 at 11:20:50AM -0400, Peter Xu wrote:
> > On Tue, Mar 11, 2025 at 08:13:16AM +, Daniel P. Berrangé wrote:
> > > On Mon, Mar 10, 2025 at 04:03:26PM -0400, Peter Xu wrote:
> > > > On Mon, Mar 10, 2025 at 07:
On 10.03.2025 10:23, Cédric Le Goater wrote:
On 3/10/25 09:17, Avihai Horon wrote:
On 07/03/2025 12:57, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
Wire data commonly use BE byte order (including in the existing migration
On Thu, 6 Mar 2025 02:33:37 +
Alireza Sanaee via wrote:
Hi everyone,
v1 -> v2: I just rebased this patchset which initially was posted in
Sep 2024.
Thanks,
Alireza
> OS like Linux is using PPTT processor node's identical implementation
> flag [1] to infer whether the whole system or a cert
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/tswap.h | 11 ++-
cpu-target.c | 1 +
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/include/exec/tswap.h b/include/exec/tswap.h
index ecd4faef015..2683da0adb7 100644
--- a/include/ex
On 3/9/25 21:58, Pierrick Bouvier wrote:
This is needed for next commits (especially when implementing st/ld
primitives which will use this function).
As well, remove reference to TARGET_BIG_ENDIAN, as we are about to
remove this dependency.
Where is the TARGET_BIG_ENDIAN reference being remove
Signed-off-by: Pierrick Bouvier
---
system/ioport.c| 1 -
system/meson.build | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/system/ioport.c b/system/ioport.c
index 55c2a752396..89daae9d602 100644
--- a/system/ioport.c
+++ b/system/ioport.c
@@ -26,7 +26,6 @@
*/
#inc
In linux-user/arm/cpu_loop.c we define a full set of get/put
macros for both code and data (since the endianness handling
is different between the two). However the only one we actually
use is get_user_code_u32(). Remove the rest.
We leave a comment noting how data-side accesses should be handled
Newer Arm CPUs need not implement AArch32 at all exception levels
(and Armv9 forbids implementing AArch32 at any EL except EL0).
All our current CPU models implement both AArch32 and AArch64
at every exception levels, so we currently get away with failing
to enforce that the guest isn't trying to d
From: Peter Maydell
For accesses to the 91c111 data register, the address within the
packet's data frame is determined by a combination of the pointer
register and the offset used to access the data register, so that you
can access data at effectively wider than byte width. The pointer
register'
We shouldn't use target specific globals for machine properties.
These ones could be desugarized, as explained in [*]. While
certainly doable, not trivial nor my priority for now. Just move
them to a different file to clarify they are *globals*, like the
generic globals residing in system/globals.c
There is no TARGET_ARM_64 definition. Luckily enough,
when TARGET_AARCH64 is defined, TARGET_ARM also is.
Fixes: 733766cd373 ("hw/arm: introduce xenpvh machine")
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Reviewed-by: Richard Henderson
Message-Id: <20250305153929.43687-
They are now accessible through exec/memory.h instead, and we make sure
all variants are available for common or target dependent code.
Move stl_phys_notdirty function as well.
Cached endianness agnostic version rely on st/ld*_p, which is available
through tswap.h.
Reviewed-by: Richard Henderson
They are now accessible through exec/memory.h instead, and we make sure
all variants are available for common or target dependent code.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 12
include/exec/memory_ldst.h.inc | 4
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
system/ioport.c| 1 -
system/meson.build | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/system/ioport.c b/system/ioport.c
index 55c2a752396..89daae9d602 100644
--- a/system/ioport.c
+++ b/system/ioport.
Will allow to make system/memory.c common later.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/memory.h | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index da21e9150b5..069021
The main goal of this series is to be able to call any memory ld/st function
from code that is *not* target dependent. As a positive side effect, we can
turn related system compilation units into common code.
The first 5 patches remove dependency of memory API to cpu headers and remove
dependency
Defining functions allows to use them from common code, by not depending
on TARGET_BIG_ENDIAN.
Remove previous macros from exec/cpu-all.h.
By moving them out of cpu-all.h, we'll be able to break dependency on
cpu.h for memory related functions coming in next commits.
Reviewed-by: Richard Henderson
Needed so compilation units including it can be common.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/memory-internal.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h
index 100c1237ac2..b729f
On Tue, Mar 11, 2025 at 02:10:28PM +, Shameer Kolothum wrote:
> +/*
> + * Copyright (c) 2025 Huawei Technologies R & D (UK) Ltd
> + * Copyright (C) 2025 NVIDIA
+ * Copyright (C) 2025 NVIDIA CORPORATION & AFFILIATES
> + * Written by Nicolin Chen, Shameer Kolothum
(Thanks for adding my name!)
On Fri, Mar 07, 2025 at 11:16:31PM +0100, Kevin Wolf wrote:
> For block drivers that don't advertise FUA support, we already call
> bdrv_co_flush(), which considers BDRV_O_NO_FLUSH. However, drivers that
> do support FUA still see the FUA flag with BDRV_O_NO_FLUSH and get the
> associated performan
From: John Snow
Sphinx prior to v4.0 uses different classes for rendering elements of
documentation objects; add some compatibility classes to use the right
node classes conditionally.
Signed-off-by: John Snow
Message-ID: <20250311034303.75779-10-js...@redhat.com>
Acked-by: Markus Armbruster
S
On 3/6/25 11:38, Jamin Lin wrote:
Added a new method "start_ast2700_test" to the "AST2x00MachineSDK" class and
this method centralizes the logic for starting the AST2700 test, making it
reusable for different test cases.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
In MCD, core-specific operations require an open connection to the core.
This commit implements the necessary operations to open and close the
connection to cores.
Signed-off-by: Mario Fleischmann
---
mcd/mcdserver.c | 176 ---
mcd/mcdstub_qapi.c| 11
Mostly revert commit c80cafa0c73 ("system: Add qemu_init_arch_modules")
but using target_name() instead of the target specific 'TARGET_NAME'
definition.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250305005225.95051-3-phi...@linaro.org>
---
include/system
On 3/9/25 21:58, Pierrick Bouvier wrote:
This function is used by system/physmem.c will be turn into common code
in next commit.
Signed-off-by: Pierrick Bouvier
---
include/system/kvm.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
is already included by "system/kvm.h" in the next line.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Reviewed-by: Richard Henderson
Reviewed-by: Cédric Le Goater
Reviewed-by: Eric Auger
Message-Id: <20250307180337.14811-3-phi...@linaro.org>
---
hw/vfio/spapr.c | 3 ---
On 2025/3/10 15:13, Cédric Le Goater wrote:
> Tomita,
>
> On 3/7/25 19:37, Tomita Moeko wrote:
>> On 2025/3/7 6:49, Alex Williamson wrote:
>>> On Fri, 7 Mar 2025 02:01:27 +0800
>>> Tomita Moeko wrote:
>>>
So far, IGD-specific quirks all require enabling legacy mode, which is
toggled by
John Snow writes:
> This is the true top-level processor for the new transmogrifier;
> responsible both for generating the intermediate rST and then running
> the nested parse on that generated document to produce the final
> docutils tree that is then - very finally - postprocessed by sphinx for
Support asynchronous fencing feature of virglrenderer. It allows Qemu to
handle fence as soon as it's signalled instead of periodically polling
the fence status. This feature is required for enabling DRM context
support in Qemu because legacy fencing mode isn't supported for DRM
contexts in virglre
This function is used by system/physmem.c will be turn into common code
in next commit.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/system/kvm.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/system/kvm.h b/include/system/kvm.h
i
Previous commit changed files relying transitively on it.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/exec-all.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index dd5c40f2233..19b0eda44a7 100644
--- a/i
On Tue, Mar 11, 2025 at 02:10:33PM +, Shameer Kolothum wrote:
> diff --git a/include/hw/arm/smmuv3-accel.h b/include/hw/arm/smmuv3-accel.h
> index 56fe376bf4..86c0523063 100644
> --- a/include/hw/arm/smmuv3-accel.h
> +++ b/include/hw/arm/smmuv3-accel.h
> @@ -16,6 +16,10 @@
> #define TYPE_ARM_S
On 3/10/25 08:17, Richard Henderson wrote:
On 3/9/25 21:58, Pierrick Bouvier wrote:
They are now accessible through exec/memory.h instead, and we make sure
all variants are available for common or target dependent code.
...
diff --git a/include/exec/memory_ldst.h.inc b/include/exec/memory_ldst
Add reset support with ipi object, register reset callback and clear
internal registers when virt machine resets.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_ipi.c | 29 +
include/hw/intc/loongarch_ipi.h | 1 +
2 files changed, 30 insertions(+)
diff --git
Fixes: ca056f4499c2 (Python: Drop support for Python 3.7)
Signed-off-by: Markus Armbruster
Message-ID: <20250227080757.3978333-2-arm...@redhat.com>
Reviewed-by: Daniel P. Berrangé
---
docs/about/build-platforms.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/about/bu
Nabih,
On 3/6/25 01:04, Nabih Estefan wrote:
Setting BIT6 in VGA0 SCRATCH register will indicate that the ddr traning
is done, therefore skipping the u-boot-spl dram_init() process.
Signed-off-by: Jamin Lin
Signed-off-by: Troy Lee
Reviewed-by: Cédric Le Goater
Tested-by: Nabih Estefan
Th
From: John Snow
This class is a generic, top-level directive for documenting some kind
of QAPI thingamajig that we expect to go into the Index. This class
doesn't do much by itself, and it isn't yet associated with any
particular directive.
handle_signature(), _object_hierarchy_parts() and _toc_
In MCD, all accesses to register or memory are issued over transaction lists.
This commit implements three types of transactions:
* register access
* logical memory access (with MMU)
* physical memory access (no MMU)
Signed-off-by: Mario Fleischmann
---
mcd/libmcd_qapi.c | 128
Hi Zoltan,
On 3/10/25 06:23, BALATON Zoltan wrote:
On Sun, 9 Mar 2025, Pierrick Bouvier wrote:
The main goal of this series is to be able to call any memory ld/st function
from code that is *not* target dependent.
Why is that needed?
this series belongs to the "single binary" topic, where
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
While the (intno << shift) expression is correct for indexing the IDT based on
whether Long Mode is active, the error code itself was unchanged with AMD64,
and is still the index with 3 bits of metadata in the bottom.
Found when running a Xen unit test, all under QEMU. The unit test objected to
b
Hi Zhao,
On 3/11/25 6:51 AM, Zhao Liu wrote:
> Hi Dongli,
>
+/*
+ * If KVM_CAP_PMU_CAPABILITY is not supported, there is no way to
+ * disable the AMD pmu virtualization.
+ *
+ * If KVM_CAP_PMU_CAPABILITY is supported !cpu->enable_pmu
+ * indi
From: Peter Maydell
Now we have a constant for the maximum packet size, we can use it
to replace various hardcoded 2048 values.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250228174802.1945417-4-peter.mayd...@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé
From: Jiqian Chen
In PVH dom0, when passthrough a device to domU, QEMU code
xen_pt_realize->xc_physdev_map_pirq wants to use gsi, but in current codes
the gsi number is got from file /sys/bus/pci/devices//irq, that is
wrong, because irq is not equal with gsi, they are in different spaces, so
pirq
Add cache topology to PPTT table. With this patch, both ACPI PPTT table
and device tree will represent the same cache topology given users
input.
Signed-off-by: Alireza Sanaee
Co-developed-by: Jonathan Cameron
Signed-off-by: Jonathan Cameron
---
hw/acpi/aml-build.c| 205 +++
gs/hw-misc-20250311
for you to fetch changes up to a5368f2e00c81c8c2b5dd0318293b11f8ed7c7c8:
hw/sd/sdhci: Remove need for SDHCI_VENDOR_FSL definition (2025-03-11 20:03:30
+0100)
Misc HW patches
- Set correct values for MPC8569E'
qemu_arch_available() is a bit simpler to understand while
reviewing than the undocumented arch_type variable.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20250305005225.95051-5-phi...@linaro.org>
---
include/system/arch_init.h | 2 +-
hw/scsi/scsi-disk.c
From: Peter Maydell
The smc91c111 uses packet numbers as an index into its internal
s->data[][] array. Valid packet numbers are between 0 and 3, but
the code does not generally check this, and there are various
places where the guest can hand us an arbitrary packet number
and cause an out-of-boun
we'll use it in system/memory.c.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/memory.h | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 069021ac3ff..70177304a92 100644
-
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/ram_addr.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h
index 7c011fadd11..098fccb5835 100644
--- a/include/exec/ram_addr.h
+++ b/inclu
On Mon, Mar 10, 2025 at 15:33:02 +0100, Kevin Wolf wrote:
> Am 13.02.2025 um 19:00 hat Stefan Hajnoczi geschrieben:
> > Allow virtio-scsi virtqueues to be assigned to different IOThreads. This
> > makes it possible to take advantage of host multi-queue block layer
> > scalability by assigning virtq
On Tue, 4 Mar 2025 18:37:47 +
Suravee Suthikulpanit wrote:
> The QEMU-emulated AMD IOMMU PCI device is implemented based on the AMD I/O
> Virtualization Technology (IOMMU) Specification [1]. The PCI id for this
> device is platform-specific.
>
> Currently, the QEMU-emulated AMD IOMMU device
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