Queued with imports tidied up. Thanks!
From: Daniel P. Berrangé
This updates the QAPI code generation to refer to 'features' instead
of 'special_features', in preparation for generalizing their exposure.
Signed-off-by: Daniel P. Berrangé
Message-ID: <20250205123550.2754387-4-berra...@redhat.com>
Reviewed-by: Markus Armbruster
[Impo
From: Zhang Boyang
The upper bound of pointer position in InputMoveEvent should be 0x7fff,
according to INPUT_EVENT_ABS_MAX.
Signed-off-by: Zhang Boyang
Message-ID: <20250116104433.12114-1-zhangboyang...@gmail.com>
Acked-by: Markus Armbruster
[Phrasing tweak squashed in]
Signed-off-by: Markus
From: Daniel P. Berrangé
The "special_features" field / parameter holds the subset of schema
features that are for internal code use. Specifically 'DEPRECATED'
and 'UNSTABLE'.
This special casing of internal features is going to be removed, so
prepare for that by renaming to 'features'. Using a
From: Daniel P. Berrangé
This replaces use of the constants from the QapiSpecialFeatures
enum, with constants from the auto-generate QapiFeatures enum
in qapi-features.h
The 'deprecated' and 'unstable' features still have a little bit of
special handling, being force defined to be the 1st + 2nd
Hi Peter,
On 2/7/25 5:58 PM, Peter Maydell wrote:
> On Fri, 7 Feb 2025 at 16:50, Eric Auger wrote:
>>
>>
>>
>> On 2/7/25 5:37 PM, Peter Maydell wrote:
>>> On Thu, 6 Feb 2025 at 14:23, Eric Auger wrote:
Currently the iommu may be reset before the devices
it protects. For example this
From: Daniel P. Berrangé
When we shortly expose all feature names to code, it will be valid to
include a '-', which must be translated to a '_' for the enum constants.
Signed-off-by: Daniel P. Berrangé
Message-ID: <20250205123550.2754387-2-berra...@redhat.com>
Reviewed-by: Markus Armbruster
Si
From: Victor Toso
As described in docs/devel/qapi-code-gen.rst line 998,
there should be no space between "Since" and ":".
Signed-off-by: Victor Toso
Message-ID: <20241217091504.16416-1-victort...@redhat.com>
Reviewed-by: Markus Armbruster
Signed-off-by: Markus Armbruster
---
qapi/cxl.json |
The following changes since commit 04d3d0e9f54d4c42759f3810aa135ce314d98dc4:
Merge tag 'hppa-system-for-v10-diva-artist-pull-request' of
https://github.com/hdeller/qemu-hppa into staging (2025-02-08 09:00:57 -0500)
are available in the Git repository at:
https://repo.or.cz/qemu/armbru.git t
Hi,
On 2/7/25 6:31 PM, Peter Xu wrote:
> On Fri, Feb 07, 2025 at 05:06:20PM +, Peter Maydell wrote:
>> On Fri, 7 Feb 2025 at 16:54, Peter Xu wrote:
>>> On Thu, Feb 06, 2025 at 03:21:51PM +0100, Eric Auger wrote:
This is a follow-up of Peter's attempt to fix the fact that
vIOMMUs a
This is a follow-up to [1], implementing it by avoiding the use of
address_space_write_rom() in cpu_memory_rw_debug() completely, and
teaching address_space_write() about debug access instead, the can also
write to ROM.
The goal is to let GDB via cpu_memory_rw_debug() to also properly write to
MMI
As documented in commit 4a2e242bbb306 ("memory: Don't use memcpy for
ram_device regions"), we disallow direct access to RAM DEVICE regions.
This change implies that address_space_write_rom() and
cpu_memory_rw_debug() won't be able to write to RAM DEVICE regions. It
will also affect cpu_flush_icach
As documented in commit 4a2e242bbb306 ("memory: Don't use memcpy for
ram_device regions"), we disallow direct access to RAM DEVICE regions.
Let's make this clearer to prepare for further changes. Note that romd
regions will never be RAM DEVICE at the same time.
Reviewed-by: Peter Xu
Signed-off-b
Let's factor the complete "directly accessible" check independent of
the "write" condition out so we can reuse it next.
We can now split up the checks RAM and ROMD check, so we really only check
for RAM DEVICE in case of RAM -- ROM DEVICE is neither RAM not RAM DEVICE.
Reviewed-by: Peter Xu
Sign
Right now, we only allow for writing to memory regions that allow direct
access using memcpy etc; all other writes are simply ignored. This
implies that debugging guests will not work as expected when writing
to MMIO device regions.
Let's extend cpu_memory_rw_debug() to write to more memory region
We want to pass another flag that will be stored in MemTxAttrs. So pass
MemTxAttrs directly.
Reviewed-by: Peter Xu
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Hildenbrand
---
hw/core/loader.c | 2 +-
hw/remote/vfio-user-obj.c | 2 +-
include/exec/memory.h | 5 +++--
Hi Peter,
On 2/7/25 7:18 PM, Peter Maydell wrote:
> On Fri, 7 Feb 2025 at 17:48, Peter Xu wrote:
>> On Fri, Feb 07, 2025 at 04:58:39PM +, Peter Maydell wrote:
>>> (I wonder if we ought to suggest quiescing outstanding
>>> DMA in the enter phase? But it's probably easier to fix
>>> the iommu
We don't need the MemTxAttrs, so let's simply use the simpler function
variant.
Reviewed-by: Peter Xu
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Hildenbrand
---
monitor/hmp-cmds-target.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/monitor/hmp-cmds-target
Let's factor more of the generic "is this directly accessible" check,
independent of the "write" condition out.
Note that the "!mr->rom_device" check in the write case essentially
disallows the memory_region_is_romd() condition again. Further note that
RAM DEVICE regions are also RAM regions, so w
Hi Cédric,
On 2/7/25 6:25 PM, Cédric Le Goater wrote:
> On 2/7/25 17:54, Peter Xu wrote:
>> On Thu, Feb 06, 2025 at 03:21:51PM +0100, Eric Auger wrote:
>>> This is a follow-up of Peter's attempt to fix the fact that
>>> vIOMMUs are likely to be reset before the device they protect:
>>>
>>> [PATCH
John Snow writes:
> On Fri, Feb 7, 2025, 6:57 AM Markus Armbruster wrote:
>
>> Daniel P. Berrangé writes:
>>
>> > This replaces use of the constants from the QapiSpecialFeatures
>> > enum, with constants from the auto-generate QapiFeatures enum
>> > in qapi-features.h
>> >
>> > The 'deprecated'
Daniel P. Berrangé writes:
> This series is a spin-off from
>
> https://lists.nongnu.org/archive/html/qemu-devel/2024-06/msg00807.html
>
> That series introduced a pragma allowing a schema to declare extra
> features that would be exposed to code.
>
> Following Markus' suggestion:
>
> https:/
Hi Peter,
On 2/7/25 6:47 PM, Peter Xu wrote:
> On Fri, Feb 07, 2025 at 04:58:39PM +, Peter Maydell wrote:
>> (I wonder if we ought to suggest quiescing outstanding
>> DMA in the enter phase? But it's probably easier to fix
>> the iommus like this series does than try to get every
>> dma-capab
On Fri, Feb 07, 2025 at 05:33:27PM -0600, Kim Phillips wrote:
> The Allowed SEV Features feature allows the host kernel to control
> which SEV features it does not want the guest to enable [1].
>
> This has to be explicitly opted-in by the user because it has the
> ability to break existing VMs if
On 2/10/2025 4:12 AM, dongli.zh...@oracle.com wrote:
> Hi Dapeng,
>
> On 2/7/25 1:52 AM, Mi, Dapeng wrote:
>> On 11/21/2024 6:06 PM, Mi, Dapeng wrote:
>>> On 11/8/2024 7:44 AM, dongli.zh...@oracle.com wrote:
Hi Zhao,
On 11/6/24 11:52 PM, Zhao Liu wrote:
> (+Dapang & Zide)
On Fri, Feb 07, 2025 at 04:53:55PM -0300, Fabiano Rosas wrote:
> We want to pass flags into qio_channel_tls_readv() but
> qio_channel_readv_full_all_eof() doesn't take a flags argument.
>
> No functional change.
>
> Signed-off-by: Fabiano Rosas
> ---
> hw/remote/mpqemu-link.c | 2 +-
> include/
On 4/2/25 15:37, Peter Maydell wrote:
On Thu, 30 Jan 2025 at 22:31, Edgar E. Iglesias
wrote:
On Mon, Jan 27, 2025 at 8:40 AM Peter Maydell wrote:
On Thu, 19 Dec 2024 at 06:17, Andrew.Yuan wrote:
-rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset];
-mask = FIELD_EX32
Cc'ing Igor for vCPU hotplugging expertise.
On 10/2/25 10:36, Bibo Mao wrote:
Interrupt controller ipi and extioi on LoongArch system can send
intterrupt to multiple CPUs, physical cpu id is used to route interrupt
for CPUs.
With cpu hotplug feature in future, notification with ipi and extioi
i
On 6/2/25 16:12, Peter Maydell wrote:
The function boston_fdt_filter() can return NULL on errors (in which
case it will print an error message). When we call this from the
non-FIT-image codepath, we aren't checking the return value, so we
will plough on with a NULL pointer, and segfault in fdt_t
On 2/10/25 10:59, Zhao Liu wrote:
On Thu, Feb 06, 2025 at 12:15:14PM +0100, Paolo Bonzini wrote:
Date: Thu, 6 Feb 2025 12:15:14 +0100
From: Paolo Bonzini
Subject: [PATCH] rust: pl011: convert pl011_create to safe Rust
X-Mailer: git-send-email 2.48.1
Not a major change but, as a small but sign
Hi Peter,
On 6/2/25 16:12, Peter Maydell wrote:
The boston machine doesn't set MachineState::fdt to the DTB blob that
it has loaded or created, which means that the QMP/HMP dumpdtb
monitor commands don't work.
Setting MachineState::fdt is easy in the non-FIT codepath: we can
simply do so immedi
On 6/2/25 16:12, Peter Maydell wrote:
In hmp_dumpdtb(), we print a message when the command succeeds. This
message is missing the trailing \n, so the HMP command prompt is
printed immediately after it. We also weren't capitalizing 'DTB', or
quoting the filename in the message. Fix these nits.
On 6/2/25 16:12, Peter Maydell wrote:
The openrisc machines don't set MachineState::fdt to point to their
DTB blob. This means that although the command line '-machine
dumpdtb=file.dtb' option works, the equivalent QMP and HMP monitor
commands do not, but instead produce the error "This machine
On Mon, Feb 10, 2025 at 2:26 AM Philippe Mathieu-Daudé
wrote:
>
> Only modify XtensaConfig within xtensa_register_core(),
> when the class is registered, not when it is initialized.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> Cc: Max Filippov
> ---
> target/xtensa/helper.c | 8 +---
>
On Sun, 9 Feb 2025 at 03:33, Joelle van Dyne wrote:
>
> When the VM exits with an data abort, we check the ISV field in the ESR and
> when
> ISV=1, that means the processor has filled the remaining fields with
> information
> needed to determine the access that caused the abort: address, access
Tell clippy the minimum supported Rust version for QEMU.
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/Cargo.toml | 1 +
rust/hw/char/pl011/src/device_class.rs | 1 -
rust/qemu-api-macros/Cargo.toml| 1 +
rust/qemu-api/Cargo.toml | 1 +
4 files changed, 3 ins
Generalize the existing optimization of "TSTNE x,sign" and "TSTNE x,-1".
This can be useful for example in the i386 frontend, which will generate
tests of zero-extended registers against 0x.
Ironically, on x86 hosts this is a very slight pessimization in the very
case it's meant to optimiz
missing_const_for_fn is not necessarily useful or good. For example in
a private API you can always add const later, and in a public API
it can be unnecessarily restrictive to annotate everything with const
(blocking further improvements to the API).
Nevertheless, QEMU turns it on because qemu_ap
Signed-off-by: Paolo Bonzini
---
docs/devel/index-process.rst | 1 +
docs/devel/rust.rst | 430 +++
2 files changed, 431 insertions(+)
create mode 100644 docs/devel/rust.rst
diff --git a/docs/devel/index-process.rst b/docs/devel/index-process.rst
index
Being the first crate added to QEMU, pl011 has a rather restrictive
Clippy setup. This can be sometimes a bit too heavy on its suggestions,
for example
error: this could be a `const fn`
--> hw/char/pl011/src/device.rs:382:5
|
382 | / fn set_read_trigger(&mut self) {
383 | | sel
From: Peter Maydell
Add a test case which tests some corner case behaviour of
fused-multiply-add on x86:
* 0 * Inf + SNaN should raise Invalid
* 0 * Inf + QNaN shouldh not raise Invalid
* tininess should be detected after rounding
There is also one currently-disabled test case:
* flush-to-ze
From: Peter Maydell
In commit 8adcff4ae7 ("fpu: handle raising Invalid for infzero in
pick_nan_muladd") we changed the handling of 0 * Inf + QNaN to always
raise the Invalid exception regardless of target architecture. (This
was a change affecting hppa, i386, sh4 and tricore.) However, this
was
Some items of Cargo.toml (readme, homepage, repository) are
only present because of clippy::cargo warnings being enabled in
rust/hw/char/pl011/src/lib.rs. But these items are not
particularly useful and would be all the same for all Cargo.toml
files in the QEMU workspace. Clean them up.
Signed-o
Configure the minimum supported Rust version (though strictly speaking
that's redundant with Cargo.toml), and the list of CamelCase identifiers
that are not Rust types.
Signed-off-by: Paolo Bonzini
---
rust/clippy.toml | 2 ++
1 file changed, 2 insertions(+)
create mode 100644 rust/clippy.toml
The following changes since commit 131c58469f6fb68c89b38fee6aba8bbb20c7f4bf:
rust: add --rust-target option for bindgen (2025-02-06 13:51:46 -0500)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
for you to fetch changes up to 476d6e4c9c4965734d
Signed-off-by: Philippe Mathieu-Daudé
---
Cc: qemu-ri...@nongnu.org
---
target/riscv/cpu.h | 2 +-
target/riscv/cpu.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 97713681cbe..fbe5548cf5a 100644
--- a/target/riscv/cpu.h
+++ b
Following Richard's suggestion [*], make QOM class data *const*.
Note, rust code not modified...
[*]
https://lore.kernel.org/qemu-devel/f4ec871d-e759-44bc-a10b-872322330...@linaro.org/
Philippe Mathieu-Daudé (10):
target/i386: Constify X86CPUModel uses
target/sparc: Constify SPARCCPUClass::
Only modify XtensaConfig within xtensa_register_core(),
when the class is registered, not when it is initialized.
Signed-off-by: Philippe Mathieu-Daudé
---
Cc: Max Filippov
---
target/xtensa/helper.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/xtensa/helpe
When the %data argument is not modified, we can declare it const.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sdhci-internal.h | 2 +-
hw/sd/sdhci.c| 2 +-
hw/sensor/emc141x.c | 2 +-
hw/sensor/isl_pmbus_vr.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff -
Signed-off-by: Philippe Mathieu-Daudé
---
target/sparc/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index dda811503b5..462bcb6c0e6 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -574,7 +574,7 @@ struct SPARCCPUClass
All callers now correctly expect a const class data.
Signed-off-by: Philippe Mathieu-Daudé
---
Cc: qemu-r...@nongnu.org
---
include/qom/object.h| 2 +-
hw/arm/armsse.c | 2 +-
hw/block/m25p80.c
Signed-off-by: Philippe Mathieu-Daudé
---
hw/isa/vt82c686.c | 2 +-
hw/rtc/m48t59-isa.c | 2 +-
hw/rtc/m48t59.c | 2 +-
hw/sensor/tmp421.c| 2 +-
hw/usb/hcd-ehci-pci.c | 2 +-
hw/usb/hcd-uhci.c | 2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/isa/vt82c
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/cpu.h | 2 +-
target/i386/cpu.c | 8
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index c67b42d34fc..f9ce6970ee1 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2288,7
Ping for review on patches 2, 3, 9, 10, 12, 14, please?
thanks
-- PMM
On Thu, 30 Jan 2025 at 18:23, Peter Maydell wrote:
>
> While reviewing Alex's recent secure timer patchset, I noticed a
> bug where it was using CP_ACCESS_TRAP when CP_ACCESS_TRAP_UNCATEGORIZED
> was wanted, and that we were m
Signed-off-by: Philippe Mathieu-Daudé
---
Cc: qemu-r...@nongnu.org
---
include/qom/object.h | 2 +-
hw/core/machine.c| 2 +-
hw/core/qdev.c | 2 +-
hw/pci/pci.c | 2 +-
qom/object.c | 2 +-
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/qom/object
On 10/2/25 11:22, Paolo Bonzini wrote:
Generalize the existing optimization of "TSTNE x,sign" and "TSTNE x,-1".
This can be useful for example in the i386 frontend, which will generate
tests of zero-extended registers against 0x.
Ironically, on x86 hosts this is a very slight pessimizati
Use GLib conversion macros to pass misa_mxl_max as
riscv_cpu_class_init() class data.
Signed-off-by: Philippe Mathieu-Daudé
---
Cc: qemu-ri...@nongnu.org
---
target/riscv/cpu.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.
On 10/2/25 11:22, Paolo Bonzini wrote:
Some items of Cargo.toml (readme, homepage, repository) are
only present because of clippy::cargo warnings being enabled in
rust/hw/char/pl011/src/lib.rs. But these items are not
particularly useful and would be all the same for all Cargo.toml
files in the
On Thu, Feb 06, 2025 at 12:15:14PM +0100, Paolo Bonzini wrote:
> Date: Thu, 6 Feb 2025 12:15:14 +0100
> From: Paolo Bonzini
> Subject: [PATCH] rust: pl011: convert pl011_create to safe Rust
> X-Mailer: git-send-email 2.48.1
>
> Not a major change but, as a small but significant step in creating
LoongArch extioi interrupt controller routes peripheral interrupt
to multiple CPUs, physical cpu id is used in interrupt routing table.
Here hotplug interface is added for extioi object, so that parent irq
line can be connected, and routing table can be added for new created
cpu.
Here only basic h
When cpu is added, it will connect gpio irq line to cpu irq.
And cpu hot-add is put in common code, move gpio irq initial
part into common code.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_extioi.c| 8 +---
hw/intc/loongarch_extioi_common.c | 6 +-
2 files changed, 6 insertions
LoongArch ipi can send interrupt to multiple CPUs, interrupt routing
to CPU comes from destination physical cpu id. Here hotplug interface
is added for IPI object, so that parent irq line can be connected, and
routing table can be added for new created cpu.
Here only basic hotplug framework is add
On Fri, 7 Feb 2025 at 18:29, Alex Bennée wrote:
>
> Richard Henderson writes:
>
> > On 2/7/25 07:45, Peter Maydell wrote:
> >> This is where things go wrong -- icount_start_warp_timer()
> >> notices that all CPU threads are currently idle, and
> >> decides it needs to warp the timer forwards to t
Use hotplug_handler_plug() to nofity extioi object when cold-plug
cpu is created, so that extioi can set and configure irq routing
to new cpu.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/hw/loongarch/virt.c b/h
Add logic cpu allocation and cpu mapping with cpu hotplug interface.
When cpu is added, connect ipi gpio irq to CPU IRQ_IPI irq pin.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_ipi.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/hw/intc/loongarch_
Use hotplug_handler_plug() to nofity ipi object when cold-plug
cpu is created, so that ipi can set and configure irq routing
to new cpu.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/vir
When cpu is added, connect extioi gpio irq to CPU irq pin.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_extioi_common.c | 45 +++
1 file changed, 45 insertions(+)
diff --git a/hw/intc/loongarch_extioi_common.c
b/hw/intc/loongarch_extioi_common.c
index 19e19a9f73..f
Interrupt controller ipi and extioi on LoongArch system can send
intterrupt to multiple CPUs, physical cpu id is used to route interrupt
for CPUs.
With cpu hotplug feature in future, notification with ipi and extioi
interrupt controller is required. Since there is common Notifier API for
CPU hotpl
> +/// A special `MemTxAttrs` constant, used to indicate that no memary
typo... s/memary/memory/
> +/// attributes are specified.
> +///
> +/// Bus masters which don't specify any attributes will get this,
> +/// which has all attribute bits clear except the topmost one
> +/// (so that we can dis
On 6/2/25 11:19, Paolo Bonzini wrote:
On 2/6/25 11:02, Philippe Mathieu-Daudé wrote:
Could we always make .valid_sizes() explicit?
Yes (for example build() could even fail to compile if you don't have
impl_sizes/valid_sizes set), but why do you want that? I'm not even
sure that all cases of .v
On Mon, 10 Feb 2025 at 10:56, Philippe Mathieu-Daudé wrote:
>
> Hi Peter,
>
> On 6/2/25 16:12, Peter Maydell wrote:
> > -int load_fit(const struct fit_loader *ldr, const char *filename, void
> > *opaque);
> > +/**
> > + * load_fit: load a FIT format image
> > + * @ldr: structure defining board sp
Hi,
On 2/6/25 8:47 PM, Sahil Siddiq wrote:
On 2/6/25 12:42 PM, Eugenio Perez Martin wrote:
On Thu, Feb 6, 2025 at 6:26 AM Sahil Siddiq wrote:
On 2/4/25 11:45 PM, Eugenio Perez Martin wrote:
PS: Please note that you can check packed_vq SVQ implementation
already without CVQ, as these features
Hi Markus,
These patches seem to have got lost/delayed along the way. Are
you able to send a pull for them soon ?
On Mon, Nov 18, 2024 at 04:12:33PM +0100, Markus Armbruster wrote:
> To repeat the 1st patch commit message...
>
> The general expectation is that header files should follow the same
SA_RESTORER and the associated sa_restorer field of struct sigaction are
an obsolete feature, not expected to be used by future architectures.
They are also absent on RISC-V, LoongArch, Hexagon and OpenRISC, but
defined due to their use of generic/signal.h. This leads to corrupted
data and out-of-
On 2/10/25 14:12, Niklas Schnelle wrote:
On Fri, 2025-02-07 at 15:56 -0500, Matthew Rosato wrote:
When receiving a guest mpcifc(4) or mpcifc(6) instruction without the T
bit set, treat this as a request to perform direct mapping instead of
address translation. In order to facilitate this, pin t
On 10/2/25 13:30, Paolo Bonzini wrote:
On 2/10/25 11:25, Philippe Mathieu-Daudé wrote:
Following Richard's suggestion [*], make QOM class data *const*.
Note, rust code not modified...
Untested but it should be something like
diff --git a/rust/qemu-api/src/qom.rs b/rust/qemu-api/src/qom.rs
in
On Fri, 2025-02-07 at 15:56 -0500, Matthew Rosato wrote:
> Specifying this bit in the guest CLP response indicates that the guest
> can optionally choose to skip translation and instead use
> identity-mapped operations.
>
> Signed-off-by: Matthew Rosato
> ---
> hw/s390x/s390-pci-vfio.c|
Since v1:
- Make XtensaConfigList::config not const (Max)
- Update / test rust (Paolo)
- Constify InterfaceInfo[]
Following Richard's suggestion [*], make QOM class data *const*.
[*]
https://lore.kernel.org/qemu-devel/f4ec871d-e759-44bc-a10b-872322330...@linaro.org/
Philippe Mathieu-Daudé (11):
Use GLib conversion macros to pass misa_mxl_max as
riscv_cpu_class_init() class data.
Signed-off-by: Philippe Mathieu-Daudé
---
Cc: qemu-ri...@nongnu.org
---
target/riscv/cpu.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/isa/vt82c686.c | 2 +-
hw/rtc/m48t59-isa.c | 2 +-
hw/rtc/m48t59.c | 2 +-
hw/sensor/tmp421.c| 2 +-
hw/usb/hcd-ehci-pci.c | 2 +-
hw/usb/hcd-uhci.c | 2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/isa/vt82c
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/cpu.h | 2 +-
target/i386/cpu.c | 8
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index c67b42d34fc..f9ce6970ee1 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2288,7
Signed-off-by: Philippe Mathieu-Daudé
---
target/sparc/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index dda811503b5..462bcb6c0e6 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -574,7 +574,7 @@ struct SPARCCPUClass
Mechanical change using gsed.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/virtio/virtio-pci.h | 2 +-
include/qom/object.h| 4 ++--
authz/list.c| 2 +-
authz/listfile.c
Make XtensaConfigList::config not const. Only modify
XtensaConfig within xtensa_register_core(), when the
class is registered, not when it is initialized.
Signed-off-by: Philippe Mathieu-Daudé
---
Cc: Max Filippov
---
target/xtensa/cpu.h| 2 +-
target/xtensa/helper.c | 5 +++--
2 files chan
Signed-off-by: Philippe Mathieu-Daudé
---
Cc: qemu-ri...@nongnu.org
---
target/riscv/cpu.h | 2 +-
target/riscv/cpu.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 97713681cbe..fbe5548cf5a 100644
--- a/target/riscv/cpu.h
+++ b
All callers now correctly expect a const class data.
Signed-off-by: Philippe Mathieu-Daudé
---
include/qom/object.h| 2 +-
hw/arm/armsse.c | 2 +-
hw/block/m25p80.c | 2 +-
hw/isa/vt82c686.c
Signed-off-by: Philippe Mathieu-Daudé
---
include/qom/object.h | 2 +-
hw/core/machine.c| 2 +-
hw/core/qdev.c | 2 +-
hw/pci/pci.c | 2 +-
qom/object.c | 2 +-
rust/qemu-api/src/qom.rs | 2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
diff --
On Fri, Feb 07, 2025 at 11:16:15AM +0100, Paolo Bonzini wrote:
> Date: Fri, 7 Feb 2025 11:16:15 +0100
> From: Paolo Bonzini
> Subject: [PATCH 04/12] rust: qdev: add clock creation
> X-Mailer: git-send-email 2.48.1
>
> Add a Rust version of qdev_init_clock_in, which can be used in
> instance_init
On Fri, Feb 07, 2025 at 03:15:48PM -0300, Fabiano Rosas wrote:
> >> +for (i = 0; i < migrate_multifd_channels(); i++) {
> >> +MultiFDSendParams *p = &multifd_send_state->params[i];
> >> +
> >> +/* thread_created implies the TLS handshake has succeeded */
> >> +if (p->tls
On Mon, 10 Feb 2025 at 14:14, Peter Xu wrote:
>
> On Fri, Feb 07, 2025 at 06:18:50PM +, Peter Maydell wrote:
> > On Fri, 7 Feb 2025 at 17:48, Peter Xu wrote:
> > >
> > > On Fri, Feb 07, 2025 at 04:58:39PM +, Peter Maydell wrote:
> > > > (I wonder if we ought to suggest quiescing outstandi
On Mon, Feb 10, 2025 at 11:58 AM Sahil Siddiq wrote:
>
> Hi,
>
> On 2/6/25 8:47 PM, Sahil Siddiq wrote:
> > On 2/6/25 12:42 PM, Eugenio Perez Martin wrote:
> >> On Thu, Feb 6, 2025 at 6:26 AM Sahil Siddiq wrote:
> >>> On 2/4/25 11:45 PM, Eugenio Perez Martin wrote:
> PS: Please note that you
On 6/2/25 22:58, Bernhard Beschow wrote:
Am 6. Februar 2025 17:32:31 UTC schrieb Peter Maydell
:
On Tue, 4 Feb 2025 at 09:21, Bernhard Beschow wrote:
The implementation just allows Linux to determine date and time.
Signed-off-by: Bernhard Beschow
---
MAINTAINERS | 1 +
hw/rt
On 30/1/25 14:43, Cédric Le Goater wrote:
This is to be consistent with other reported errors related to vIOMMU
devices.
Signed-off-by: Cédric Le Goater
---
hw/vfio/pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
On Thu, 6 Feb 2025 at 22:12, Hao Wu wrote:
>
> NPCM8XX SoC is the successor of the NPCM7XX. It features quad-core
> Cortex-A35 (Armv8, 64-bit) CPUs and some additional peripherals.
>
> This document describes the NPCM8XX SoC and an evaluation board
> (NPCM 845 EVB).
>
> Signed-off-by: Hao Wu
> --
On 30/1/25 14:43, Cédric Le Goater wrote:
This helper will be useful in the listener handlers to extract the
VFIO device from a memory region using memory_region_owner(). At the
moment, we only care for PCI passthrough devices. If the need arises,
we will add more.
Signed-off-by: Cédric Le Goate
On 30/1/25 14:43, Cédric Le Goater wrote:
When the IOMMU address space width is smaller than the physical
address width, a MMIO region of a device can fail to map because the
region is outside the supported IOVA ranges of the VM. In this case,
PCI peer-to-peer transactions on BARs are not support
Hi Cédric,
On 30/1/25 14:43, Cédric Le Goater wrote:
The Intel CPU has a complex history regarding setting of the physical
address space width on KVM. A 'phys_bits' field and a "phys-bits"
property were added by commit af45907a1328 ("target-i386: Allow
physical address bits to be set") to tune t
Coverity scan complained about expression "|LARGEFILE" to be non reachable
and the detailed Coverity report claims O_LARGEFILE was zero. I can't
reproduce this here, but I assume that means there are at least some
system(s) which define O_LARGEFILE as zero.
This is not really an issue, but to sile
When running in TOR mode (Top of Range) the next PMP entry controls
whether the entry is locked. However simply checking if the PMP_LOCK bit
is set is not sufficient with the Smepmp extension which now provides a
bit (mseccfg.RLB (Rule Lock Bypass)) to disregard the lock bits. In
order to respect t
On Fri, Feb 07 2025, Richard Henderson wrote:
> On 2/7/25 03:02, Cornelia Huck wrote:
>> And switch to using the generated definitions.
>>
>> Generated against Linux 6.14-rc1.
>>
>> Signed-off-by: Cornelia Huck
>> ---
>> target/arm/cpu-sysreg-properties.c | 716 -
>
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