Hi Peter,
On 2/7/25 6:47 PM, Peter Xu wrote: > On Fri, Feb 07, 2025 at 04:58:39PM +0000, Peter Maydell wrote: >> (I wonder if we ought to suggest quiescing outstanding >> DMA in the enter phase? But it's probably easier to fix >> the iommus like this series does than try to get every >> dma-capable pci device to do something different.) > I wonder if we should provide some generic helper to register vIOMMU reset > callbacks, so that we'll be sure any vIOMMU model impl that will register > at exit() phase only, and do nothing during the initial two phases. Then > we can put some rich comment on that helper on why. As discussed with Cédric, I think it shall think about having eventually a base class for vIOMMU. Maybe this is something we can handle afterwards though. > > Looks like it means the qemu reset model in the future can be a combination > of device tree (which resets depth-first) and the three phases model. We > will start to use different approach to solve different problems. > > Maybe after we settle our mind, we should update the reset document, > e.g. for device emulation developers, we need to be clear on where to > quiesce the DMAs, and it must not happen at exit(). Both all devices and > all iommu impls need to follow the rules to make it work like the plan. The 3 phase documentation already states that you shouldn't do anything in enter phase that can have side-effect on other devices. However I agree we can add another example besides the qemu_irq line one. Eric > > Thanks, >
