Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
---
Cc: qemu-ri...@nongnu.org
---
target/riscv/cpu.h | 2 +-
target/riscv/cpu.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 97713681cbe..fbe5548cf5a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -529,7 +529,7 @@ struct RISCVCPUClass {
DeviceRealize parent_realize;
ResettablePhases parent_phases;
- uint32_t misa_mxl_max; /* max mxl for this cpu */
+ RISCVMXL misa_mxl_max; /* max mxl for this cpu */
};
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3d4bd157d2c..f3ad7f88f0e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2955,7 +2955,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void
*data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
- mcc->misa_mxl_max = (uint32_t)(uintptr_t)data;
+ mcc->misa_mxl_max = (RISCVMXL)(uintptr_t)data;
riscv_cpu_validate_misa_mxl(mcc);
}
--
2.47.1
