Hi Peter,
On 2/7/25 7:18 PM, Peter Maydell wrote: > On Fri, 7 Feb 2025 at 17:48, Peter Xu <pet...@redhat.com> wrote: >> On Fri, Feb 07, 2025 at 04:58:39PM +0000, Peter Maydell wrote: >>> (I wonder if we ought to suggest quiescing outstanding >>> DMA in the enter phase? But it's probably easier to fix >>> the iommus like this series does than try to get every >>> dma-capable pci device to do something different.) >> I wonder if we should provide some generic helper to register vIOMMU reset >> callbacks, so that we'll be sure any vIOMMU model impl that will register >> at exit() phase only, and do nothing during the initial two phases. Then >> we can put some rich comment on that helper on why. >> >> Looks like it means the qemu reset model in the future can be a combination >> of device tree (which resets depth-first) and the three phases model. We >> will start to use different approach to solve different problems. > The tree of QOM devices (i.e. the one based on the qbus buses > and rooted at the sysbus) resets depth-first, but it does so in > three phases: first we traverse everything doing 'enter'; then > we traverse everything doing 'hold'; then we traverse everything > doing 'exit'. There *used* to be an awkward mix of some things > being three-phase and some not, but we have now got rid of all > of those so a system reset does a single three-phase reset run > which resets everything. Thank you Peter. This is reassuring. I will add such kind of description in the commit msg/cover letter. Eric > > -- PMM >
