Re: Rust in QEMU roadmap

On Tue, Nov 26, 2024 at 6:48 PM Paolo Bonzini wrote: > Callbacks > ' > > This is the least mature of the "urgent" changes, and perhaps the more > important to have a good design for. PL011 has callbacks for character > devices and memory regions, but other usecases include timers, bottom

Re: [PATCH v2] tests/functional/aarch64: add tests for FEAT_RME

W dniu 28.11.2024 o 22:37, Pierrick Bouvier pisze: This boot an OP-TEE environment, and launch a nested guest VM inside it using the Realms feature. We do it for virt and sbsa-ref platforms. Signed-off-by: Pierrick Bouvier diff --git a/tests/functional/meson.build b/tests/functional/meson.bu

Re: [PATCH v2] tests/functional/aarch64: add tests for FEAT_RME

Hi Marcin, On 12/1/24 05:34, Marcin Juszkiewicz wrote: W dniu 28.11.2024 o 22:37, Pierrick Bouvier pisze: This boot an OP-TEE environment, and launch a nested guest VM inside it using the Realms feature. We do it for virt and sbsa-ref platforms. Signed-off-by: Pierrick Bouvier diff --git a

[PATCH 64/67] target/arm: Convert FRECPE, FRECPX, FRSQRTE to decodetree

Remove disas_simd_scalar_two_reg_misc and disas_simd_two_reg_misc_fp16 as these were the last insns decoded by those functions. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 330 - target/arm/tcg/a64.decode | 15 ++ 2 files changed, 5

[PATCH 55/67] target/arm: Convert FCVT* (vector, integer) scalar to decodetree

Arm silliness with naming, the scalar insns described as part of the vector instructions, as separate from the "regular" scalar insns which output to general registers. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 135 ++--- target/arm/tcg/a64

[PATCH 09/67] target/arm: Convert PAC[ID]*, AUT[ID]* to decodetree

This includes PACIA, PACIZA, PACIB, PACIZB, PACDA, PACDZA, PACDB, PACDZB, AUTIA, AUTIZA, AUTIB, AUTIZB, AUTDA, AUTDZA, AUTDB, AUTDZB. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 173 + target/arm/tcg/a64.decode | 13 +++ 2 files cha

[PATCH 27/67] target/arm: Convert FRINT[NPMSAXI] (scalar) to decodetree

Remove handle_fp_1src_half as these were the last insns decoded by that function. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 107 ++--- target/arm/tcg/a64.decode | 8 +++ 2 files changed, 39 insertions(+), 76 deletions(-) diff --git

[PATCH 47/67] target/arm: Introduce clear_vec

In a couple of places, clearing the entire vector before storing one element is the easiest solution. Wrap that into a helper function. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 21 - 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/

[PATCH 67/67] target/arm: Convert FCVTL to decodetree

Remove lookup_disas_fn, handle_2misc_widening, disas_simd_two_reg_misc, disas_data_proc_simd, disas_data_proc_simd_fp, disas_a64_legacy, as this is the final insn to be converted. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 202 +++-- target/

[PATCH 65/67] target/arm: Introduce gen_gvec_urecpe, gen_gvec_ursqrte

Signed-off-by: Richard Henderson --- target/arm/helper.h | 3 +++ target/arm/tcg/translate.h | 5 + target/arm/tcg/gengvec.c| 16 target/arm/tcg/translate-neon.c | 4 ++-- target/arm/tcg/vec_helper.c | 22 ++ 5 files changed

[PATCH 4/8] vfio/igd: align generation with i915 kernel driver

Define the igd device generations according to i915 kernel driver to avoid confusion, and adjust comment placement to clearly reflect the relationship between ids and devices. Signed-off-by: Tomita Moeko --- hw/vfio/igd.c | 36 1 file changed, 16 insertions(+

[PATCH 2/8] vfio/igd: canonicalize memory size calculations

Add helper functions igd_gtt_memory_size() and igd_stolen_size() for calculating GTT stolen memory and Data stolen memory size in bytes, and use macros to replace the hardware-related magic numbers for better readability. Signed-off-by: Tomita Moeko --- hw/vfio/igd.c | 101 ++

[PATCH 5/8] vfio/igd: add Alder/Raptor/Rocket/Ice/Jasper Lake device ids

All gen 11 and 12 igd devices have 64 bit BDSM register at 0xC0 in its config space, add them to the list to support igd passthrough on Alder/ Raptor/Rocket/Ice/Jasper Lake platforms. Tested legacy mode of igd passthrough works properly on both linux and windows guests with AlderLake-S GT1 (8086:4

[PATCH 6/8] vfio/igd: emulate GGC register in mmio bar0

The GGC register at 0x50 of pci config space is a mirror of the same register at 0x108040 of mmio bar0 [1]. i915 driver also reads that register from mmio bar0 instead of config space. As GGC is programmed and emulated by qemu, the mmio address should also be emulated, in the same way of BDSM regis

[PATCH 3/8] vfio/igd: remove unsupported device ids

Since e433f208973f ("vfio/igd: return an invalid generation for unknown devices"), the default return of igd_gen() was changed to unsupported. There is no need to filter out those unsupported devices. Signed-off-by: Tomita Moeko --- hw/vfio/igd.c | 10 -- 1 file changed, 10 deletions(-)

[PATCH 0/8] vfio/igd: Enable legacy mode on more devices

This patchset extends the support of legacy mode igd passthrough to all Intel Gen 11 and 12 devices (including Ice Lake, Jasper Lake, Rocket Lake, Alder Lake and Raptor Lake), and emulates GGC register in MMIO BAR0 for better compatibiltiy (It is tested Windows and GOP driver will read this MMIO re

[PATCH 1/8] vfio/igd: fix GTT stolen memory size calculation for gen 7

Both intel documentation [1][2] and i915 driver shows GGMS represents GTT stolen memory size in multiple of 1MB, not 2MB starting from gen 8. [1] https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/3rd-gen-core-desktop-vol-2-datasheet.pdf [2] https://www.intel.com/content/dam

[PATCH 7/8] vfio/igd: emulate BDSM in mmio bar0 for gen 6-10 devices

A recent commit in i915 driver [1] claims the BDSM register at 0x1080c0 of mmio bar0 has been there since gen 6. Mirror this register to the 32 bit BDSM register at 0x5c in pci config space for gen6-10 devices. [1] https://patchwork.freedesktop.org/patch/msgid/20240202224340.30647-7-ville.syrj...

[PATCH 8/8] vfio/igd: add x-igd-gms option back to set DSM region size for guest

DSM region is likely to store framebuffer in Windows, a small DSM region may cause display issues (e.g. half of the screen is black). By default, QEMU uses host's original value, which is determined by DVMT Pre-Allocated option in Intel FSP of host bios. Some vendors do not expose this config item

RE: [PATCH v6 0/3] Upgrade ACPI SPCR table to support SPCR table revision 4 format

> -Original Message- > From: JeeHeng Sia > Sent: Monday, 28 October, 2024 9:58 AM > To: qemu-...@nongnu.org; qemu-devel@nongnu.org; qemu-ri...@nongnu.org > Cc: m...@redhat.com; imamm...@redhat.com; anisi...@redhat.com; > peter.mayd...@linaro.org; JeeHeng Sia > ; shannon.zha...@gmail.co

Re: [PATCH 2/8] vfio/igd: canonicalize memory size calculations

On Mon, 2 Dec 2024 00:09:32 +0800 Tomita Moeko wrote: > Add helper functions igd_gtt_memory_size() and igd_stolen_size() for > calculating GTT stolen memory and Data stolen memory size in bytes, > and use macros to replace the hardware-related magic numbers for > better readability. > > Signed-

Re: [PATCH 1/8] vfio/igd: fix GTT stolen memory size calculation for gen 7

On Mon, 2 Dec 2024 00:09:31 +0800 Tomita Moeko wrote: > Both intel documentation [1][2] and i915 driver shows GGMS represents > GTT stolen memory size in multiple of 1MB, not 2MB starting from gen 8. > > [1] > https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/3rd-gen-core

Re: [PATCH 3/8] vfio/igd: remove unsupported device ids

On Mon, 2 Dec 2024 00:09:33 +0800 Tomita Moeko wrote: > Since e433f208973f ("vfio/igd: return an invalid generation for unknown > devices"), the default return of igd_gen() was changed to unsupported. > There is no need to filter out those unsupported devices. > > Signed-off-by: Tomita Moeko >

Re: [PATCH 1/8] vfio/igd: fix GTT stolen memory size calculation for gen 7

On Sun, 1 Dec 2024 22:11:29 -0700 Alex Williamson wrote: > On Mon, 2 Dec 2024 00:09:31 +0800 > Tomita Moeko wrote: > > > Both intel documentation [1][2] and i915 driver shows GGMS represents > > GTT stolen memory size in multiple of 1MB, not 2MB starting from gen 8. > > > > [1] > > https://w

Re: [PULL 0/6] ppc-for-9.2-2 queue

02.12.2024 08:44, Nicholas Piggin wrote: On Wed Nov 27, 2024 at 11:22 PM AEST, Harsh Prateek Bora wrote: Hi Michael, On Wed, 27 Nov, 2024, 3:14 pm Michael Tokarev, wrote: 26.11.2024 20:12, Nicholas Piggin: * Assorted small ppc fixes

Re: [PATCH RFC-for-10.0] hw/usb/hcd-xhci-pci: Use event ring 0 if interrupter mapping unsupported

On 2024/12/02 1:03, Phil Dennis-Jordan wrote: This change addresses an edge case that trips up macOS guest drivers for PCI based XHCI controllers. The XHCI specification, section 4.17.1 specifies that "If Interrupter Mapping is not supported, the Interrupter Target field shall be ignored by the

Re: [PULL 0/6] ppc-for-9.2-2 queue

On Wed Nov 27, 2024 at 11:22 PM AEST, Harsh Prateek Bora wrote: > Hi Michael, > > On Wed, 27 Nov, 2024, 3:14 pm Michael Tokarev, wrote: > > > 26.11.2024 20:12, Nicholas Piggin: > > > > > * Assorted small ppc fixes > > > > > > > > > B

Re: [PATCH 4/8] vfio/igd: align generation with i915 kernel driver

On Mon, 2 Dec 2024 00:09:34 +0800 Tomita Moeko wrote: > Define the igd device generations according to i915 kernel driver to > avoid confusion, and adjust comment placement to clearly reflect the > relationship between ids and devices. > > Signed-off-by: Tomita Moeko > --- > hw/vfio/igd.c | 3

Re: nested-smmuv3 topic for QEMU/libvirt, Nov 2024

Hi, Nico On Fri, 1 Nov 2024 at 19:55, Jason Gunthorpe wrote: > > On Thu, Oct 31, 2024 at 09:09:20PM -0700, Nicolin Chen wrote: > > > FWIW, Robin requested a different solution for MSI mapping [1], v.s. > > the RMR one that we have been using since Eric's work. I drafted a > > few VFIO/IOMMUFD pat

[PATCH 08/67] target/arm: Convert CLZ, CLS to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 72 ++ target/arm/tcg/a64.decode | 3 ++ 2 files changed, 33 insertions(+), 42 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1805d77f43..5

[PATCH 62/67] target/arm: Convert FCVT* (vector, integer) to decodetree

Remove handle_2misc_64 as these were the last insns decoded by that function. Remove helper_advsimd_f16to[su]inth as unused; we now always go through helper_vfp_to[su]hh or a specialized vector function instead. Signed-off-by: Richard Henderson --- target/arm/helper.h| 2 + target

[PATCH 40/67] target/arm: Convert CMGT, CMGE, GMLT, GMLE, CMEQ (zero) to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 94 +++--- target/arm/tcg/a64.decode | 10 2 files changed, 40 insertions(+), 64 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 3d08c6e09b.

[PATCH 50/67] target/arm: Convert FCVTXN to decodetree

Remove handle_2misc_narrow as this was the last insn decoded by that function. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 101 +++-- target/arm/tcg/a64.decode | 4 ++ 2 files changed, 24 insertions(+), 81 deletions(-) diff --git a/ta

[PATCH 42/67] target/arm: Convert handle_rev to decodetree

This includes REV16, REV32, REV64. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 79 +++--- target/arm/tcg/a64.decode | 5 +++ 2 files changed, 10 insertions(+), 74 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tc

[PATCH 12/67] target/arm: Convert disas_add_sub_ext_reg to decodetree

This includes ADD, SUB, ADDS, SUBS (extended register). Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 65 +++--- target/arm/tcg/a64.decode | 9 + 2 files changed, 29 insertions(+), 45 deletions(-) diff --git a/target/arm/tcg/translat

[PATCH 41/67] target/arm: Introduce gen_gvec_rev{16,32,64}

Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 6 +++ target/arm/tcg/gengvec.c| 58 ++ target/arm/tcg/translate-neon.c | 88 +++-- 3 files changed, 81 insertions(+), 71 deletions(-) diff --git a/target/arm/tcg/trans

[PATCH 56/67] target/arm: Convert FCVT* (vector, fixed-point) scalar to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 4 +--- target/arm/tcg/a64.decode | 19 +++ 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index ad245f2c26..bdeb0288fd 1006

[PATCH 22/67] target/arm: Convert FCMP, FCMPE, FCCMP, FCCMPE to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 287 + target/arm/tcg/a64.decode | 8 + 2 files changed, 116 insertions(+), 179 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 4611ae4ade.

[PATCH 63/67] target/arm: Convert handle_2misc_fcmp_zero to decodetree

This includes FCMEQ, FCMGT, FCMGE, FCMLT, FCMLE. Signed-off-by: Richard Henderson --- target/arm/helper.h| 5 + target/arm/tcg/translate-a64.c | 249 + target/arm/tcg/vec_helper.c| 4 +- target/arm/tcg/a64.decode | 30 4 files change

[PATCH 07/67] target/arm: Convert RBIT, REV16, REV32, REV64 to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 137 +++-- target/arm/tcg/a64.decode | 11 +++ 2 files changed, 72 insertions(+), 76 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index ca8b644dc7.

[PATCH 39/67] target/arm: Convert CNT, NOT, RBIT (vector) to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 34 ++ target/arm/tcg/a64.decode | 4 2 files changed, 10 insertions(+), 28 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index f96b29e5a9.

[PATCH 60/67] target/arm: Convert [US]CVTF (vector) to decodetree

Remove handle_simd_intfp_conv and handle_simd_shift_intfp_conv as these were the last insns decoded by those functions. Signed-off-by: Richard Henderson --- target/arm/helper.h| 3 + target/arm/tcg/translate-a64.c | 201 ++--- target/arm/tcg/vec_helper.c

[PATCH 20/67] target/arm: Introduce fp_access_check_scalar_hsd

Provide a simple way to check for float64, float32, and float16 support, as well as the fpu enabled. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 62 ++ 1 file changed, 32 insertions(+), 30 deletions(-) diff --git a/target/arm/tcg/transla

[PATCH 58/67] target/arm: Convert [US]CVTF (vector, fixed-point) scalar to decodetree

Remove disas_simd_scalar_shift_imm as these were the last insns decoded by that function. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 47 -- target/arm/tcg/a64.decode | 8 ++ 2 files changed, 8 insertions(+), 47 deletions(-) di

[PATCH 30/67] target/arm: Convert FCVT (scalar) to decodetree

Remove handle_fp_fcvt and disas_fp_1src as these were the last insns decoded by those functions. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 159 ++--- target/arm/tcg/a64.decode | 7 ++ 2 files changed, 74 insertions(+), 92 deletions(-

[PATCH 44/67] target/arm: Introduce gen_gvec_{s,u}{add,ada}lp

Pairwise addition with and without accumulation. Signed-off-by: Richard Henderson --- target/arm/helper.h | 2 - target/arm/tcg/translate.h | 9 ++ target/arm/tcg/gengvec.c| 230 target/arm/tcg/neon_helper.c| 22 --- target/arm/t

[PATCH 59/67] target/arm: Rename helper_gvec_vcvt_[hf][su] with _rz

Emphasize that these functions use round-to-zero mode. Signed-off-by: Richard Henderson --- target/arm/helper.h | 8 target/arm/tcg/translate-neon.c | 8 target/arm/tcg/vec_helper.c | 8 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/t

[PATCH 16/67] target/arm: Convert RMIF to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 32 +--- target/arm/tcg/a64.decode | 3 +++ 2 files changed, 12 insertions(+), 23 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index d7747fcf57..1a

[PATCH 61/67] target/arm: Convert FCVTZ[SU] (vector, fixed-point) to decodetree

Remove handle_simd_shift_fpint_conv and disas_simd_shift_imm as these were the last insns decoded by those functions. Signed-off-by: Richard Henderson --- target/arm/helper.h| 4 + target/arm/tcg/translate-a64.c | 160 +++-- target/arm/tcg/vec_helper.c

[PATCH 54/67] target/arm: Convert FRINT* (vector) to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 176 - target/arm/tcg/a64.decode | 26 + 2 files changed, 88 insertions(+), 114 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1e8cb079

[PATCH 66/67] target/arm: Convert URECPE and URSQRTE to decodetree

Remove handle_2misc_reciprocal as these were the last insns decoded by that function. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 139 ++--- target/arm/tcg/a64.decode | 3 + 2 files changed, 8 insertions(+), 134 deletions(-) diff --gi

[PATCH 49/67] target/arm: Convert FCVTN, BFCVTN to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 89 ++ target/arm/tcg/a64.decode | 5 ++ 2 files changed, 52 insertions(+), 42 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 6c44e9d8a1..8

[PATCH 02/67] target/arm: Convert UDIV, SDIV to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 64 +- target/arm/tcg/a64.decode | 22 2 files changed, 54 insertions(+), 32 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index b28

[PATCH 51/67] target/arm: Convert SHLL to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 75 +- target/arm/tcg/a64.decode | 2 + 2 files changed, 40 insertions(+), 37 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index dd46749ac6..61

[PATCH RFC-for-10.0] hw/usb/hcd-xhci-pci: Use event ring 0 if interrupter mapping unsupported

This change addresses an edge case that trips up macOS guest drivers for PCI based XHCI controllers. The XHCI specification, section 4.17.1 specifies that "If Interrupter Mapping is not supported, the Interrupter Target field shall be ignored by the xHC and all Events targeted at Interrupter 0."

[PATCH 36/67] target/arm: Introduce gen_gvec_cls, gen_gvec_clz

Add gvec interfaces for CLS and CLZ operations. Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 5 + target/arm/tcg/gengvec.c| 35 + target/arm/tcg/translate-a64.c | 29 +++ target/arm/tcg/translate-neon

[PATCH 01/67] target/arm: Use ### to separate 3rd-level sections in a64.decode

We already use ### for 4.1.92 Data Processing (immediate), but not the two following two third-level sections: 4.1.93 Branches, and 4.1.94 Loads and stores. Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targ

[PATCH 17/67] target/arm: Convert SETF8, SETF16 to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 48 +- target/arm/tcg/a64.decode | 4 +++ 2 files changed, 11 insertions(+), 41 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1af41e22eb..

[PATCH 10/67] target/arm: Convert XPAC[ID] to decodetree

Remove disas_data_proc_1src, as these were the last insns decoded by that function. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 99 +- target/arm/tcg/a64.decode | 3 ++ 2 files changed, 16 insertions(+), 86 deletions(-) diff --git

[PATCH 37/67] target/arm: Convert CLS, CLZ (vector) to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 37 -- target/arm/tcg/a64.decode | 2 ++ 2 files changed, 19 insertions(+), 20 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 4abc786cf6..3

[PATCH 34/67] target/arm: Convert SQABS, SQNEG to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 123 + target/arm/tcg/a64.decode | 11 +++ 2 files changed, 89 insertions(+), 45 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index e0b5dd76b0.

[PATCH 43/67] target/arm: Move helper_neon_addlp_{s8, s16} to neon_helper.c

Move from helper-a64.c to neon_helper.c so that these functions are available for arm32 code as well. Signed-off-by: Richard Henderson --- target/arm/helper.h | 2 ++ target/arm/tcg/helper-a64.h | 2 -- target/arm/tcg/helper-a64.c | 43 target/ar

[PATCH 33/67] target/arm: Convert handle_fmov to decodetree

Remove disas_fp_int_conv and disas_data_proc_fp as these were the last insns decoded by those functions. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 232 ++--- target/arm/tcg/a64.decode | 14 ++ 2 files changed, 86 insertions(+), 160 de

[PATCH 05/67] target/arm: Convert SUBP, IRG, GMI to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 94 +++--- target/arm/tcg/a64.decode | 7 +++ 2 files changed, 59 insertions(+), 42 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 22594a1149..

[PATCH 24/67] target/arm: Pass fpstatus to vfp_sqrt*

Pass fpstatus not env, like most other fp helpers. Signed-off-by: Richard Henderson --- target/arm/helper.h| 6 +++--- target/arm/tcg/translate-a64.c | 15 +++ target/arm/tcg/translate-vfp.c | 6 +++--- target/arm/vfp_helper.c| 12 ++-- 4 files changed,

[PATCH 46/67] target/arm: Remove helper_neon_{add,sub}l_u{16,32}

These have generic equivalents: tcg_gen_vec_{add,sub}{16,32}_i64. Signed-off-by: Richard Henderson --- target/arm/helper.h | 4 target/arm/tcg/neon_helper.c| 36 - target/arm/tcg/translate-neon.c | 22 ++-- 3 files changed, 11

[PATCH 31/67] target/arm: Convert handle_fpfpcvt to decodetree

This includes SCVTF, UCVTF, FCVT{N,P,M,Z,A}{S,U}. Remove disas_fp_fixed_conv as those were the last insns decoded by that function. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 391 ++--- target/arm/tcg/a64.decode | 40 2 files chan

[PATCH 21/67] target/arm: Introduce fp_access_check_vector_hsd

Provide a simple way to check for float64, float32, and float16 support vs vector width, as well as the fpu enabled. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 135 + 1 file changed, 54 insertions(+), 81 deletions(-) diff --git a/target

[PATCH 13/67] target/arm: Convert disas_add_sub_reg to decodetree

This includes ADD, SUB, ADDS, SUBS (shifted register). Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 64 ++ target/arm/tcg/a64.decode | 11 +- 2 files changed, 28 insertions(+), 47 deletions(-) diff --git a/target/arm/tcg/translat

[PATCH 15/67] target/arm: Convert disas_adc_sbc to decodetree

This includes ADC, SBC, ADCS, SBCS. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 43 +- target/arm/tcg/a64.decode | 6 + 2 files changed, 22 insertions(+), 27 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm

[PATCH 53/67] target/arm: Convert FSQRT (vector) to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 67 +- target/arm/tcg/a64.decode | 3 ++ 2 files changed, 53 insertions(+), 17 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 31272c1878..1

[PATCH 35/67] target/arm: Convert ABS, NEG to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 46 +++--- target/arm/tcg/a64.decode | 4 +++ 2 files changed, 35 insertions(+), 15 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 6564fff6b9..

[PATCH 48/67] target/arm: Convert XTN, SQXTUN, SQXTN, UQXTN to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 153 - target/arm/tcg/a64.decode | 9 ++ 2 files changed, 102 insertions(+), 60 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 9b2ff20413.

[PATCH 11/67] target/arm: Convert disas_logic_reg to decodetree

This includes AND, BIC, ORR, ORN, EOR, EON, ANDS, BICS (shifted reg). Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 117 - target/arm/tcg/a64.decode | 9 +++ 2 files changed, 51 insertions(+), 75 deletions(-) diff --git a/target/arm

[PATCH 45/67] target/arm: Convert handle_2misc_pairwise to decodetree

This includes SADDLP, UADDLP, SADALP, UADALP. Signed-off-by: Richard Henderson --- target/arm/tcg/helper-a64.h| 2 - target/arm/tcg/helper-a64.c| 18 target/arm/tcg/translate-a64.c | 84 +++--- target/arm/tcg/a64.decode | 5 ++ 4 files changed,

[PATCH 28/67] target/arm: Convert BFCVT to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 24 ++-- target/arm/tcg/a64.decode | 3 +++ 2 files changed, 9 insertions(+), 18 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index e8842012ea..b713c7d184

[PATCH 06/67] target/arm: Convert PACGA to decodetree

Remove disas_data_proc_2src, as this was the last insn decoded by that function. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 65 ++ target/arm/tcg/a64.decode | 2 ++ 2 files changed, 13 insertions(+), 54 deletions(-) diff --git a/t

[PATCH 18/67] target/arm: Convert CCMP, CCMN to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 66 +++--- target/arm/tcg/a64.decode | 6 ++-- 2 files changed, 25 insertions(+), 47 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 774689641d.

[PATCH 23/67] target/arm: Convert FMOV, FABS, FNEG (scalar) to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 104 ++--- target/arm/tcg/a64.decode | 7 +++ 2 files changed, 78 insertions(+), 33 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 2d3566e45c.

[PATCH 19/67] target/arm: Convert disas_cond_select to decodetree

This includes CSEL, CSINC, CSINV, CSNEG. Remove disas_data_proc_reg, as these were the last insns decoded by that function. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 84 ++ target/arm/tcg/a64.decode | 3 ++ 2 files changed, 17 in

[PATCH 52/67] target/arm: Convert FABS, FNEG (vector) to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 61 ++ target/arm/tcg/a64.decode | 7 2 files changed, 39 insertions(+), 29 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 613dcdb9a2.

[PATCH 57/67] target/arm: Convert [US]CVTF (vector, integer) scalar to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 35 -- target/arm/tcg/a64.decode | 6 ++ 2 files changed, 31 insertions(+), 10 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index bdeb0288f

[PATCH 29/67] target/arm: Convert FRINT{32, 64}[ZX] (scalar) to decodetree

Remove handle_fp_1src_single and handle_fp_1src_double as these were the last insns decoded by those functions. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 150 - target/arm/tcg/a64.decode | 5 ++ 2 files changed, 21 insertions(+),

[PATCH 38/67] target/arm: Introduce gen_gvec_cnt, gen_gvec_rbit

Add gvec interfaces for CNT and RBIT operations. Use ctpop8 for CNT and revbit+bswap for RBIT. Signed-off-by: Richard Henderson --- target/arm/helper.h | 4 ++-- target/arm/tcg/translate.h | 4 target/arm/tcg/gengvec.c| 16 target/arm/tcg/neon_hel

[PATCH 26/67] target/arm: Convert FSQRT (scalar) to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 70 +- target/arm/tcg/a64.decode | 1 + 2 files changed, 61 insertions(+), 10 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 4d945f2d5b..75

[PATCH 04/67] target/arm: Convert CRC32, CRC32C to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 101 + target/arm/tcg/a64.decode | 12 2 files changed, 53 insertions(+), 60 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 8b7ca2c68a

[PATCH 00/67] target/arm: AArch64 decodetree conversion, final part

Finish the conversion of all aarch64 instructions to decodetree. r~ Richard Henderson (67): target/arm: Use ### to separate 3rd-level sections in a64.decode target/arm: Convert UDIV, SDIV to decodetree target/arm: Convert LSLV, LSRV, ASRV, RORV to decodetree target/arm: Convert CRC32, CRC

[PATCH 14/67] target/arm: Convert disas_data_proc_3src to decodetree

This includes MADD, MSUB, SMADDL, SMSUBL, UMADDL, UMSUBL, SMULH, UMULH. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 119 - target/arm/tcg/a64.decode | 16 + 2 files changed, 59 insertions(+), 76 deletions(-) diff --git a/target

[PATCH 03/67] target/arm: Convert LSLV, LSRV, ASRV, RORV to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 46 -- target/arm/tcg/a64.decode | 4 +++ 2 files changed, 25 insertions(+), 25 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 9f687ba840..

[PATCH 32/67] target/arm: Convert FJCVTZS to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 41 +- target/arm/tcg/a64.decode | 2 ++ 2 files changed, 22 insertions(+), 21 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 68bef0963b..9

[PATCH 25/67] target/arm: Remove helper_sqrt_f16

This function is identical with helper_vfp_sqrth. Replace all uses. Signed-off-by: Richard Henderson --- target/arm/tcg/helper-a64.h| 1 - target/arm/tcg/helper-a64.c| 11 --- target/arm/tcg/translate-a64.c | 4 ++-- 3 files changed, 2 insertions(+), 14 deletions(-) diff --git

Re: [PATCH v12 15/15] hw/vmapple/vmapple: Add vmapple machine type

Thanks for testing, and thank you for putting all that effort into repeated reviews! I now also have a solution for the keyboard/mouse/USB issue in case you want to re-test with that applied on top. https://patchew.org/QEMU/20241201160316.96121-1-p...@philjordan.eu/ All the best, Phil On Sat, 30

Re: [PATCH v2 0/3] Allow to enable multifd and postcopy migration together

Hello Peter, On Fri, 29 Nov 2024 at 22:16, Peter Xu wrote: > I saw that there's still discussion in the previous version, while this > cover letter doesn't mention why it was ignored. Especially, at least to > me, what Fabiano commented on simplifying the flush condition check makes > senes to m

Re: [PATCH] hw/misc/vmfwupdate: Introduce hypervisor fw-cfg interface support

> On 29 Nov 2024, at 3:42 PM, Philippe Mathieu-Daudé wrote: > > On 29/11/24 10:16, Ani Sinha wrote: >> VM firmware update is a mechanism where the virtual machines can use their >> preferred and trusted firmware image in their execution environment without >> having to depend on a untrusted pa