Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/arm/tcg/translate-a64.c | 94 +++++++++++++++++++---------------
target/arm/tcg/a64.decode | 7 +++
2 files changed, 59 insertions(+), 42 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 22594a1149..00e55d42ff 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -7625,6 +7625,55 @@ static bool do_crc32(DisasContext *s, arg_rrr_e *a, bool
crc32c)
TRANS_FEAT(CRC32, aa64_crc32, do_crc32, a, false)
TRANS_FEAT(CRC32C, aa64_crc32, do_crc32, a, true)
+static bool do_subp(DisasContext *s, arg_rrr *a, bool setflag)
+{
+ TCGv_i64 tcg_n = read_cpu_reg_sp(s, a->rn, true);
+ TCGv_i64 tcg_m = read_cpu_reg_sp(s, a->rm, true);
+ TCGv_i64 tcg_d = cpu_reg(s, a->rd);
+
+ tcg_gen_sextract_i64(tcg_n, tcg_n, 0, 56);
+ tcg_gen_sextract_i64(tcg_m, tcg_m, 0, 56);
+
+ if (setflag) {
+ gen_sub_CC(true, tcg_d, tcg_n, tcg_m);
+ } else {
+ tcg_gen_sub_i64(tcg_d, tcg_n, tcg_m);
+ }
+ return true;
+}
+
+TRANS_FEAT(SUBP, aa64_mte_insn_reg, do_subp, a, false)
+TRANS_FEAT(SUBPS, aa64_mte_insn_reg, do_subp, a, true)
+
+static bool trans_IRG(DisasContext *s, arg_rrr *a)
+{
+ if (dc_isar_feature(aa64_mte_insn_reg, s)) {
+ TCGv_i64 tcg_rd = cpu_reg_sp(s, a->rd);
+ TCGv_i64 tcg_rn = cpu_reg_sp(s, a->rn);
+
+ if (s->ata[0]) {
+ gen_helper_irg(tcg_rd, tcg_env, tcg_rn, cpu_reg(s, a->rm));
+ } else {
+ gen_address_with_allocation_tag0(tcg_rd, tcg_rn);
+ }
+ return true;
+ }
+ return false;
+}
+
+static bool trans_GMI(DisasContext *s, arg_rrr *a)
+{
+ if (dc_isar_feature(aa64_mte_insn_reg, s)) {
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ tcg_gen_extract_i64(t, cpu_reg_sp(s, a->rn), 56, 4);
+ tcg_gen_shl_i64(t, tcg_constant_i64(1), t);
+ tcg_gen_or_i64(cpu_reg(s, a->rd), cpu_reg(s, a->rm), t);
+ return true;
+ }
+ return false;
+}
+
/* Logical (shifted register)
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
* +----+-----+-----------+-------+---+------+--------+------+------+
@@ -8528,48 +8577,6 @@ static void disas_data_proc_2src(DisasContext *s,
uint32_t insn)
}
switch (opcode) {
- case 0: /* SUBP(S) */
- if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
- goto do_unallocated;
- } else {
- TCGv_i64 tcg_n, tcg_m, tcg_d;
-
- tcg_n = read_cpu_reg_sp(s, rn, true);
- tcg_m = read_cpu_reg_sp(s, rm, true);
- tcg_gen_sextract_i64(tcg_n, tcg_n, 0, 56);
- tcg_gen_sextract_i64(tcg_m, tcg_m, 0, 56);
- tcg_d = cpu_reg(s, rd);
-
- if (setflag) {
- gen_sub_CC(true, tcg_d, tcg_n, tcg_m);
- } else {
- tcg_gen_sub_i64(tcg_d, tcg_n, tcg_m);
- }
- }
- break;
- case 4: /* IRG */
- if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
- goto do_unallocated;
- }
- if (s->ata[0]) {
- gen_helper_irg(cpu_reg_sp(s, rd), tcg_env,
- cpu_reg_sp(s, rn), cpu_reg(s, rm));
- } else {
- gen_address_with_allocation_tag0(cpu_reg_sp(s, rd),
- cpu_reg_sp(s, rn));
- }
- break;
- case 5: /* GMI */
- if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
- goto do_unallocated;
- } else {
- TCGv_i64 t = tcg_temp_new_i64();
-
- tcg_gen_extract_i64(t, cpu_reg_sp(s, rn), 56, 4);
- tcg_gen_shl_i64(t, tcg_constant_i64(1), t);
- tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t);
- }
- break;
case 12: /* PACGA */
if (sf == 0 || !dc_isar_feature(aa64_pauth, s)) {
goto do_unallocated;
@@ -8579,8 +8586,11 @@ static void disas_data_proc_2src(DisasContext *s,
uint32_t insn)
break;
default:
do_unallocated:
+ case 0: /* SUBP(S) */
case 2: /* UDIV */
case 3: /* SDIV */
+ case 4: /* IRG */
+ case 5: /* GMI */
case 8: /* LSLV */
case 9: /* LSRV */
case 10: /* ASRV */
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 1664f4793c..f0a5ffb1cd 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -26,6 +26,7 @@
%hlm 11:1 20:2
&r rn
+&rrr rd rn rm
&ri rd imm
&rri_sf rd rn imm sf
&rrr_sf rd rn rm sf
@@ -656,6 +657,7 @@ CPYE 00 011 1 01100 ..... .... 01 ..... .....
@cpy
# Data Processing (2-source)
+@rrr . .......... rm:5 ...... rn:5 rd:5 &rrr
@rrr_sf sf:1 .......... rm:5 ...... rn:5 rd:5 &rrr_sf
UDIV . 00 11010110 ..... 00001 0 ..... ..... @rrr_sf
@@ -675,6 +677,11 @@ CRC32C 0 00 11010110 ..... 0101 01 ..... .....
@rrr_h
CRC32C 0 00 11010110 ..... 0101 10 ..... ..... @rrr_s
CRC32C 1 00 11010110 ..... 0101 11 ..... ..... @rrr_d
+SUBP 1 00 11010110 ..... 000000 ..... ..... @rrr
+SUBPS 1 01 11010110 ..... 000000 ..... ..... @rrr
+IRG 1 00 11010110 ..... 000100 ..... ..... @rrr
+GMI 1 00 11010110 ..... 000101 ..... ..... @rrr
+
# Data Processing (1-source)
# Logical (shifted reg)
# Add/subtract (shifted reg)
--
2.43.0
