Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/arm/tcg/translate-a64.c | 67 +++++++++++++++++++++++++---------
target/arm/tcg/a64.decode | 3 ++
2 files changed, 53 insertions(+), 17 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 31272c1878..1e8cb07992 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -9176,6 +9176,51 @@ static bool do_fabs_fneg_v(DisasContext *s, arg_qrr_e
*a, bool neg)
TRANS(FABS_v, do_fabs_fneg_v, a, false)
TRANS(FNEG_v, do_fabs_fneg_v, a, true)
+static bool do_fp1_vector(DisasContext *s, arg_qrr_e *a,
+ const FPScalar1 *f, int rmode)
+{
+ TCGv_i32 tcg_rmode = NULL;
+ TCGv_ptr fpst;
+ int check = fp_access_check_vector_hsd(s, a->q, a->esz);
+
+ if (check <= 0) {
+ return check == 0;
+ }
+
+ fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ if (rmode >= 0) {
+ tcg_rmode = gen_set_rmode(rmode, fpst);
+ }
+
+ if (a->esz == MO_64) {
+ TCGv_i64 t64 = tcg_temp_new_i64();
+
+ for (int pass = 0; pass < 2; ++pass) {
+ read_vec_element(s, t64, a->rn, pass, MO_64);
+ f->gen_d(t64, t64, fpst);
+ write_vec_element(s, t64, a->rd, pass, MO_64);
+ }
+ } else {
+ TCGv_i32 t32 = tcg_temp_new_i32();
+ void (*gen)(TCGv_i32, TCGv_i32, TCGv_ptr)
+ = (a->esz == MO_16 ? f->gen_h : f->gen_s);
+
+ for (int pass = 0, n = (a->q ? 16 : 8) >> a->esz; pass < n; ++pass) {
+ read_vec_element_i32(s, t32, a->rn, pass, a->esz);
+ gen(t32, t32, fpst);
+ write_vec_element_i32(s, t32, a->rd, pass, a->esz);
+ }
+ }
+ clear_vec_high(s, a->q, a->rd);
+
+ if (rmode >= 0) {
+ gen_restore_rmode(tcg_rmode, fpst);
+ }
+ return true;
+}
+
+TRANS(FSQRT_v, do_fp1_vector, a, &f_scalar_fsqrt, -1)
+
/* Common vector code for handling integer to FP conversion */
static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
int elements, int is_signed,
@@ -9473,9 +9518,6 @@ static void handle_2misc_64(DisasContext *s, int opcode,
bool u,
* requires them.
*/
switch (opcode) {
- case 0x7f: /* FSQRT */
- gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, tcg_fpstatus);
- break;
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
case 0x1c: /* FCVTAS */
@@ -9519,6 +9561,7 @@ static void handle_2misc_64(DisasContext *s, int opcode,
bool u,
case 0xb: /* ABS, NEG */
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
+ case 0x7f: /* FSQRT */
g_assert_not_reached();
}
}
@@ -10016,13 +10059,6 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
}
handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd);
return;
- case 0x7f: /* FSQRT */
- need_fpstatus = true;
- if (size == 3 && !is_q) {
- unallocated_encoding(s);
- return;
- }
- break;
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
case 0x3a: /* FCVTPS */
@@ -10116,6 +10152,7 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
case 0x56: /* FCVTXN, FCVTXN2 */
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
+ case 0x7f: /* FSQRT */
unallocated_encoding(s);
return;
}
@@ -10188,9 +10225,6 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
{
/* Special cases for 32 bit elements */
switch (opcode) {
- case 0x7f: /* FSQRT */
- gen_helper_vfp_sqrts(tcg_res, tcg_op, tcg_fpstatus);
- break;
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
case 0x1c: /* FCVTAS */
@@ -10233,6 +10267,7 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
case 0x7: /* SQABS, SQNEG */
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
+ case 0x7f: /* FSQRT */
g_assert_not_reached();
}
}
@@ -10376,11 +10411,11 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
rmode = FPROUNDING_ZERO;
break;
case 0x7d: /* FRSQRTE */
- case 0x7f: /* FSQRT (vector) */
break;
default:
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
+ case 0x7f: /* FSQRT (vector) */
unallocated_encoding(s);
return;
}
@@ -10486,12 +10521,10 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
case 0x7d: /* FRSQRTE */
gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
break;
- case 0x7f: /* FSQRT */
- gen_helper_vfp_sqrth(tcg_res, tcg_op, tcg_fpstatus);
- break;
default:
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
+ case 0x7f: /* FSQRT */
g_assert_not_reached();
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index fec6aa7a23..f6b334b148 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1694,3 +1694,6 @@ FABS_v 0.00 1110 1.1 00000 11111 0 ..... .....
@qrr_sd
FNEG_v 0.10 1110 111 11000 11111 0 ..... ..... @qrr_h
FNEG_v 0.10 1110 1.1 00000 11111 0 ..... ..... @qrr_sd
+
+FSQRT_v 0.10 1110 111 11001 11111 0 ..... ..... @qrr_h
+FSQRT_v 0.10 1110 1.1 00001 11111 0 ..... ..... @qrr_sd
--
2.43.0
