Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/arm/tcg/translate-a64.c | 123 +++++++++++++++++++++------------
target/arm/tcg/a64.decode | 11 +++
2 files changed, 89 insertions(+), 45 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index e0b5dd76b0..6564fff6b9 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8821,6 +8821,78 @@ static bool trans_FMOV_xu(DisasContext *s, arg_rr *a)
return true;
}
+typedef struct ENVScalar1 {
+ NeonGenOneOpEnvFn *gen_bhs[3];
+ NeonGenOne64OpEnvFn *gen_d;
+} ENVScalar1;
+
+static bool do_env_scalar1(DisasContext *s, arg_rr_e *a, const ENVScalar1 *f)
+{
+ if (!fp_access_check(s)) {
+ return true;
+ }
+ if (a->esz == MO_64) {
+ TCGv_i64 t = read_fp_dreg(s, a->rn);
+ f->gen_d(t, tcg_env, t);
+ write_fp_dreg(s, a->rd, t);
+ } else {
+ TCGv_i32 t = tcg_temp_new_i32();
+
+ read_vec_element_i32(s, t, a->rn, 0, a->esz);
+ f->gen_bhs[a->esz](t, tcg_env, t);
+ write_fp_sreg(s, a->rd, t);
+ }
+ return true;
+}
+
+static bool do_env_vector1(DisasContext *s, arg_qrr_e *a, const ENVScalar1 *f)
+{
+ if (a->esz == MO_64 && !a->q) {
+ return false;
+ }
+ if (!fp_access_check(s)) {
+ return true;
+ }
+ if (a->esz == MO_64) {
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ for (int i = 0; i < 2; ++i) {
+ read_vec_element(s, t, a->rn, i, MO_64);
+ f->gen_d(t, tcg_env, t);
+ write_vec_element(s, t, a->rd, i, MO_64);
+ }
+ } else {
+ TCGv_i32 t = tcg_temp_new_i32();
+ int n = (a->q ? 16 : 8) >> a->esz;
+
+ for (int i = 0; i < n; ++i) {
+ read_vec_element_i32(s, t, a->rn, i, a->esz);
+ f->gen_bhs[a->esz](t, tcg_env, t);
+ write_vec_element_i32(s, t, a->rd, i, a->esz);
+ }
+ }
+ clear_vec_high(s, a->q, a->rd);
+ return true;
+}
+
+static const ENVScalar1 f_scalar_sqabs = {
+ { gen_helper_neon_qabs_s8,
+ gen_helper_neon_qabs_s16,
+ gen_helper_neon_qabs_s32 },
+ gen_helper_neon_qabs_s64,
+};
+TRANS(SQABS_s, do_env_scalar1, a, &f_scalar_sqabs)
+TRANS(SQABS_v, do_env_vector1, a, &f_scalar_sqabs)
+
+static const ENVScalar1 f_scalar_sqneg = {
+ { gen_helper_neon_qneg_s8,
+ gen_helper_neon_qneg_s16,
+ gen_helper_neon_qneg_s32 },
+ gen_helper_neon_qneg_s64,
+};
+TRANS(SQNEG_s, do_env_scalar1, a, &f_scalar_sqneg)
+TRANS(SQNEG_v, do_env_vector1, a, &f_scalar_sqneg)
+
/* Common vector code for handling integer to FP conversion */
static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
int elements, int is_signed,
@@ -9133,13 +9205,6 @@ static void handle_2misc_64(DisasContext *s, int opcode,
bool u,
*/
tcg_gen_not_i64(tcg_rd, tcg_rn);
break;
- case 0x7: /* SQABS, SQNEG */
- if (u) {
- gen_helper_neon_qneg_s64(tcg_rd, tcg_env, tcg_rn);
- } else {
- gen_helper_neon_qabs_s64(tcg_rd, tcg_env, tcg_rn);
- }
- break;
case 0xa: /* CMLT */
cond = TCG_COND_LT;
do_cmop:
@@ -9202,6 +9267,7 @@ static void handle_2misc_64(DisasContext *s, int opcode,
bool u,
gen_helper_frint64_d(tcg_rd, tcg_rn, tcg_fpstatus);
break;
default:
+ case 0x7: /* SQABS, SQNEG */
g_assert_not_reached();
}
}
@@ -9544,8 +9610,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext
*s, uint32_t insn)
TCGv_ptr tcg_fpstatus;
switch (opcode) {
- case 0x7: /* SQABS / SQNEG */
- break;
case 0xa: /* CMLT */
if (u) {
unallocated_encoding(s);
@@ -9644,6 +9708,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext
*s, uint32_t insn)
break;
default:
case 0x3: /* USQADD / SUQADD */
+ case 0x7: /* SQABS / SQNEG */
unallocated_encoding(s);
return;
}
@@ -9673,18 +9738,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext
*s, uint32_t insn)
read_vec_element_i32(s, tcg_rn, rn, 0, size);
switch (opcode) {
- case 0x7: /* SQABS, SQNEG */
- {
- NeonGenOneOpEnvFn *genfn;
- static NeonGenOneOpEnvFn * const fns[3][2] = {
- { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 },
- { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 },
- { gen_helper_neon_qabs_s32, gen_helper_neon_qneg_s32 },
- };
- genfn = fns[size][u];
- genfn(tcg_rd, tcg_env, tcg_rn);
- break;
- }
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
case 0x1c: /* FCVTAS */
@@ -9702,6 +9755,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext
*s, uint32_t insn)
tcg_fpstatus);
break;
default:
+ case 0x7: /* SQABS, SQNEG */
g_assert_not_reached();
}
@@ -10059,12 +10113,6 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
return;
}
break;
- case 0x7: /* SQABS, SQNEG */
- if (size == 3 && !is_q) {
- unallocated_encoding(s);
- return;
- }
- break;
case 0xc ... 0xf:
case 0x16 ... 0x1f:
{
@@ -10235,6 +10283,7 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
}
default:
case 0x3: /* SUQADD, USQADD */
+ case 0x7: /* SQABS, SQNEG */
unallocated_encoding(s);
return;
}
@@ -10325,13 +10374,6 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
tcg_gen_clrsb_i32(tcg_res, tcg_op);
}
break;
- case 0x7: /* SQABS, SQNEG */
- if (u) {
- gen_helper_neon_qneg_s32(tcg_res, tcg_env, tcg_op);
- } else {
- gen_helper_neon_qabs_s32(tcg_res, tcg_env, tcg_op);
- }
- break;
case 0x2f: /* FABS */
gen_vfp_abss(tcg_res, tcg_op);
break;
@@ -10380,6 +10422,7 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
gen_helper_frint64_s(tcg_res, tcg_op, tcg_fpstatus);
break;
default:
+ case 0x7: /* SQABS, SQNEG */
g_assert_not_reached();
}
} else {
@@ -10395,17 +10438,6 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
gen_helper_neon_cnt_u8(tcg_res, tcg_op);
}
break;
- case 0x7: /* SQABS, SQNEG */
- {
- NeonGenOneOpEnvFn *genfn;
- static NeonGenOneOpEnvFn * const fns[2][2] = {
- { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 },
- { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 },
- };
- genfn = fns[size][u];
- genfn(tcg_res, tcg_env, tcg_op);
- break;
- }
case 0x4: /* CLS, CLZ */
if (u) {
if (size == 0) {
@@ -10422,6 +10454,7 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
}
break;
default:
+ case 0x7: /* SQABS, SQNEG */
g_assert_not_reached();
}
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 787e673f7c..d26ee07597 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -47,6 +47,7 @@
@rr_h ........ ... ..... ...... rn:5 rd:5 &rr_e esz=1
@rr_s ........ ... ..... ...... rn:5 rd:5 &rr_e esz=2
@rr_d ........ ... ..... ...... rn:5 rd:5 &rr_e esz=3
+@rr_e ........ esz:2 . ..... ...... rn:5 rd:5 &rr_e
@rr_sd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_sd
@rr_hsd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_hsd
@@ -1626,3 +1627,13 @@ UQRSHRN_si 0111 11110 .... ... 10011 1 ..... .....
@shri_s
SQRSHRUN_si 0111 11110 .... ... 10001 1 ..... ..... @shri_b
SQRSHRUN_si 0111 11110 .... ... 10001 1 ..... ..... @shri_h
SQRSHRUN_si 0111 11110 .... ... 10001 1 ..... ..... @shri_s
+
+# Advanced SIMD scalar two-register miscellaneous
+
+SQABS_s 0101 1110 ..1 00000 01111 0 ..... ..... @rr_e
+SQNEG_s 0111 1110 ..1 00000 01111 0 ..... ..... @rr_e
+
+# Advanced SIMD two-register miscellaneous
+
+SQABS_v 0.00 1110 ..1 00000 01111 0 ..... ..... @qrr_e
+SQNEG_v 0.10 1110 ..1 00000 01111 0 ..... ..... @qrr_e
--
2.43.0
