Convert the next-kbd device from the legacy UI qemu_add_kbd_event_handler()
function to use qemu_input_handler_register().
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/next-kbd.c | 158 +
1 file changed, 103 insertions(+), 55 deletions(-)
diff --git a/
On Wed, Oct 30, 2024, 1:03 PM Paolo Bonzini wrote:
> On Tue, Oct 29, 2024 at 9:08 PM Dorjoy Chowdhury
> wrote:
> > Thanks for fixing. The attached patch looks great to me. I just have
> > one suggestion. Now that the CONFIG_* symbols have the dependencies
> > listed explicitly in the Kconfig fil
Mark Cave-Ayland writes:
> Convert the next-kbd device from the legacy UI qemu_add_kbd_event_handler()
> function to use qemu_input_handler_register().
If that is the last user we should probably remove the function as well.
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
On Wed, Oct 30, 2024 at 04:44:54PM +0800, Zhao Liu wrote:
> On Tue, Oct 29, 2024 at 04:18:54PM +0100, Paolo Bonzini wrote:
> > Date: Tue, 29 Oct 2024 16:18:54 +0100
> > From: Paolo Bonzini
> > Subject: [PATCH 4/8] target/i386: add AVX10 feature and AVX10 version
> > property
> > X-Mailer: git-sen
On Tue, Oct 29, 2024 at 05:16:05PM -0400, Peter Xu wrote:
> X86 IOMMUs cannot be created more than one on a system yet. Make it a
> singleton so it guards the system from accidentally create yet another
> IOMMU object when one already presents.
>
> Now if someone tries to create more than one, e.
v1 -> v2:
- Change to CXL Spec identification and description
- Add CXIMS, RDPAS and CSDS structures
- Fix code style problems
RFC because
- Less experience and not particularly confident in edk2 area so this might be
stupidly broken in a way I've not considered.
I am trying to support cxl on Q
Gcrypt does not return negative values on error, it returns non-zero
values. This caused QEMU not to detect failure to open an unsupported
hash, resulting in a later crash trying to use a NULL context.
Signed-off-by: Daniel P. Berrangé
---
crypto/hash-gcrypt.c | 4 ++--
1 file changed, 2 inserti
gcrypto has the ability to dynamically disable hash/hmac algorithms
at runtime, so QEMU must perform a runtime check.
Signed-off-by: Daniel P. Berrangé
---
crypto/hash-gcrypt.c | 2 +-
crypto/hmac-gcrypt.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/crypto/hash-gcrypt.
This fixes the test suite when gcrypt disables some algorithms
at runtime.
Daniel P. Berrangé (2):
crypto: fix error check on gcry_md_open
crypto: perform runtime check for hash/hmac support in gcrypt
crypto/hash-gcrypt.c | 6 +++---
crypto/hmac-gcrypt.c | 2 +-
2 files changed, 4 insertions
Il mer 30 ott 2024, 04:23 Tao Su ha scritto:
> > I don't have a Granite Rapids machine, so please test! :)
>
> I test it on Granite Rapids and all meet expection with my minor changes on
> patch4 :)
>
Thanks, can you send v3?
Paolo
>
> > Paolo
> >
> > Paolo Bonzini (3):
> > target/i386: cpu:
Hey Paolo,
On 29.10.24 20:32, Paolo Bonzini wrote:
On 10/23/24 16:27, Dorjoy Chowdhury wrote:
On Wed, Oct 16, 2024 at 7:58 PM Dorjoy Chowdhury
wrote:
Ping
This patch series has been reviewed by Alex. I am not sure if it needs
more review. If not, maybe this can be picked up for merging. Th
On Tue, Oct 29, 2024 at 04:18:57PM +0100, Paolo Bonzini wrote:
> Date: Tue, 29 Oct 2024 16:18:57 +0100
> From: Paolo Bonzini
> Subject: [PATCH 7/8] target/i386: Add AVX512 state when AVX10 is supported
> X-Mailer: git-send-email 2.47.0
>
> From: Tao Su
>
> AVX10 state enumeration in CPUID leaf
On Tue, Oct 29, 2024 at 04:18:55PM +0100, Paolo Bonzini wrote:
> Date: Tue, 29 Oct 2024 16:18:55 +0100
> From: Paolo Bonzini
> Subject: [PATCH 5/8] target/i386: add CPUID.24 features for AVX10
> X-Mailer: git-send-email 2.47.0
>
> From: Tao Su
>
> Introduce features for the supported vector bit
On Tue, Oct 29, 2024 at 9:08 PM Dorjoy Chowdhury wrote:
> Thanks for fixing. The attached patch looks great to me. I just have
> one suggestion. Now that the CONFIG_* symbols have the dependencies
> listed explicitly in the Kconfig files, maybe we don't need the
> explicit dependencies in the meso
On Tue, Oct 29, 2024 at 04:18:54PM +0100, Paolo Bonzini wrote:
> Date: Tue, 29 Oct 2024 16:18:54 +0100
> From: Paolo Bonzini
> Subject: [PATCH 4/8] target/i386: add AVX10 feature and AVX10 version
> property
> X-Mailer: git-send-email 2.47.0
>
> From: Tao Su
>
> When AVX10 enable bit is set, t
This adds #defines and struct typedefs for the various structure
types in the CXL3.1 CXL Early Discovery Table (CEDT).
Signed-off-by: Yuquan Wang
---
.../IndustryStandard/CxlEarlyDiscoveryTable.h | 113 ++
1 file changed, 113 insertions(+)
create mode 100644 MdePkg/Include/Indus
On Tue, Oct 29, 2024 at 05:16:00PM -0400, Peter Xu wrote:
> v1: https://lore.kernel.org/r/20241024165627.1372621-1-pet...@redhat.com
> Meanwhile, migration has a long standing issue on current_migration
> pointer, where it can point to freed data after the migration object is
> finalized. It is d
On 10/29/24 18:58, Daniel Henrique Barboza wrote:
On 9/18/24 2:14 PM, Max Chou wrote:
The vm field of the vector load/store whole register instruction's
encoding is 1.
The helper function of the vector load/store whole register instructions
may need the vdata.vm field to do some optimizations.
On Wed, Oct 30, 2024 at 11:05:23AM +0800, Tao Su wrote:
> Date: Wed, 30 Oct 2024 11:05:23 +0800
> From: Tao Su
> Subject: Re: [PATCH 4/8] target/i386: add AVX10 feature and AVX10 version
> property
>
> On Tue, Oct 29, 2024 at 04:18:54PM +0100, Paolo Bonzini wrote:
> > From: Tao Su
>
> [ ... ]
On 10/30/24 09:43, Alexander Graf wrote:
Hi,
sorry about the delay -- the patches failed CI and I didn't have much
time to investigate until now.
The issues are basically:
1) some rST syntax errors
2) failures on non-Linux due to lack of VHOST_USER
3) failures on 32-bit due to uint64_t/long
On Wed, Oct 30, 2024 at 10:33:23AM +, Daniel P. Berrangé wrote:
> On Tue, Oct 29, 2024 at 05:16:05PM -0400, Peter Xu wrote:
> > X86 IOMMUs cannot be created more than one on a system yet. Make it a
> > singleton so it guards the system from accidentally create yet another
> > IOMMU object when
> > > Introduce avx10-version property so that avx10 version can be controlled
> > > by user and cpu model. Per spec, avx10 version can never be 0, the default
> > > value of avx10-version is set to 0 to determine whether it is specified by
> > > user.
> >
> > The default value of 0 does not refle
Hi Alistair,
On 10/30/24 03:54, Alistair Francis wrote:
On Thu, Oct 17, 2024 at 5:26 PM Sai Pavan Boddu wrote:
diff --git a/hw/riscv/microblaze-v-virt.c b/hw/riscv/microblaze-v-virt.c
new file mode 100644
index 000..6603e6d6b06
--- /dev/null
+++ b/hw/riscv/microblaze-v-virt.c
@@ -0,0
On Wed, Oct 30, 2024 at 09:01:03AM -0400, Peter Xu wrote:
> On Wed, Oct 30, 2024 at 10:33:23AM +, Daniel P. Berrangé wrote:
> > On Tue, Oct 29, 2024 at 05:16:05PM -0400, Peter Xu wrote:
> > > X86 IOMMUs cannot be created more than one on a system yet. Make it a
> > > singleton so it guards the
On Wed, Oct 30, 2024 at 09:48:07AM +, Daniel P. Berrangé wrote:
> On Tue, Oct 29, 2024 at 05:16:00PM -0400, Peter Xu wrote:
> > v1: https://lore.kernel.org/r/20241024165627.1372621-1-pet...@redhat.com
>
> > Meanwhile, migration has a long standing issue on current_migration
> > pointer, where
As shown below, if a virtio PCI device is attached under a pci-bridge, the MR
of VirtIOPCIRegion does not belong to any address space. So memory_region_find
cannot be used to search for this MR.
Introduce the virtio-pci and pci_bridge address spaces to solve this problem.
Before:
memory-region: p
On 10/30/24 13:30, Phil Dennis-Jordan wrote:
On Tue, 29 Oct 2024 at 14:05, Paolo Bonzini wrote:
QEMU does not show availability of MPX in CPUID when running under
Hypervisor.framework. Therefore, in the unlikely chance that the host
has MPX enabled, hide those bits from leaf 0xD as well.
To
On Tue, 29 Oct 2024 09:37:59 -0700
Fan Ni wrote:
> On Mon, Sep 16, 2024 at 06:35:14PM +0100, Jonathan Cameron wrote:
> > Copied from gen_pcie_root_port.c
> > Drop the previous code that ensured a valid value in s->width, s->speed
> > as now a default is provided so this will always be set.
> >
>
On Wed, 30 Oct 2024, Lei Huang wrote:
Use a convergence factor to make the VM's input
global coordinates more closely approach the global
coordinates of host.
Change-Id: I2c3f12f1fe7dfb9306d1fc40c4fd4d299937f4c6
Signed-off-by: Lei Huang
---
ui/sdl2.c | 32 ++--
1 file
default case has no condition. So if it is placed
higher that other cases, they are unreachable.
Move dafult case down.
Found by Linux Verification Center (linuxtesting.org)
Signed-off-by: Anastasia Belova
---
monitor/hmp-cmds-target.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
On Wed, Oct 30, 2024 at 9:10 AM Noah Goldstein wrote:
>
> The new option '-qemu-children' makes it so that on `execve` the child
> process will be launch by the same `qemu` executable that is currently
> running along with its current commandline arguments.
>
> The motivation for the change is to
On Wed, Oct 30, 2024 at 09:13:24PM +0800, Gao Shiyuan wrote:
> As shown below, if a virtio PCI device is attached under a pci-bridge, the MR
> of VirtIOPCIRegion does not belong to any address space. So memory_region_find
> cannot be used to search for this MR.
>
> Introduce the virtio-pci and pci
The new option '-qemu-children' makes it so that on `execve` the child
process will be launch by the same `qemu` executable that is currently
running along with its current commandline arguments.
The motivation for the change is to make it so that plugins running
through `qemu` can continue to run
On 28/10/2024 21:06, Peter Xu wrote:
External email: Use caution opening links or attachments
On Mon, Oct 28, 2024 at 07:20:27PM +0200, Avihai Horon wrote:
On 28/10/2024 18:58, Peter Xu wrote:
External email: Use caution opening links or attachments
On Mon, Oct 28, 2024 at 06:41:42PM +020
This helper is mostly the same as migration_is_running(), except that one
has COLO reported as true, the other has CANCELLING reported as true.
Per my past years experience on the state changes, none of them should
matter.
To make it slightly safer, report both COLO || CANCELLING to be true in
mi
On 9/18/24 2:14 PM, Max Chou wrote:
The unmasked unit-stride fault-only-first load instructions are similar
to the unmasked unit-stride load/store instructions that is suitable to
be optimized by using a direct access to host ram fast path.
Signed-off-by: Max Chou
---
Reviewed-by: Daniel
On 14/10/24 15:48, Roque Arcudia Hernandez wrote:
From: Nabih Estefan
Converting error to trace message to avoid spamming of message when
there is nothing to transmit.
Signed-off-by: Nabih Estefan
Signed-off-by: Roque Arcudia Hernandez
---
hw/net/npcm_gmac.c | 5 ++---
hw/net/trace-event
On Wed, Oct 30, 2024 at 05:58:15PM +, Daniel P. Berrangé wrote:
> That's a result from moving the "assert()" into the constructor.
> The assert(!current_migration) can be kept in migration_object_init,
> the constructor could conditionally set current_migration only if it
> is NULL, and the fin
On 30/10/24 07:11, Daniel P. Berrangé wrote:
Gcrypt does not return negative values on error, it returns non-zero
values. This caused QEMU not to detect failure to open an unsupported
hash, resulting in a later crash trying to use a NULL context.
Signed-off-by: Daniel P. Berrangé
---
crypto/h
On Mon, Oct 28, 2024 at 02:59:17PM +0800, Zhao Liu wrote:
> (+John)
>
> Hi Babu,
>
> This patch is fine for me.
>
> However, users recently reported an issue with SUCCOR support on AMD
> hosts: https://gitlab.com/qemu-project/qemu/-/issues/2571.
>
> Could you please double check and clarify tha
On Wed, Oct 30, 2024 at 06:07:08PM +, Daniel P. Berrangé wrote:
> On Tue, Oct 29, 2024 at 05:16:00PM -0400, Peter Xu wrote:
> > v1: https://lore.kernel.org/r/20241024165627.1372621-1-pet...@redhat.com
> >
> > This patchset introduces the singleton interface for QOM. I didn't add a
> > changel
On 9/18/24 2:14 PM, Max Chou wrote:
The vector unit-stride whole register load/store instructions are
similar to unmasked unit-stride load/store instructions that is suitable
to be optimized by using a direct access to host ram fast path.
Because the vector whole register load/store instructi
We have received a sponsorship from DigitalOcean, so add it next to Azure (in
alphabetical order) on the sponsors page of QEMU's website
Signed-off-by: Paolo Bonzini
---
sponsors.md | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/sponsors.md b/sponsors.md
index efbec
On Wed, 30 Oct 2024 at 14:35, Paolo Bonzini wrote:
>
> On 10/30/24 13:30, Phil Dennis-Jordan wrote:
> > On Tue, 29 Oct 2024 at 14:05, Paolo Bonzini wrote:
> >>
> >> QEMU does not show availability of MPX in CPUID when running under
> >> Hypervisor.framework. Therefore, in the unlikely chance tha
Thanks for the review Richard.
On 10/30/24 11:40, Richard Henderson wrote:
On 10/29/24 19:43, Paolo Savini wrote:
This patch optimizes the emulation of unit-stride load/store RVV
instructions
when the data being loaded/stored per iteration amounts to 16 bytes
or more.
The optimization consists
Hello,
Is there any feedback for this patch?
Thanks
Roque
On Mon, Oct 14, 2024 at 11:49 AM Roque Arcudia Hernandez
wrote:
>
> From: Nabih Estefan
>
> Converting error to trace message to avoid spamming of message when
> there is nothing to transmit.
>
> Signed-off-by: Nabih Estefan
> Signed-
Hello,
This is the second version of the patch. I have taken into
consideration the feedback from the first discussion thread. Is there
anything else to do?
Thanks
Roque
On Thu, Oct 17, 2024 at 8:37 AM Roque Arcudia Hernandez
wrote:
>
> This patch series modifies the gdbstub to address a bug r
Ping for missing reviews; particularly patches 11, 13 and 14.
https://lore.kernel.org/qemu-devel/20241025160209.194307-12-pbonz...@redhat.com/
https://lore.kernel.org/qemu-devel/20241025160209.194307-14-pbonz...@redhat.com/
https://lore.kernel.org/qemu-devel/20241025160209.194307-15
On Wed, Oct 30, 2024 at 04:13:57PM +, Daniel P. Berrangé wrote:
> On Wed, Oct 30, 2024 at 09:13:13AM -0400, Peter Xu wrote:
> > On Wed, Oct 30, 2024 at 09:48:07AM +, Daniel P. Berrangé wrote:
> > > On Tue, Oct 29, 2024 at 05:16:00PM -0400, Peter Xu wrote:
> > > > v1: https://lore.kernel.org
On Wed, Oct 30, 2024 at 10:05:51PM +0800, Tao Su wrote:
> Date: Wed, 30 Oct 2024 22:05:51 +0800
> From: Tao Su
> Subject: Re: [PATCH 4/8] target/i386: add AVX10 feature and AVX10 version
> property
>
> On Wed, Oct 30, 2024 at 09:21:36PM +0800, Zhao Liu wrote:
> > > > > Introduce avx10-version pr
From: Hyman Huang
Signed-off-by: Hyman Huang
Reviewed-by: Fabiano Rosas
Link:
https://lore.kernel.org/r/5e33b423d0b8506e5cb33fff42b50aa301b7731b.1729146786.git.yong.hu...@smartx.com
Signed-off-by: Peter Xu
---
accel/tcg/icount-common.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/accel
From: Hanna Czenczek
migration/savevm.c contains some calls to vmstate_save() that are
followed by migrate_set_error() if the integer return value indicates an
error. migrate_set_error() requires that the `Error *` object passed to
it is set. Therefore, vmstate_save() is assumed to always set *
Per previous discussion [1,2], this patch deprecates query-migrationthreads
command.
To summarize, the major reason of the deprecation is due to no sensible way
to consume the API properly:
(1) The reported list of threads are incomplete (ignoring destination
threads and non-multifd threa
Both migration thread or background snapshot thread will take a refcount of
the migration object at the entrace of the thread function.
That makes sense, because it protects the object from being freed by the
main thread in migration_shutdown() later, but it might still race with it
if the thread
It's only used within migration/, so it shouldn't be exported.
Reviewed-by: Cédric Le Goater
Reviewed-by: Fabiano Rosas
Link: https://lore.kernel.org/r/20241024213056.1395400-3-pet...@redhat.com
Signed-off-by: Peter Xu
---
include/migration/misc.h | 3 ---
migration/migration.h| 4
2
The cleanup function can in many cases needs cleanup on its own.
The major thing we want to do here is not referencing to_dst_file when
without the file mutex. When at it, touch things elsewhere too to make it
look slightly better in general.
One thing to mention is, migration_thread has its own
On Tue, Oct 29, 2024 at 05:16:00PM -0400, Peter Xu wrote:
> v1: https://lore.kernel.org/r/20241024165627.1372621-1-pet...@redhat.com
>
> This patchset introduces the singleton interface for QOM. I didn't add a
> changelog because there're quite a few changes here and there, plus new
> patches. S
On Wed, Oct 30, 2024 at 04:22:18PM +0100, Paolo Bonzini wrote:
> We have received a sponsorship from DigitalOcean, so add it next to Azure (in
> alphabetical order) on the sponsors page of QEMU's website
>
> Signed-off-by: Paolo Bonzini
> ---
> sponsors.md | 9 ++---
> 1 file changed, 6 inse
On Wed, Oct 30, 2024 at 05:15:05PM +0100, Cornelia Huck wrote:
> On Mon, Oct 28 2024, Oliver Upton wrote:
>
> > On Mon, Oct 28, 2024 at 04:48:18PM +, Peter Maydell wrote:
> >> On Mon, 28 Oct 2024 at 16:35, Daniel P. Berrangé
> >> wrote:
> >> >
> >> > On Mon, Oct 28, 2024 at 04:16:31PM +
On 9/18/24 2:14 PM, Max Chou wrote:
This commit references the sve_ldN_r/sve_stN_r helper functions in ARM
target to optimize the vector unmasked unit-stride load/store
implementation with following optimizations:
* Get the page boundary
* Probing pages/resolving host memory address at the be
On 10/30/24 11:17 AM, Alexey Baturo wrote:
Hi Daniel,
Let's try to push it before EOY.
I'm planning to start working on it in the first half of November.
Does that work for you?
Fine by me. We can add it to Alistair's tree for 10.0 to be upstreamed in
January 2025.
Thanks,
Daniel
Than
It's only used within migration/.
Reviewed-by: Cédric Le Goater
Reviewed-by: Fabiano Rosas
Link: https://lore.kernel.org/r/20241024213056.1395400-4-pet...@redhat.com
Signed-off-by: Peter Xu
---
include/migration/misc.h | 1 -
migration/ram.h | 1 +
2 files changed, 1 insertion(+), 1 d
From: Hyman Huang
Move cpu-throttle.c from system to migration since it's
only used for migration; this makes us avoid exporting the
util functions and variables in misc.h but export them in
migration.h when implementing the periodic ramblock dirty
sync feature in the upcoming commits.
Since CPU
On Wed, Oct 30, 2024 at 01:51:54PM -0400, Peter Xu wrote:
> On Wed, Oct 30, 2024 at 04:13:57PM +, Daniel P. Berrangé wrote:
> > On Wed, Oct 30, 2024 at 09:13:13AM -0400, Peter Xu wrote:
> > > On Wed, Oct 30, 2024 at 09:48:07AM +, Daniel P. Berrangé wrote:
> > > > On Tue, Oct 29, 2024 at 05:
From: Hyman Huang
Signed-off-by: Hyman Huang
Reviewed-by: Peter Xu
Reviewed-by: Fabiano Rosas
Link:
https://lore.kernel.org/r/cb61504f1a1e9d5f2ca4dac12e518deb076ce9f3.1729146786.git.yong.hu...@smartx.com
Signed-off-by: Peter Xu
---
tests/qtest/migration-test.c | 32 +
On Wed, Oct 30, 2024 at 10:09:38AM +0800, Yong Huang wrote:
> On Wed, Oct 30, 2024 at 12:21 AM Peter Xu wrote:
>
> > On Wed, Oct 23, 2024 at 10:09:51AM +0800, yong.hu...@smartx.com wrote:
> > > From: Hyman Huang
> > >
> > > KVM always returns 1 when userspace retrieves a dirty bitmap for
> > > t
On Wed, Oct 30, 2024 at 09:13:13AM -0400, Peter Xu wrote:
> On Wed, Oct 30, 2024 at 09:48:07AM +, Daniel P. Berrangé wrote:
> > On Tue, Oct 29, 2024 at 05:16:00PM -0400, Peter Xu wrote:
> > > v1: https://lore.kernel.org/r/20241024165627.1372621-1-pet...@redhat.com
> >
> > > Meanwhile, migratio
On Mon, Oct 28 2024, Oliver Upton wrote:
> On Mon, Oct 28, 2024 at 04:48:18PM +, Peter Maydell wrote:
>> On Mon, 28 Oct 2024 at 16:35, Daniel P. Berrangé wrote:
>> >
>> > On Mon, Oct 28, 2024 at 04:16:31PM +, Peter Maydell wrote:
>> > > On Fri, 25 Oct 2024 at 14:24, Daniel P. Berrangé
On Tue, 29 Oct 2024 at 20:47, wrote:
> >Our coding style for multiline comments says
> >/*
> > * they look like this, with the opening and closing markers on
> > * lines of their own
> > */
>
> I will changed that.
>
> It do not seem to be followed in In hw/intc/armv7m_nvic.c, but my new comment
/migration-20241030-pull-request
for you to fetch changes up to 53a60118d2654dd8e595e61f4e767ff747fd0b69:
migration/multifd: Zero p->flags before starting filling a packet (2024-10-30
11:32:41 -0400)
Migration pull request for sof
From: Hyman Huang
Since CPU throttling only occurs when auto-converge
is on, stop it conditionally.
Signed-off-by: Hyman Huang
Reviewed-by: Fabiano Rosas
Link:
https://lore.kernel.org/r/f0c787080bb9ab0c37952f0ca5bfaa525d5ddd14.1729146786.git.yong.hu...@smartx.com
Signed-off-by: Peter Xu
---
On 9/18/24 2:14 PM, Max Chou wrote:
In the vector unit-stride load/store helper functions. the vext_ldst_us
& vext_ldst_whole functions corresponding most of the execution time.
Inline the functions can avoid the function call overhead to improve the
helper function performance.
Signed-off-by
On Wed 30. Oct 2024 at 15:09, Anastasia Belova
wrote:
> default case has no condition. So if it is placed
> higher that other cases, they are unreachable.
>
> Move dafult case down.
>
The stylistic merits might be debatable, but: the order of cases in a
switch block in C does not matter, the def
Keep migration thread names together, so it's easier to see a list of all
possible migration threads.
Still two functional changes below besides the macro defintions:
- There's one dirty rate thread that we overlooked before, now we add
that too and name it as "mig/dirtyrate" following the ol
From: "Maciej S. Szmigiero"
There's a RAM load complete trace event but there wasn't its start equivalent.
Signed-off-by: Maciej S. Szmigiero
Reviewed-by: Fabiano Rosas
Link:
https://lore.kernel.org/r/94ddfa7ecb83a78f73b82867dd30c8767592d257.1730203967.git.maciej.szmigi...@oracle.com
Signed-o
From: Thomas Huth
The linker on OpenBSD complains:
ld: warning: dirtyrate.c:447 (../src/migration/dirtyrate.c:447)(...):
warning: strcpy() is almost always misused, please use strlcpy()
It's currently not a real problem in this case since both arrays
have the same size (256 bytes). But just i
From: "Maciej S. Szmigiero"
This way there aren't stale flags there.
p->flags can't contain SYNC to be sent at the next RAM packet since syncs
are now handled separately in multifd_send_thread.
Reviewed-by: Fabiano Rosas
Reviewed-by: Peter Xu
Signed-off-by: Maciej S. Szmigiero
Link:
https:/
From: Hyman Huang
The global static variable ram_state in fact is referred to by the
"rs" parameter in migration_bitmap_sync_precopy. For ease of calling
by the callees, use the global variable directly in
migration_bitmap_sync_precopy and remove "rs" parameter.
The migration_bitmap_sync_precopy
On 30/10/24 05:47, Daniel P. Berrangé wrote:
The 'loaded' property on TLS creds and secret objects was marked as
deprected in 6.0.0 and then marked as removed in 7.1.0.
Except it wasn't actually removed, it was just made read-only, while
claiming it was removed. Finish the long overdue removal j
On 10/30/24 1:35 AM, Anton Blanchard wrote:
vcompress packs vl or less fields into vd, so the tail starts after the
last packed field. This could be more clearly expressed in the ISA,
but for now this thread helps to explain it:
https://github.com/riscv/riscv-v-spec/issues/796
Signed-off-by:
From: Hyman Huang
When VM is configured with huge memory, the current throttle logic
doesn't look like to scale, because migration_trigger_throttle()
is only called for each iteration, so it won't be invoked for a long
time if one iteration can take a long time.
The periodic dirty sync aims to f
On Wed, Oct 30, 2024 at 08:58:21AM +0800, liequan che wrote:
> Introduce the SM3 cryptographic hash algorithm (GB/T 32905-2016).
>
> SM3 (GB/T 32905-2016) is a cryptographic standard issued by the
> Organization of State Commercial Cryptography Administration (OSCCA)
> as an authorized cryptograph
virtio_net_receive_rcu does not populate hash value and
hash type in case it needs to change queue number from the
initially defined by tap/tun to one calculated according
to the packet hash. Earlier commit a4c960e places the hash
value/type into local extra_hdr structure but the extra_hdr
is not f
On 2024/10/30 21:13, Yuri Benditovich wrote:
virtio_net_receive_rcu does not populate hash value and
hash type in case it needs to change queue number from the
initially defined by tap/tun to one calculated according
to the packet hash. Earlier commit a4c960e places the hash
value/type into local
On Tue, 29 Oct 2024 at 14:05, Paolo Bonzini wrote:
>
> QEMU does not show availability of MPX in CPUID when running under
> Hypervisor.framework. Therefore, in the unlikely chance that the host
> has MPX enabled, hide those bits from leaf 0xD as well.
To clarify: is there some kind of issue with
On Tue, Oct 29, 2024 at 03:44:01PM -0400, Michael S. Tsirkin wrote:
> On Wed, Oct 09, 2024 at 05:58:27PM +0800, Gao Shiyuan wrote:
> > As shown below, if a virtio PCI device is attached under a pci-bridge, the
> > MR
> > of VirtIOPCIRegion does not belong to any address space. So
> > memory_regio
On Wed, Oct 30, 2024, 5:31 PM Paolo Bonzini wrote:
> On 10/30/24 09:43, Alexander Graf wrote:
> >> Hi,
> >>
> >> sorry about the delay -- the patches failed CI and I didn't have much
> >> time to investigate until now.
> >>
> >> The issues are basically:
> >>
> >> 1) some rST syntax errors
> >>
>
On 10/29/24 19:43, Paolo Savini wrote:
This patch optimizes the emulation of unit-stride load/store RVV instructions
when the data being loaded/stored per iteration amounts to 16 bytes or more.
The optimization consists of calling __builtin_memcpy on chunks of data of 16
bytes between the memory
On Sun, 20 Oct 2024 at 05:17, William Hooper wrote:
>
> On Sat, Aug 17, 2024 at 11:33 PM William Hooper wrote:
> > At least on macOS 12.7.2, vmnet doesn't pad Ethernet frames, such as the
> > host's ARP replies, to the minimum size (60 bytes before the frame check
> > sequence) defined in IEEE St
On Wed, Oct 30, 2024, 9:08 a.m. Daniel P. Berrangé
wrote:
> On Wed, Oct 30, 2024 at 09:01:03AM -0400, Peter Xu wrote:
> > On Wed, Oct 30, 2024 at 10:33:23AM +, Daniel P. Berrangé wrote:
> > > On Tue, Oct 29, 2024 at 05:16:05PM -0400, Peter Xu wrote:
> > > > X86 IOMMUs cannot be created more t
On Wed, Oct 30, 2024 at 09:21:36PM +0800, Zhao Liu wrote:
> > > > Introduce avx10-version property so that avx10 version can be controlled
> > > > by user and cpu model. Per spec, avx10 version can never be 0, the
> > > > default
> > > > value of avx10-version is set to 0 to determine whether it i
Hi Daniel,
Let's try to push it before EOY.
I'm planning to start working on it in the first half of November.
Does that work for you?
Thanks
вт, 29 окт. 2024 г. в 20:40, Daniel Henrique Barboza <
dbarb...@ventanamicro.com>:
> Hi Alexey,
>
>
> Do you have plans to post a new version of this ser
On Wed, Oct 30, 2024, 10:39 a.m. Avihai Horon wrote:
>
> On 28/10/2024 21:06, Peter Xu wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > On Mon, Oct 28, 2024 at 07:20:27PM +0200, Avihai Horon wrote:
> >> On 28/10/2024 18:58, Peter Xu wrote:
> >>> External email: Use
On 10/26/24 10:53, Philippe Mathieu-Daudé wrote:
Loongson fixed-point multiplies and divisions opcodes are
specific to 64-bit cores (Loongson-2 and Loongson-3 families).
Simplify by removing the 32-bit checks.
Reported-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mi
On 10/26/24 10:53, Philippe Mathieu-Daudé wrote:
Extract the decode_64bit_enabled() helper which detects
whether CPUs can run 64-bit instructions.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/translate.h | 2 ++
target/mips/tcg/translate.c | 7 ++-
2 files changed, 8 insert
On Wed, Oct 30, 2024 at 11:55:34PM +0800, Zhao Liu wrote:
> On Wed, Oct 30, 2024 at 10:05:51PM +0800, Tao Su wrote:
> > Date: Wed, 30 Oct 2024 22:05:51 +0800
> > From: Tao Su
> > Subject: Re: [PATCH 4/8] target/i386: add AVX10 feature and AVX10 version
> > property
> >
> > On Wed, Oct 30, 2024 a
On 31/10/24 01:04, Pierrick Bouvier wrote:
Fixes: 4a448b148ca ("plugins: add qemu_plugin_num_vcpus function")
Signed-off-by: Pierrick Bouvier
---
include/qemu/qemu-plugin.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qemu-plugin.h
index 622c
From: Deepak Gupta
zicfiss introduces a new state ssp ("shadow stack register") in cpu.
ssp is expressed as a new unprivileged csr (CSR_SSP=0x11) and holds
virtual address for shadow stack as programmed by software.
Shadow stack (for each mode) is enabled via bit3 in *envcfg CSRs.
Shadow stack c
On Wed, Oct 30, 2024 at 2:37 PM Anton Blanchard wrote:
>
> vcompress packs vl or less fields into vd, so the tail starts after the
> last packed field. This could be more clearly expressed in the ISA,
> but for now this thread helps to explain it:
>
> https://github.com/riscv/riscv-v-spec/issues/7
From: Tomasz Jeznach
The RISC-V IOMMU specification is now ratified as-per the RISC-V
international process. The latest frozen specifcation can be found at:
https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf
Add the foundation of the device emulation for RISC-V
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