[PATCH v6] hw/misc/aspeed_hace: Fix SG Accumulative hashing

From: Alejandro Zeise Make the Aspeed HACE module use the new qcrypto accumulative hashing functions when in scatter-gather accumulative mode. A hash context will maintain a "running-hash" as each scatter-gather chunk is received. Previously each scatter-gather "chunk" was cached so the hash cou

Re: [PATCH 2/4] target/riscv/kvm: clarify how 'riscv-aia' default works

On Tue, Sep 24, 2024 at 10:46 PM Daniel Henrique Barboza wrote: > > We do not have control in the default 'riscv-aia' default value. We can > try to set it to a specific value, in this case 'auto', but there's no > guarantee that the host will accept it. > > Couple with this we're always doing a '

Re: [PATCH 3/4] target/riscv/kvm: add kvm-aia bools props

On Tue, Sep 24, 2024 at 10:46 PM Daniel Henrique Barboza wrote: > > Boolean properties are preferrable in comparision to string properties > since they don't require a string parsing. > > Add three bools that represents the available kvm-aia mode: > riscv-aia-emul, riscv-aia-hwaccel, riscv-aia-aut

[PATCH v2 01/16] target/mips: Declare mips_env_is_bigendian() in 'internal.h'

In order to re-use cpu_is_bigendian(), declare it on "internal.h" after renaming it as mips_env_is_bigendian(). Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20241004162118.84570-6-phi...@linaro.org> --- target/mips/internal.h| 5 ++

[PATCH v2 06/16] target/mips: Factor mo_endian_rev() out of MXU code

Instead of swapping the reversed target endianness using MO_BSWAP, directly return the correct endianness. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h | 5 + target/mips/tcg/mxu_translate.c | 8 2 files changed, 9 insert

[PATCH v2 03/16] target/mips: Introduce mo_endian_env() helper

Introduce mo_endian_env() which returns the endian MemOp corresponding to the vCPU env. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- target/mips/internal.h | 5 + 1 file changed, 5 insertions(+) diff --git a/target/mips/internal.h b/target/mips

[PATCH v2 00/16] target/mips: Remove target-specific endianness knowledge

Since v1: - Addressed rth review comment (adding new patches) Get vCPU endianness from CP0::BE bit. Propagate endianness at the board level, using QOM property. Remove target-specific endianness knowledge from target/. Philippe Mathieu-Daudé (16): target/mips: Declare mips_env_is_bigendian() in

[PATCH v2 02/16] target/mips: Rename cpu_is_bigendian() -> disas_is_bigendian()

Methods using the 'cpu_' prefix usually take a (Arch)CPUState argument. Since this method takes a DisasContext argument, rename it as disas_is_bigendian(). Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h | 2 +- target/mips/tcg/

[PATCH v2 07/16] target/mips: Explode MO_TExx -> MO_TE | MO_xx

Extract the implicit MO_TE definition in order to replace it by runtime variable in the next commit. Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/mips); \ done manually remove superfluous

[PATCH v2 12/16] target/mips: Use gen_op_addr_addi() when possible

Replace tcg_gen_movi_tl() + gen_op_addr_add() by a single gen_op_addr_addi() call. gen_op_addr_addi() calls tcg_gen_addi_tl() which might optimize if the immediate is zero. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h | 1

[PATCH v2 14/16] target/mips: Expose MIPSCPU::is_big_endian property

Add the "big-endian" property and set the CP0C0_BE bit in CP0_Config0. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- target/mips/cpu.h | 3 +++ target/mips/cpu.c | 12 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/targ

[PATCH v2 15/16] hw/mips/cps: Set the vCPU 'cpu-big-endian' property

Have the CPS expose a 'cpu-big-endian' property so it can set it to the vCPUs it creates. Note, since the number of vCPUs created is dynamic, we can not use QOM aliases. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- include/hw/mips/cps.h | 1 + hw/mi

[PATCH v2 09/16] target/mips: Introduce mo_endian() helper

Introduce mo_endian() which returns the endian MemOp corresponding to the vCPU DisasContext. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- target/mips/tcg/translate.h | 5 + 1 file changed, 5 insertions(+) diff --git a/target/mips/tcg/translate.

[PATCH v2 08/16] target/mips: Rename unused sysemu argument of OP_LD_ATOMIC()

In commit 6d0cad12594 ("target/mips: Finish conversion to tcg_gen_qemu_{ld,st}_*") we renamed the argument of the user definition. Rename the system part for coherency. Since the argument is ignored, prefix with 'ignored_'. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.c |

Re: precreate phase

On Thu, Oct 10, 2024 at 11:19:15PM +0200, Paolo Bonzini wrote: > Moving migration_object_init() earlier sounds like a good idea anyway! I take the last sentence back of my other reply - I believe I underestimated the potential reviewers of the upcoming precreate patchset.. :) -- Peter Xu

[PATCH v2 10/16] target/mips: Replace MO_TE by mo_endian()

Replace compile-time MO_TE evaluation by runtime mo_endian() one, which expand target endianness from DisasContext. Mechanical change using: $ sed -i -e 's/MO_TE/mo_endian(ctx)/' \ $(git grep -l MO_TE target/mips) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by:

[PATCH v2 16/16] hw/mips: Have mips_cpu_create_with_clock() take an endianness argument

mips_cpu_create_with_clock() creates a vCPU. Pass it the vCPU endianness requested by argument. Update the board call sites. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- target/mips/cpu.h| 4 +++- hw/mips/fuloong2e.c | 2 +- hw/mips/jaz

[PATCH v2 05/16] target/mips: Convert mips16e decr_and_load/store() macros to functions

Functions are easier to rework than macros. Besides, there is no gain here in inlining these. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Reviewed-by: Richard Henderson --- target/mips/tcg/mips16e_translate.c.inc | 101 +--- 1 file

[PATCH v2 04/16] target/mips: Replace MO_TE by mo_endian_env() in get_pte()

Replace compile-time MO_TE evaluation by runtime mo_endian_env() one, which expand target endianness from vCPU env. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- target/mips/tcg/sysemu/tlb_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-

[PATCH v2 11/16] target/mips: Have gen_addiupc() expand $pc during translation

Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 4802a6a1d87..41f25c938de 100644 --- a/target/mips/t

Ping: [PATCH] accel/kvm: check for KVM_CAP_READONLY_MEM on VM

I haven't heard anything about this patch for a while. https://patchew.org/QEMU/20240903062953.3926498-1-erbse...@gmx.de/ From 5c1ad1ff44438402ec824a224ac4659c8044ec7e Mon Sep 17 00:00:00 2001 From: Tom Dohrmann Date: Tue, 3 Sep 2024 06:25:04 + Subject: [PATCH] accel/kvm: check for KVM_CAP_RE

Re: [PATCH v2 2/8] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior

On Wed, Sep 25, 2024 at 9:58 PM Clément Léger wrote: > > When the Ssdbltrp extension is enabled, SSTATUS.SDT field is cleared > when executing sret. When executing mret/mnret, SSTATUS.SDT is cleared > when returning to U, VS or VU and VSSTATUS.SDT is cleared when returning > to VU from HS. I don'

[PATCH v2 0/4] qemu-ga: Fix some potential issues find by coverity

v2: Split v1 up to separate commits for each logically independent change Dehan Meng (4): sscanf return values are checked to ensure correct parsing. Proper initialization of n to 0 for getline to function correctly. Avoiding freeing line prematurely. It's now only freed at the end of th

[PATCH v2 2/4] Proper initialization of n to 0 for getline to function correctly.

Signed-off-by: Dehan Meng --- qga/commands-linux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qga/commands-linux.c b/qga/commands-linux.c index 2c2b5f4ff2..b905f33a57 100644 --- a/qga/commands-linux.c +++ b/qga/commands-linux.c @@ -2126,7 +2126,7 @@ GuestNetworkRouteList

[PATCH v2 1/4] sscanf return values are checked to ensure correct parsing.

Signed-off-by: Dehan Meng --- qga/commands-linux.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qga/commands-linux.c b/qga/commands-linux.c index 51d5e3d927..2c2b5f4ff2 100644 --- a/qga/commands-linux.c +++ b/qga/commands-linux.c @@ -2103,7 +2103,9 @@ static char *hexToI

Re: [PATCH v2 4/8] target/riscv: Add Ssdbltrp ISA extension enable switch

On Wed, Sep 25, 2024 at 9:59 PM Clément Léger wrote: > > Add the switch to enable the Ssdbltrp ISA extension. > > Signed-off-by: Clément Léger > --- > target/riscv/cpu.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 65347ccd5a..4f52cf7

[PATCH v2 3/4] Avoiding freeing line prematurely. It's now only freed at the end of the function.

Signed-off-by: Dehan Meng --- qga/commands-linux.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/qga/commands-linux.c b/qga/commands-linux.c index b905f33a57..4f0e38be81 100644 --- a/qga/commands-linux.c +++ b/qga/commands-linux.c @@ -2137,8 +2137,7 @@ GuestNetworkRout

[PATCH v2 4/4] For correcting code style: Variable declarations moved to the beginning of blocks Followed the coding style of using snake_case for variable names. And merged redundant route and networ

Signed-off-by: Dehan Meng --- qga/commands-linux.c | 116 --- 1 file changed, 53 insertions(+), 63 deletions(-) diff --git a/qga/commands-linux.c b/qga/commands-linux.c index 4f0e38be81..c6cca630ef 100644 --- a/qga/commands-linux.c +++ b/qga/commands-linux

Re: [PATCH v2 3/8] target/riscv: Implement Ssdbltrp exception handling

On Wed, Sep 25, 2024 at 9:59 PM Clément Léger wrote: > > When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode > while SSTATUS.SDT isn't cleared, generate a double trap exception to > M-mode. > > Signed-off-by: Clément Léger > --- > target/riscv/cpu.c| 2 +- > target/r

Re: [PATCH v2 5/8] target/riscv: Add Smdbltrp CSRs handling

On Wed, Sep 25, 2024 at 10:02 PM Clément Léger wrote: > > Add `ext_smdbltrp`in RISCVCPUConfig and implement MSTATUS.MDT behavior. > > Signed-off-by: Clément Léger > --- > target/riscv/cpu_bits.h | 1 + > target/riscv/cpu_cfg.h | 1 + > target/riscv/csr.c | 15 +++ > 3 files c

Re: [PATCH v1 0/7] target/riscv: Support SXL32 on RV64 CPU

On Mon, Oct 7, 2024 at 1:35 PM LIU Zhiwei wrote: > > From: TANG Tiancheng > > We have implemented UXL32 on QEMU already. It enables us to run RV32 > applications on RV64 Linux on QEMU. Similarly, RISCV specification > doesn't limit the SXLEN to be the same with MXLEN. In this patch set, > we will

Re: [PATCH v1 7/7] target/riscv: Expose sxl32 configuration in RISC-V CPU

On Mon, Oct 7, 2024 at 2:19 PM LIU Zhiwei wrote: > > From: TANG Tiancheng > > Enable with "-cpu rv64,sxl32=on". > When sxl32 is enabled, RV64 can boot 32-bit Linux with > 64-bit Opensbi while requiring to make minor modifications > to the Linux kernel source code. > > How to patch linux: > https:

Re: [PATCH v1 1/7] target/riscv: Fix sstatus read and write

On Mon, Oct 7, 2024 at 1:35 PM LIU Zhiwei wrote: > > From: TANG Tiancheng > > Sstatus is SXLEN bits in length and always has the layout determined by > the SXL configuration, regardless of the current XLEN. > > Signed-off-by: TANG Tiancheng > Fixes: b550f89457 (target/riscv: Compute mstatus.sd o

Re: [PATCH v1 2/7] target/riscv: Fix satp read and write implicitly or explicitly.

On Mon, Oct 7, 2024 at 1:35 PM LIU Zhiwei wrote: > > From: TANG Tiancheng > > CSR satp is SXLEN bits in length and always has the $layout determined by > the SXL configuration, regardless of the current XLEN. > > Only process CSR satp, as we still don't have a riscv_cpu_vsxl API > currently. > >

Re: [PATCH v1 3/7] target/riscv: Read pte and satp based on SXL in PTW

On Mon, Oct 7, 2024 at 1:36 PM LIU Zhiwei wrote: > > From: TANG Tiancheng > > Satp and PTE are always SXLEN-bit. when SXLEN is 32, > read PTE as 4 bytes, and treat satp as SATP32. > > Signed-off-by: TANG Tiancheng Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu_helper.c | 4

Re: [PATCH v1 5/7] target/riscv: Enable 32-bit only registers for RV64 with sxl32

On Mon, Oct 7, 2024 at 1:52 PM LIU Zhiwei wrote: > > From: TANG Tiancheng > > Allow reading 32-bit only registers like timeh and stimecmph when > booting a 32-bit Linux kernel on RV64 when sxl32 is true. > > Signed-off-by: TANG Tiancheng > --- > target/riscv/csr.c | 4 ++-- > 1 file changed, 2

Re: [PATCH] target/i386: Add more features enumerated by CPUID.7.2.EDX

On Thu, Oct 10, 2024 at 03:17:16PM +0200, Paolo Bonzini wrote: > Date: Thu, 10 Oct 2024 15:17:16 +0200 > From: Paolo Bonzini > Subject: Re: [PATCH] target/i386: Add more features enumerated by > CPUID.7.2.EDX > > On 10/9/24 10:12, Chao Gao wrote: > > > > diff --git a/target/i386/cpu.c b/target/i

Re: [PATCH v2 1/1] x86: Add support save/load HWCR MSR

On Wed, Oct 09, 2024 at 05:51:09PM +0800, Gao Shiyuan wrote: > Date: Wed, 9 Oct 2024 17:51:09 +0800 > From: Gao Shiyuan > Subject: [PATCH v2 1/1] x86: Add support save/load HWCR MSR > X-Mailer: git-send-email 2.39.3 (Apple Git-146) > > KVM commit 191c8137a939 ("x86/kvm: Implement HWCR support") >

Re: [PATCH 1/4] target/riscv/kvm: set 'aia_mode' to default in error path

On Tue, Sep 24, 2024 at 10:46 PM Daniel Henrique Barboza wrote: > > When failing to set the selected AIA mode, 'aia_mode' is left untouched. > This means that 'aia_mode' will not reflect the actual AIA mode, > retrieved in 'default_aia_mode', > > This is benign for now, but it will impact QMP quer

Re: [PATCH v3 04/14] ppc/spapr: remove deprecated machine pseries-2.4

On 10/7/24 17:38, Harsh Prateek Bora wrote: Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.4 specific code with this patch for now. While at it, also remove SpaprMachineClass::dr_lmb_enabled which is now

Re: [PATCH v3 05/14] ppc/spapr: remove deprecated machine pseries-2.5

On 10/7/24 17:38, Harsh Prateek Bora wrote: Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.5 specific code with this patch for now. Also drop sPAPRMachineClass::use_ohci_by_default which is now useless.

Re: [PATCH v3 03/14] ppc/spapr: remove deprecated machine pseries-2.3

On 10/7/24 17:38, Harsh Prateek Bora wrote: Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.3 specific code with this patch for now. While at it, also remove the dynamic-reconfiguration option which was in

[PATCH v2 13/16] target/mips: Use tcg_constant_tl() instead of tcg_gen_movi_tl()

Directly use tcg_constant_tl() for constant integer, this save a call to tcg_gen_movi_tl(), often saving a temp register. Most of the places found using the following Coccinelle spatch script: @@ identifier tmp; constant val; @@ *TCGv tmp = tcg_temp_new(); ... *tcg_gen_

[PATCH] sched_attr: Do not define for glibc >= 2.41

glibc 2.41+ has added [1] definitions for sched_setattr and sched_getattr functions and struct sched_attr. Therefore, it needs to be checked for here as well before defining sched_attr Fixes builds with glibc/trunk [1] https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=21571ca0d70302909cf72

Re: [PATCH] net: Check if nc is NULL in qemu_get_vnet_hdr_len()

On Sat, Aug 17, 2024 at 04:00:43PM +0900, Akihiko Odaki wrote: > A netdev may not have a peer specified, resulting in NULL. We should > make it behave like /dev/null in such a case instead of letting it > cause segmentatin fault. segmentation > > Fixes: 4b52d63249a5 ("tap: Remove qemu_using_vnet

Re: [PATCH v3 14/14] ppc/spapr: remove deprecated machine pseries-3.0

On 10/7/24 17:38, Harsh Prateek Bora wrote: As per Qemu's deprecation policy [1], and the mailing list discussion that happened on [2], pseries-3.0 is more than 6 years old since release and therefore due for deletion as already deprecated for >3 years. [1] https://www.qemu.org/docs/master/about

Re: [PATCH v3 12/14] ppc/spapr: remove deprecated machine pseries-2.12-sxxm

On 10/7/24 17:38, Harsh Prateek Bora wrote: Commit 0cac0f1b964 marked pseries-2.12 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.12-sxxm specific code with this patch. Suggested-by: Cédric Le Goater Signed-off-by: Harsh Prateek Bora --- hw/ppc/spapr.c |

Re: [PATCH v3 13/14] ppc/spapr: remove deprecated machine pseries-2.12

On 10/7/24 17:38, Harsh Prateek Bora wrote: Commit 0cac0f1b964 marked pseries-2.12 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.12 specific code with this patch. While at it, also remove pre-3.0-migration hacks introduced for backward compatibility which ar

Re: [PULL 00/12] Migration 20241009 patches

On Wed, 9 Oct 2024 at 13:42, Peter Xu wrote: > > The following changes since commit 2af37e791906cfda42cb9604a16d218e56994bb1: > > Merge tag 'pull-request-2024-10-07' of https://gitlab.com/thuth/qemu into > staging (2024-10-07 12:55:02 +0100) > > are available in the Git repository at: > > htt

Re: [PATCH v5 00/16] hw/misc/aspeed_hace: Fix SG Accumulative Hash Calculations

On 10/10/24 13:28, Daniel P. Berrangé wrote: On Tue, Oct 08, 2024 at 09:57:07AM +0200, Cédric Le Goater wrote: Hello, This is a resping of Alejandro's series fixing SG Accumulative Hash Calculations. See [1] for more details. The goal of this patch series is to fix accumulative hashing support

Re: [PATCH V3] virtio/vhost-user: fix qemu abort when hotunplug vhost-user-net device

Stefano Garzarella 于2024年10月10日周四 16:20写道： > > On Thu, Oct 10, 2024 at 02:18:24PM GMT, yaozhenguo wrote: > >During the hot-unplugging of vhost-user-net type network cards, > >the vhost_user_cleanup function may add the same rcu node to > >the rcu linked list. > >The function call relationship in t

Re: [PATCH v3 19/20] target/arm: Implement TCGCPUOps.tlb_fill_align

On Wed, 9 Oct 2024 at 01:05, Richard Henderson wrote: > > Fill in the tlb_fill_align hook. Handle alignment not due to > memory type, since that's no longer handled by generic code. > Pass memop to get_phys_addr. > > Signed-off-by: Richard Henderson > --- > target/arm/internals.h | 6 ++--

Re: [PATCH] tests/unit: Add a assert for test_io_channel_unix_listen_cleanup

On Thu, Oct 10, 2024 at 10:34:55AM +0800, Kunwu wrote: > Calling bind without checking return value. Add a assert for it. > > Signed-off-by: Kunwu > --- > tests/unit/test-io-channel-socket.c | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) Reviewed-by: Daniel P. Berrangé and queu

Re: [RFC V2 PATCH 11/11] arm/virt: enable sleep support

Hi Peter, > On 8 Oct 2024, at 11:53, Peter Maydell wrote: > > On Fri, 27 Sept 2024 at 19:40, Annie Li wrote: >> >> From: Miguel Luis >> >> For reference: qmp_system_sleep relies on wakeup support delegated >> by qemu_wakeup_suspend_enabled() hence the need for calling >> qemu_register_wakeup

Re: [PATCH v5 05/16] crypto/hash-nettle: Implement new hash API

On Thu, Oct 10, 2024 at 11:49:22AM +0100, Daniel P. Berrangé wrote: > On Tue, Oct 08, 2024 at 09:57:12AM +0200, Cédric Le Goater wrote: > > From: Alejandro Zeise > > > > Implements the new hashing API in the nettle hash driver. > > Supports creating/destroying a context, updating the context > >

Re: [PATCH v5 05/16] crypto/hash-nettle: Implement new hash API

On 10/10/24 13:43, Daniel P. Berrangé wrote: On Thu, Oct 10, 2024 at 11:49:22AM +0100, Daniel P. Berrangé wrote: On Tue, Oct 08, 2024 at 09:57:12AM +0200, Cédric Le Goater wrote: From: Alejandro Zeise Implements the new hashing API in the nettle hash driver. Supports creating/destroying a con

Re: [PATCH] target/i386: Add more features enumerated by CPUID.7.2.EDX

On 10/9/24 10:12, Chao Gao wrote: diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 85ef7452c0..18ba958f46 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1148,8 +1148,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { [FEAT_7_2_EDX] = { .type = CPUID_FEAT

[PATCH v2] docs/system/cpu-hotplug: Update example's socket-id/core-id

The example of how to do vCPU hotplug and hot-unlpug in the cpu-hotplug documentation no longer works, because the way we allocate socket-id and core-id to CPUs by default has changed at some point. The output also no longer matches what current QEMU produces in some more cosmetic ways. Update th

Re: [PATCH RFC 02/10] target/riscv: Introduce helper functions for pmu hashtable lookup

On 10.10.2024 02:09, Atish Patra wrote: The pmu implementation requires hashtable lookup operation sprinkled through the file. Add a helper function that allows to consolidate the implementation and extend it in the future easily. Signed-off-by: Atish Patra --- target/riscv/pmu.c | 56

Re: [PATCH RFC 05/10] target/riscv: Rename the PMU events

On 10.10.2024 02:09, Atish Patra wrote: The current PMU events are defined by SBI PMU specification. As there is no standard event encoding scheme, Virt machine chooses to use the SBI PMU encoding. A platform may choose to implement a different event encoding scheme completely. Rename the ev

Re: [PATCH v2] chardev: introduce 'reconnect-ms' and deprecate 'reconnect'

On 10/10/24 11:32 AM, Marc-André Lureau wrote: Hi Vladimir On Mon, Sep 30, 2024 at 5:17 PM Vladimir Sementsov-Ogievskiy wrote: Hi Mark-Andre! Could you please take a look? We have collected acks for QAPI changes, could this be queued? While writing to 9.2 changelog, I realize

Re: [PATCH] target/i386: Add more features enumerated by CPUID.7.2.EDX

Queued, thanks. Paolo

Re: [PATCH RFC 06/10] target/riscv: Define PMU event related structures

On 10.10.2024 02:09, Atish Patra wrote: Signed-off-by: Atish Patra --- target/riscv/cpu.h | 25 + 1 file changed, 25 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2ac391a7cf74..53426710f73e 100644 --- a/target/riscv/cpu.h +++ b/target/ris

Re: [RFC v2 1/2] vhost-vdpa: Implement IOVA->GPA tree

On 10/9/2024 2:29 AM, Eugenio Perez Martin wrote: On Tue, Oct 8, 2024 at 10:30 PM Si-Wei Liu wrote: On 10/8/2024 8:40 AM, Jonah Palmer wrote: On 10/8/24 2:51 AM, Eugenio Perez Martin wrote: On Tue, Oct 8, 2024 at 2:14 AM Si-Wei Liu wrote: On 10/7/2024 6:51 AM, Eugenio Perez Martin w

Re: [PATCH v2] audio/pw: Report more accurate error when connecting to PipeWire fails

On 9/18/24 11:29, Marc-André Lureau wrote: > On Wed, Sep 18, 2024 at 12:17 PM Michal Privoznik wrote: >> >> According to its man page [1], pw_context_connect() sets errno on >> failure: >> >> Returns a Core on success or NULL with errno set on error. >> >> It may be handy to see errno when figur

Re: [PATCH] tests/tcg: Do not use inttypes.h in multiarch/system/memory.c

On 10/10/24 10:58, Ilya Leoshkevich wrote: make check-tcg fails on Fedora with the following error message: alpha-linux-gnu-gcc [...] qemu/tests/tcg/multiarch/system/memory.c -o memory [...] qemu/tests/tcg/multiarch/system/memory.c:17:10: fatal error: inttypes.h: No such file or dire

[PATCH v3] intel_iommu: Introduce property "x-stale-tm" to control Transient Mapping (TM) field

VT-d spec removed Transient Mapping (TM) field from second-level page-tables and treat the field as Reserved(0) since revision 3.2. Changing the field as reserved(0) will break backward compatibility, so introduce a property "x-stale-tm" to allow user to control the setting. Use hw_compat_9_1 to

Re: [PATCH] meson: drop --enable-avx* options

On Thu, Oct 10, 2024 at 11:13:22AM +0200, Paolo Bonzini wrote: > Just detect compiler support and always enable the optimizations if > it is avilable; warn if the user did request AVX2/AVX512 use via > -Dx86_version= but the intrinsics are not available. > > Suggested-by: Richard Henderson > Sign

[PATCH] meson: drop --enable-avx* options

Just detect compiler support and always enable the optimizations if it is avilable; warn if the user did request AVX2/AVX512 use via -Dx86_version= but the intrinsics are not available. Suggested-by: Richard Henderson Signed-off-by: Paolo Bonzini --- meson.build | 30 +

PING: [PATCH v2 0/5] linux-user/i386: Emulate orig_ax

On Thu, 2024-09-12 at 11:28 +0200, Ilya Leoshkevich wrote: > v1: > https://lore.kernel.org/qemu-devel/20240802095942.34565-1-...@linux.ibm.com/ > v1 -> v2: Move orig_ax declaration higher, simplify gdb_write_reg() >   for TARGET_LONG_BITS == 32 (Richard). > > Hi, > > Currently gdbstub is

[PATCH 1/4] gdbstub: Make gdb_get_char() static

It's user-only since commit a7e0f9bd2ace ("gdbstub: abstract target specific details from gdb_put_packet_binary"). Reviewed-by: Richard Henderson Signed-off-by: Ilya Leoshkevich --- gdbstub/internals.h | 2 -- gdbstub/user.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --g

[PATCH 0/4] Minor gdbstub cleanups

Hi, These four patches are from the [1] series, which will probably take a while. But IMHO they make sense on their own, so I'm sending them as a separate series. [1] https://lore.kernel.org/qemu-devel/20240923162208.90745-1-...@linux.ibm.com/ Best regards, Ilya Ilya Leoshkevich (4): gdbstub:

[PATCH 2/4] gdbstub: Move phy_memory_mode to GDBSystemState

Follow the convention that all the pieces of the global stub state must be inside a single struct. While at it, convert phy_memory_mode to bool. Reviewed-by: Richard Henderson Signed-off-by: Ilya Leoshkevich --- gdbstub/system.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-)

[PATCH 3/4] gdbstub: Move gdb_syscall_mode to GDBSyscallState

Follow the convention that all the pieces of the global stub state must be inside a single struct. Reviewed-by: Richard Henderson Signed-off-by: Ilya Leoshkevich --- gdbstub/syscalls.c | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/gdbstub/syscalls.c

Re: [PATCH v5 01/16] crypto: accumulative hashing API

On Tue, Oct 08, 2024 at 09:57:08AM +0200, Cédric Le Goater wrote: > From: Alejandro Zeise > > Changes the hash API to support accumulative hashing. > Hash objects are created with "qcrypto_hash_new", > updated with data with "qcrypto_hash_update", and > the hash obtained with "qcrypto_hash_finali

Re: [PATCH v5 02/16] crypto/hash-glib: Implement new hash API

On Tue, Oct 08, 2024 at 09:57:09AM +0200, Cédric Le Goater wrote: > From: Alejandro Zeise > > Implements the new hashing API in the GLib hash driver. > Supports creating/destroying a context, updating the context > with input data and obtaining an output hash. > > Signed-off-by: Alejandro Zeise

Re: [PATCH v5 07/16] crypto/hash-afalg: Implement new hash API

On Tue, Oct 08, 2024 at 09:57:14AM +0200, Cédric Le Goater wrote: > From: Alejandro Zeise > > Updates the afalg hash driver to support the new accumulative > hashing changes as part of the patch series. > > Implements opening/closing of contexts, updating hash data > and finalizing the hash dige

Re: [PATCH for-9.2 0/7] docs/devel: Convert txt files to rST

Ping^3 for review (or I'm going to just apply these anyway). Paolo, I know we discussed this on IRC, but can I get an Acked-by tag from you for the license clarification in patch 6, please? thanks -- PMM On Thu, 19 Sept 2024 at 13:12, Peter Maydell wrote: > > Ping^2. > > In particular: Paolo, i

Re: [PULL v2 00/14] Rust initial PoC + meson changes for 2024-10-07

On Wed, 9 Oct 2024 at 10:47, Paolo Bonzini wrote: > > The following changes since commit b5ab62b3c0050612c7f9b0b4baeb44ebab42775a: > > Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging > (2024-10-04 19:28:37 +0100) > > are available in the Git repository at: > > https:/

Re: [PATCH -qemu] hw/cxl: Support get/set mctp response payload size

On Wed, Oct 09, 2024 at 06:41:57PM -0700, Davidlohr Bueso wrote: > Add Get/Set Response Message Limit commands. > > Signed-off-by: Davidlohr Bueso The commit log may include the cxl spec reference. Otherwise, Reviewed-by: Fan Ni > --- > hw/cxl/cxl-mailbox-utils.c | 68 ++

Re: [PATCH v2 1/8] target/riscv: Add Ssdbltrp CSRs handling

On Wed, Sep 25, 2024 at 10:02 PM Clément Léger wrote: > > Add ext_ssdbltrp in RISCVCPUConfig and implement MSTATUS.SDT, > {H|M}ENVCFG.DTE and modify the availability of MTVAL2 based on the > presence of the Ssdbltrp ISA extension. > > Signed-off-by: Clément Léger Reviewed-by: Alistair Francis

Re: [RFC v2 1/2] vhost-vdpa: Implement IOVA->GPA tree

On Thu, Oct 10, 2024 at 9:00 AM Si-Wei Liu wrote: > > > > On 10/9/2024 2:29 AM, Eugenio Perez Martin wrote: > > On Tue, Oct 8, 2024 at 10:30 PM Si-Wei Liu wrote: > >> > >> > >> On 10/8/2024 8:40 AM, Jonah Palmer wrote: > >>> > >>> On 10/8/24 2:51 AM, Eugenio Perez Martin wrote: > On Tue, Oct

[PATCH v3 6/7] tests/unit/test-char: add unit test for the `mux-be` multiplexer

The test is trivial: several backends, 1 `mux-be`, 1 frontend do the buffer write and read. Pipe is used for EAGAIN verification. Signed-off-by: Roman Penyaev Cc: "Marc-André Lureau" Cc: qemu-devel@nongnu.org --- tests/unit/test-char.c | 218 - 1 file cha

Re: [PATCH 1/1] chardev/char: fix qemu_chr_is_busy() check

Hi Roman On Thu, Oct 10, 2024 at 1:28 PM Roman Penyaev wrote: > `mux_cnt` struct member never goes negative or decrements, > so mux chardev can be !busy only when there are no > frontends attached. This patch fixes the always-true > check. > > Fixes: a4afa548fc6d ("char: move front end handlers

[PATCH v3 7/7] qemu-options.hx: describe multiplexing of several backend devices

This adds a few lines describing `mux-be` multiplexer configuration for multiplexing several backend devices with a single frontend device. Signed-off-by: Roman Penyaev Cc: "Marc-André Lureau" Cc: qemu-devel@nongnu.org --- qemu-options.hx | 78 -

[PATCH v3 1/7] chardev/char: rename `char-mux.c` to `char-mux-fe.c`

In the following patches backend multiplexer will be introduced and the implementation will be named as follows: `char-mux-be.c`. This patch renames the frontend multiplexer from `char-mux.c` to `char-mux-fe.c`. Signed-off-by: Roman Penyaev Cc: "Marc-André Lureau" Cc: qemu-devel@nongnu.org ---

[PATCH v3 4/7] chardev/char: introduce `mux-be-id=ID` option

Patch introduces `mux-be-id=ID` option for all chardev devices. This is necessary to attach chardev to `mux-be` for backend multiplexing. Actual implementation wimplementation will follow. Signed-off-by: Roman Penyaev Cc: "Marc-André Lureau" Cc: qemu-devel@nongnu.org --- chardev/char.c | 3 +++

[PATCH v3 2/7] chardev/char: move away mux suspend/resume calls

The suspend/resume open multiplexer calls are generic and will be used for frontend (current mux) and backend (will follow) implementations. Move them away from the `char-mux-fe.c` to more generic `char.c` file. Also for the sake of clarity these renames were made: s/suspend_mux_open/mux_suspend

[PATCH v3 5/7] chardev/char-mux: implement backend chardev multiplexing

This patch implements multiplexing capability of several backend devices, which opens up an opportunity to use a single frontend device on the guest, which can be manipulated from several backend devices. The idea of the change is trivial: keep list of backend devices (up to 4), init them on deman

[PATCH v3 3/7] chardev/char: rename frontend mux calls

This patch renames calls in the frontend mux implementation to reflect its frontend nature. Patch does the following: s/mux_chr/mux_fe_chr/g No functional changes are made. Signed-off-by: Roman Penyaev Cc: "Marc-André Lureau" Cc: qemu-devel@nongnu.org --- chardev/char-mux-fe.c | 57

Re: [PATCH 3/4] STM32: new GPIO device

On Wed, 9 Oct 2024 at 15:32, Román Cárdenas Rodríguez wrote: > > Looks like the stm32l4x5 is quite similar to my implementation. It didn’t > exist when I started with my implementation . I will take a closer look and > work on improving/extending the stm32l4x5 GPIO with my proposal. Is it OK if

Re: [PATCH v5 03/16] crypto/hash-gcrypt: Implement new hash API

On Tue, Oct 08, 2024 at 09:57:10AM +0200, Cédric Le Goater wrote: > From: Alejandro Zeise > > Implements the new hashing API in the gcrypt hash driver. > Supports creating/destroying a context, updating the context > with input data and obtaining an output hash. > > Signed-off-by: Alejandro Zeis

Re: [PATCH v3 05/20] accel/tcg: Add TCGCPUOps.tlb_fill_align

On Wed, 9 Oct 2024 at 01:05, Richard Henderson wrote: > > Add a new callback to handle softmmu paging. Return the page > details directly, instead of passing them indirectly to > tlb_set_page. Handle alignment simultaneously with paging so > that faults are handled with target-specific priority.

Re: [PATCH v5 04/16] crypto/hash-gnutls: Implement new hash API

On Tue, Oct 08, 2024 at 09:57:11AM +0200, Cédric Le Goater wrote: > From: Alejandro Zeise > > Implements the new hashing API in the gnutls hash driver. > Supports creating/destroying a context, updating the context > with input data and obtaining an output hash. > > Signed-off-by: Alejandro Zeis

[PATCH] tests/tcg: Do not use inttypes.h in multiarch/system/memory.c

make check-tcg fails on Fedora with the following error message: alpha-linux-gnu-gcc [...] qemu/tests/tcg/multiarch/system/memory.c -o memory [...] qemu/tests/tcg/multiarch/system/memory.c:17:10: fatal error: inttypes.h: No such file or directory 17 | #include |

[PATCH 1/1] chardev/char: fix qemu_chr_is_busy() check

`mux_cnt` struct member never goes negative or decrements, so mux chardev can be !busy only when there are no frontends attached. This patch fixes the always-true check. Fixes: a4afa548fc6d ("char: move front end handlers in CharBackend") Signed-off-by: Roman Penyaev Cc: "Marc-André Lureau" Cc:

[PATCH 4/4] gdbstub: Factor out gdb_try_stop()

Move checking and setting allow_stop_reply into a function. Reviewed-by: Richard Henderson Signed-off-by: Ilya Leoshkevich --- gdbstub/gdbstub.c | 15 +++ gdbstub/internals.h | 2 ++ gdbstub/system.c| 6 ++ gdbstub/user.c | 11 --- 4 files changed, 19 insert

Re: [PATCH v3 06/20] accel/tcg: Use the alignment test in tlb_fill_align

On Wed, 9 Oct 2024 at 01:05, Richard Henderson wrote: > > When we have a tlb miss, defer the alignment check to > the new tlb_fill_align hook. Move the existing alignment > check so that we only perform it with a tlb hit. > > Signed-off-by: Richard Henderson > @@ -1754,8 +1767,8 @@ static bool

Re: [PATCH v5 05/16] crypto/hash-nettle: Implement new hash API

On Tue, Oct 08, 2024 at 09:57:12AM +0200, Cédric Le Goater wrote: > From: Alejandro Zeise > > Implements the new hashing API in the nettle hash driver. > Supports creating/destroying a context, updating the context > with input data and obtaining an output hash. > > Signed-off-by: Alejandro Zeis

Re: [PATCH v5 06/16] util/iov: Introduce iov_send_recv_with_flags()

On Tue, Oct 08, 2024 at 09:57:13AM +0200, Cédric Le Goater wrote: > From: Alejandro Zeise > > In order to support a new update function, a flag needs to be passed > to the kernel via the socket send call (MSG_MORE) to notify it that > more data is to be expected to calculate the hash correctly. >

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