Re: [PATCH v1 5/7] target/riscv: Enable 32-bit only registers for RV64 with sxl32

[Alistair Francis]

On Mon, Oct 7, 2024 at 1:52 PM LIU Zhiwei <zhiwei_...@linux.alibaba.com> wrote:
>
> From: TANG Tiancheng <tangtiancheng....@alibaba-inc.com>
>
> Allow reading 32-bit only registers like timeh and stimecmph when
> booting a 32-bit Linux kernel on RV64 when sxl32 is true.
>
> Signed-off-by: TANG Tiancheng <tangtiancheng....@alibaba-inc.com>
> ---
>  target/riscv/csr.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 93a5cf87ed..c412ac8e31 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -161,7 +161,7 @@ skip_ext_pmu_check:
>
>  static RISCVException ctr32(CPURISCVState *env, int csrno)
>  {
> -    if (riscv_cpu_mxl(env) != MXL_RV32) {
> +    if (env->xl != MXL_RV32) {

Why not riscv_cpu_sxl()?

Alistair