On 9/4/24 07:27, LIU Zhiwei wrote:
@@ -2322,6 +2411,51 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
riscv_set_vec_config_vl(s, type);
tcg_out_opc_vi(s, OPC_VXOR_VI, a0, a1, -1, true);
break;
+case INDEX_op_cmpsel_vec:
+TCGArg a3, a4;
+
Reviewed-by: Mark Cave-Ayland
Signed-off-by: Bernhard Beschow
---
hw/char/riscv_htif.c | 1 -
hw/ppc/prep.c| 1 -
hw/riscv/sifive_e.c | 1 -
hw/riscv/sifive_u.c | 1 -
4 files changed, 4 deletions(-)
diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index 9bef60def1..54fd55c3e6
The includes where updated based on compile errors. Now, the inclusion of the
header roughly matches Kconfig dependencies:
# grep -r -e "select SERIAL_ISA"
hw/ppc/Kconfig:select SERIAL_ISA
hw/isa/Kconfig:select SERIAL_ISA
hw/sparc64/Kconfig:select SERIAL_ISA
hw/i386/Kconfig:
hw/char/serial currently contains the implementation of both TYPE_SERIAL and
TYPE_SERIAL_MM. According to serial_class_init(), TYPE_SERIAL is an internal
class while TYPE_SERIAL_MM is used by numerous machine types directly. Let's
move the latter into its own module which makes the dependencies mor
This series extracts TYPE_SERIAL_MM into its own module and introduces a
dedicated header for TYPE_SERIAL_ISA. The result is that no board directly
depends on CONFIG_SERIAL or includes hw/char/serial.h any more.
The first two patches are only paritally reviewed and would benefit from a few
more R-
On 9/4/24 16:36, Philippe Mathieu-Daudé wrote:
As per the deprecation notice in commit c7bbef4023:
The CRIS architecture was pulled from Linux in 4.17 and
the compiler is no longer packaged in any distro [...].
It is now unlikely QEMU is build on CRIS host.
Signed-off-by: Philippe Mathie
On Wed, 04 Sep 2024 14:01, Paolo Bonzini wrote:
On Wed, Aug 28, 2024 at 6:12 AM Manos Pitsidianakis
wrote:
Add rust/qemu-api, which exposes rust-bindgen generated FFI bindings and
provides some declaration macros for symbols visible to the rest of
QEMU.
The only comment I have is that I wou
Queued, thanks.
Paolo
On 9/4/24 07:19, Daniil Tatianin wrote:
The 'reconnect' option only allows to specify the time in seconds,
which is way too long for certain workflows.
We have a lightweight disk backend server, which takes about 20ms to
live update, but due to this limitation in QEMU, previously the guest
disk
dtb-kaslr-seed is a deprecated alias of dtb-randomness.
After ~two years it is time to remove it.
Signed-off-by: Paolo Bonzini
---
docs/about/deprecated.rst | 8
docs/about/removed-features.rst | 8
docs/system/arm/virt.rst| 3 ---
hw/arm/virt.c
It has been deprecated since 8.1; remove it and suggest using permission mapping
or virtiofsd.
Signed-off-by: Paolo Bonzini
---
MAINTAINERS|8 -
docs/about/deprecated.rst | 23 -
docs/about/removed-features.rst| 14 +
docs/conf.py
Hi all,
Hope I didn't miss anybody who is related to the topic. Please,
feel free to add!
<--- Background --->
As some of you know, there is an ongoing effort for nested-smmuv3
support in QEMU on ARM, working with the kernel IOMMUFD uAPIs:
[Nesting for vSTE]
https://lore.kernel.org/linux-iommu/0-
在 2024/7/29 上午11:57, Richard Henderson 写道:
On 7/29/24 11:39, Song Gao wrote:
/* Mapped address */
- return loongarch_map_address(env, physical, prot, address,
- access_type, mmu_idx);
+ ret = loongarch_map_address(env, physical, prot, address,
+
On 9/4/24 10:21, Thomas Huth wrote:
When configuring QEMU with "--without-default-devices", currently a lot
of the x86 qtests are failing since they silently assume that a certain
device or the i440fx pc machine is available. Add more checks for CONFIG
switches here to not run those tests in case
The 'reconnect' option only allows to specify the time in seconds,
which is way too long for certain workflows.
We have a lightweight disk backend server, which takes about 20ms to
live update, but due to this limitation in QEMU, previously the guest
disk controller would hang for one second becau
On Fri, Aug 16, 2024 at 01:09:23PM -0400, Steven Sistare wrote:
> On 8/16/2024 12:17 PM, Peter Xu wrote:
> > On Fri, Aug 16, 2024 at 05:00:32PM +0100, Daniel P. Berrangé wrote:
> > > On Fri, Aug 16, 2024 at 11:34:10AM -0400, Peter Xu wrote:
> > > > On Fri, Aug 16, 2024 at 04:16:50PM +0100, Daniel P
On Wed, Sep 04, 2024 at 04:58:14PM -0400, Steven Sistare wrote:
> On 8/21/2024 2:34 PM, Peter Xu wrote:
> > On Fri, Aug 16, 2024 at 01:09:23PM -0400, Steven Sistare wrote:
> > >
> > > libvirt starts qemu with the -sandbox spawn=deny option which blocks
> > > fork, exec,
> > > and change namespace
On Wed, Sep 04, 2024 at 06:23:50PM -0400, Peter Xu wrote:
> On Wed, Sep 04, 2024 at 04:58:14PM -0400, Steven Sistare wrote:
> > On 8/21/2024 2:34 PM, Peter Xu wrote:
> > > On Fri, Aug 16, 2024 at 01:09:23PM -0400, Steven Sistare wrote:
> > > > On 8/16/2024 12:17 PM, Peter Xu wrote:
> > > What I rea
On Wed, 4 Sept 2024 at 11:14, wrote:
>
> From: Helge Deller
>
> The following changes since commit fd1952d814da738ed107e05583b3e02ac11e88ff:
>
> Update version for v9.1.0 release (2024-09-03 09:18:26 -0700)
>
> are available in the Git repository at:
>
> https://github.com/hdeller/qemu-hppa.g
Hi,
On 29/7/24 03:39, Song Gao wrote:
Add a new LoongArch cpu type la664. The la664 has many new features,
such as new atomic instructions, hardware page table walk, etc.
We will implement them later.
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 48 +++
On 5/9/24 03:30, Richard Henderson wrote:
On 9/4/24 07:36, Philippe Mathieu-Daudé wrote:
--- a/include/disas/dis-asm.h
+++ b/include/disas/dis-asm.h
@@ -232,10 +232,6 @@ enum bfd_architecture
#define bfd_mach_avrxmega5 105
#define bfd_mach_avrxmega6 106
#define bfd_mach_avrxmega7 107
-
On 5/9/24 09:48, Paolo Bonzini wrote:
On 9/4/24 16:36, Philippe Mathieu-Daudé wrote:
As per the deprecation notice in commit c7bbef4023:
The CRIS architecture was pulled from Linux in 4.17 and
the compiler is no longer packaged in any distro [...].
It is now unlikely QEMU is build on CRI
zhenwei pi writes:
> QCryptodevBackendServiceType was introduced by
> bc304a6442e (cryptodev: Introduce server type in QAPI). However there
> is a lack of member description. Thanks to Markus for pointing out
> this.
>
> Signed-off-by: zhenwei pi
> ---
> qapi/cryptodev.json | 10 ++
> 1
Philippe Mathieu-Daudé writes:
> On 12/8/24 03:42, zhenwei pi wrote:
>> QCryptodevBackendServiceType was introduced by
>> bc304a6442e (cryptodev: Introduce server type in QAPI). However there
>> is a lack of member description. Thanks to Markus for pointing out
>> this.
>> Signed-off-by: zhenwei
On Aug 29 16:42, Changqi Lu wrote:
> Add reservation acquire, reservation register,
> reservation release and reservation report commands
> in the nvme device layer.
>
> By introducing these commands, this enables the nvme
> device to perform reservation-related tasks, including
> querying keys, q
On 05/09/2024 10.28, Paolo Bonzini wrote:
On 9/4/24 10:21, Thomas Huth wrote:
When configuring QEMU with "--without-default-devices", currently a lot
of the x86 qtests are failing since they silently assume that a certain
device or the i440fx pc machine is available. Add more checks for CONFIG
s
On 5/9/24 12:46, Markus Armbruster wrote:
Philippe Mathieu-Daudé writes:
On 12/8/24 03:42, zhenwei pi wrote:
QCryptodevBackendServiceType was introduced by
bc304a6442e (cryptodev: Introduce server type in QAPI). However there
is a lack of member description. Thanks to Markus for pointing out
The existing plugins already liberally use host pointer stuffing for
passing user data which will fail when doing 64 bit guests on 32 bit
hosts. We should discourage this by officially deprecating support and
adding another nail to the 32 bit host coffin.
Signed-off-by: Alex Bennée
---
docs/abou
Hi,
On 5/9/24 09:38, Bernhard Beschow wrote:
hw/char/serial currently contains the implementation of both TYPE_SERIAL and
TYPE_SERIAL_MM. According to serial_class_init(), TYPE_SERIAL is an internal
class while TYPE_SERIAL_MM is used by numerous machine types directly. Let's
move the latter into
From: Hendrik Wüthrich
Add CPUID enumeration for intel RDT monitoring and allocation, as well
as the flags used in the enumeration code.
Signed-off-by: Hendrik Wüthrich
---
hw/i386/rdt.c | 33 +++
include/hw/i386/rdt.h | 31 +
target/i386/cpu.c
From: Hendrik Wüthrich
Add RDT code to Associate CLOSID with RMID / set RMID for monitoring,
write COS, and read monitoring data. This patch does not add code for
the guest to interact through these things with MSRs, only the actual
ability for the RDT device to do them.
Signed-off-by: Hendrik
From: Hendrik Wüthrich
The aim of this patch series is to emulate Intel RDT features in order
to make testing of the linux Resctrl subsystem possible with Qemu.
A branch with the patches applied can be found at:
https://github.com/Gray-Colors/Intel_RDT_patches_applied
The changes made introduce
From: Hendrik Wüthrich
Add RDT features to feature word / TCG.
Signed-off-by: Hendrik Wüthrich
---
target/i386/cpu.c | 30 --
target/i386/cpu.h | 2 ++
2 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index a5c4
From: Hendrik Wüthrich
Add code to initialize all necessary state for the RDT device.
Signed-off-by: Hendrik Wüthrich
---
hw/i386/rdt.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c
index 934f7fbf75..c395ab91a9 100644
--- a/h
From: Hendrik Wüthrich
Change config to show RDT, add minimal code to the rdt.c module to make
sure things still compile.
Signed-off-by: Hendrik Wüthrich
---
hw/i386/Kconfig | 4 ++
hw/i386/meson.build | 1 +
hw/i386/rdt.c | 96 +++
in
From: Hendrik Wüthrich
Adjust minimum CPUID level if RDT monitoring or allocation features are
enabled to ensure that CPUID will return them.
Signed-off-by: Hendrik Wüthrich
---
target/i386/cpu.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/c
From: Hendrik Wüthrich
Implement rdmsr and wrmsr for the following MSRs:
* MSR_IA32_PQR_ASSOC
* MSR_IA32_QM_EVTSEL
* MSR_IA32_QM_CTR
* IA32_L3_QOS_Mask_n
* IA32_L2_QOS_Mask_n
* IA32_L2_QoS_Ext_BW_Thrtl_n
This allows for the guest to call RDT-internal functions to
associate an RMID with a CLOSID
From: Hendrik Wüthrich
Make sure that RDT monitoring and allocation features are included in
in full_cpuid_auto_level.
Signed-off-by: Hendrik Wüthrich
---
target/i386/cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 7c8bf707c2..649540e97
On 04/09/2024 19:16, Peter Xu wrote:
External email: Use caution opening links or attachments
On Wed, Sep 04, 2024 at 06:41:03PM +0300, Avihai Horon wrote:
On 04/09/2024 16:00, Peter Xu wrote:
External email: Use caution opening links or attachments
Hello, Avihai,
Reviving this thread ju
On Thu, 5 Sept 2024 at 12:13, Alex Bennée wrote:
>
> The existing plugins already liberally use host pointer stuffing for
> passing user data which will fail when doing 64 bit guests on 32 bit
> hosts. We should discourage this by officially deprecating support and
> adding another nail to the 32
On 5/9/24 13:11, Alex Bennée wrote:
The existing plugins already liberally use host pointer stuffing for
passing user data which will fail when doing 64 bit guests on 32 bit
hosts. We should discourage this by officially deprecating support and
adding another nail to the 32 bit host coffin.
Sign
On 3/9/24 18:07, Peter Maydell wrote:
Remove the pxa2xx specific pcmcia device.
Signed-off-by: Peter Maydell
---
include/hw/arm/pxa.h | 8 --
hw/pcmcia/pxa2xx.c| 248 --
hw/pcmcia/meson.build | 1 -
3 files changed, 257 deletions(-)
delete
On 3/9/24 18:07, Peter Maydell wrote:
Remove the pxa2xx-specific GPIO device.
Signed-off-by: Peter Maydell
---
include/hw/arm/pxa.h | 5 -
hw/arm/pxa2xx_gpio.c | 365 ---
hw/arm/meson.build | 2 +-
3 files changed, 1 insertion(+), 371 deletions
On 3/9/24 18:07, Peter Maydell wrote:
Remove the 'n800' and 'n810' machine types, which modelled
Nokia internet tablets. These were deprecated in 9.0 and
so we can remove them for 9.2.
Signed-off-by: Peter Maydell
---
MAINTAINERS |3 -
docs/system/arm/nseries.
On 3/9/24 18:07, Peter Maydell wrote:
The 'mainstone' machine has been deprecated since 9.0, and
so we can remove it for the 9.2 release.
Signed-off-by: Peter Maydell
---
MAINTAINERS | 2 -
docs/system/arm/mainstone.rst | 25
docs/system/target-
On 3/9/24 18:07, Peter Maydell wrote:
The MAINSTONE_FPGA device was used only by the 'mainstone' machine
type, so we can remove it now.
Signed-off-by: Peter Maydell
---
MAINTAINERS | 1 -
hw/misc/mst_fpga.c | 269
hw/misc/meson.build |
On 3/9/24 18:07, Peter Maydell wrote:
The 'z2' machine was deprecated in 9.0, so we can remove it for
9.2.
Signed-off-by: Peter Maydell
---
MAINTAINERS | 1 -
configs/devices/arm-softmmu/default.mak | 1 -
hw/arm/z2.c | 355 ---
On Wed, 4 Sept 2024 at 13:49, Fabiano Rosas wrote:
>
> The following changes since commit e638d685ec2a0700fb9529cbd1b2823ac4120c53:
>
> Open 9.2 development tree (2024-09-03 09:18:43 -0700)
>
> are available in the Git repository at:
>
> https://gitlab.com/farosas/qemu.git tags/migration-20240
On Tue, 3 Sept 2024 at 18:15, Paolo Bonzini wrote:
>
> On Tue, Sep 3, 2024 at 7:04 PM Peter Maydell wrote:
> > The PXA display device doesn't pass anything through to the guest,
> > by the way -- it just draws the pixels in the guest framebuffer
> > in a different place in the UI window. As the F
On Thu, 5 Sep 2024, Bernhard Beschow wrote:
hw/char/serial currently contains the implementation of both TYPE_SERIAL and
TYPE_SERIAL_MM. According to serial_class_init(), TYPE_SERIAL is an internal
class while TYPE_SERIAL_MM is used by numerous machine types directly. Let's
move the latter into i
在 2024/9/5 下午6:32, Philippe Mathieu-Daudé 写道:
Hi,
On 29/7/24 03:39, Song Gao wrote:
Add a new LoongArch cpu type la664. The la664 has many new features,
such as new atomic instructions, hardware page table walk, etc.
We will implement them later.
Signed-off-by: Song Gao
---
target/loongar
Hi Nicolin,
Thanks for the write up and task progress status.
> -Original Message-
> From: Nicolin Chen
> Sent: Thursday, September 5, 2024 9:26 AM
> To: Eric Auger ; Shameerali Kolothum Thodi
> ; Mostafa Saleh
>
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Peter Maydell
> ; Jason
Pass the env pointer through to the gvec_bfmmla helper,
so we can use it to add support for FEAT_EBF16.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper.h | 4 ++--
target/arm/tcg/translate-a64.c | 2 +-
target/arm/tcg/translate-neon.c | 4 ++--
tar
The TYPE_XLNX_BBRAM device creates a register block with
register_init_block32() in its instance_init method; we must
therefore destroy it in our instance_finalize method to avoid a leak
in the QOM introspection "init-inspect-finalize" lifecycle:
Direct leak of 304 byte(s) in 1 object(s) allocated
Pass the env pointer through to the gvec_bfdot_idx helper,
so we can use it to add support for FEAT_EBF16.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper.h | 4 ++--
target/arm/tcg/translate-a64.c | 11 ++-
target/arm/tcg/translate-neon.c
Now that our SMMU model supports enabling both stages of translation
at once, we can enable this in the sbsa-ref board. Existing guest
code that only programs stage 1 and doesn't care about stage 2 should
continue to run with the same behaviour, but guests that do want to
do nested SMMU configurat
Now that our SMMU model supports enabling both stages of translation
at once, we can enable this in the virt board. This is no change in
behaviour for guests, because if they simply ignore stage 2 and never
configure it then it has no effect. For the usual backwards
compatibility reasons we enabl
The TYPE_XLNX_VERSAL_TRNG device creates s->prng with g_rand_new()
in its init method, but it frees it in its unrealize method. This
results in a leak in the QOM introspection "initialize-inspect-finalize"
lifecycle:
Direct leak of 2500 byte(s) in 1 object(s) allocated from:
#0 0x55ec89eae9d8
The TYPE_XLNX_VERSAL_EFUSE_CTRL device creates a register block with
register_init_block32() in its instance_init method; we must
therefore destroy it in our instance_finalize method to avoid a leak
in the QOM introspection "init-inspect-finalize" lifecycle:
Direct leak of 304 byte(s) in 1 object(
In sbsa_fdt_add_gic_node() we g_strdup_printf() two nodename
strings, but only free one.
Since the string is actually entirely constant and we don't
make any use of printf's format-string operations, we can
drop the g_strdup_printf() use entirely.
Signed-off-by: Peter Maydell
Reviewed-by: Philip
Now that we've implemented the required behaviour for FEAT_EBF16, we
can enable it for the "max" CPU type, list it in our documentation,
and delete a TODO comment about it being missing.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
docs/system/arm/emulation.rst | 1 +
target
From: Changbin Du
Print errors before exit. Do not exit silently.
Cc: Philippe Mathieu-Daudé
Signed-off-by: Changbin Du
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20240903133940.3447430-1-changbin...@huawei.com
Signed-off-by: Peter Maydell
---
hw/arm/boot.c | 2 ++
1 file changed, 2 in
The TYPE_XLNX_VERSAL_TRNG device creates a register block with
register_init_block32() in its instance_init method; we must
therefore destroy it in our instance_finalize method to avoid a leak
in the QOM introspection "init-inspect-finalize" lifecycle:
Direct leak of 304 byte(s) in 1 object(s) all
4 13:20:17 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20240905
for you to fetch changes up to 99ec7b440a1d6a6ef07450b68687d24d13a25fb5:
platform-bus: fix refcount leak (2024-09-05 13:1
From: Sebastian Huber
The system supports the Security Extensions (core and GIC). This change is
necessary to run tests which pass on the real hardware.
Signed-off-by: Sebastian Huber
Reviewed-by: Edgar E. Iglesias
Tested-by: Edgar E. Iglesias
Message-id: 20240828005019.57705-1-sebastian.hu.
Implement the FPCR.EBF=1 semantics for bfdotadd() operations:
* is_ebf() sets up fpst and fpst_odd
* bfdotadd_ebf() implements the fused paired-multiply-and-add
operation that we need
The paired-multiply-and-add is similar to f16_dotadd() and
we use the same trick here as in that function, bu
From: Cornelia Huck
Add 9.2 machine types for arm/i440fx/m68k/q35/s390x/spapr.
Signed-off-by: Cornelia Huck
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Eric Auger
Signed-off-by: Peter Maydell
Message-id: 20240816161350.3706332-2-peter.mayd...@linaro.org
Message-id: 20240816103723.2325982-1-
We use bfdotadd() in four callsites for various helper functions. Currently
this all assumes that we have the FPCR.EBF=0 semantics. For FPCR.EBF=1
we will need to:
* call a different routine to bfdotadd() because we need to do a
fused multiply-add rather than separate multiply and add steps
*
On Thu, 5 Sept 2024 at 12:13, Philippe Mathieu-Daudé wrote:
> Could we start recommend to also add SPDX tags for new files committed
> to the repository? They are clearer than mis-copy/pasted license with
> typos and can be parsed by tools.
This is probably worth a discussion in a separate thread
To implement the FEAT_EBF16 semantics, we are going to need
the CPUARMState env pointer in every helper function which calls
bfdotadd().
Pass the env pointer through from generated code to the sme_bfmopa
helper. (We'll add the code that uses it when we've adjusted
all the helpers to have access to
FEAT_EBF16 adds one new bit to the FPCR floating point control
register. Allow this bit to be read and written when the ID
registers indicate the presence of the feature.
Note that because this new bit is not in FPSCR_FPCR_MASK the bit is
not visible in the AArch32 FPSCR, and FPSCR writes do not
From: Philippe Mathieu-Daudé
If the file is not an ELF file, arm_setup_direct_kernel_boot()
falls back to try it as a uimage or an AArch64 Image file or as
last resort a bare raw binary. We can discard load_elf_hdr()
error and silently return.
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 2
From: Gao Shiyuan
memory_region_find() returns an MR which it is the caller's
responsibility to unref, but platform_bus_map_mmio() was
forgetting to do so, thus leaking the MR.
Signed-off-by: Gao Shiyuan
Message-id: 20240829131005.9196-1-gaoshiy...@baidu.com
Reviewed-by: Peter Maydell
[PMM: tw
The TYPE_XLNX_ZYNQMP_EFUSE device creates a register block with
register_init_block32() in its instance_init method; we must
therefore destroy it in our instance_finalize method to avoid a leak
in the QOM introspection "init-inspect-finalize" lifecycle:
Direct leak of 304 byte(s) in 1 object(s) al
In vfp.decode we have the names of the VFNMA and VFNMS instructions
the wrong way around. The architecture says that bit 6 is the 'op'
bit, which is 1 for VFNMA and 0 for VFNMS, but we label these two
lines of decode the other way around. This doesn't cause any
user-visible problem because in the
When we added support for nested (stage 1 + stage 2) translation
to the SMMU in commit 58377c363291d we forgot to update the
comment that documents the valid values of the "stage" property.
Add the new "nested" value to it.
Fixes: 58377c363291d ("hw/arm/smmuv3: Support and advertise nesting")
Sign
Since the TYPE_XNLX_VERSAL_CFU_FDRO device creates a FIFO in its
instance_init method, we must destroy the FIFO in instance_finalize
to avoid a memory leak for the QOM introspection
"instantiate-examine-finalize" cycle:
Direct leak of 8192 byte(s) in 1 object(s) allocated from:
#0 0x55ec89eae7
Pass the env pointer through to the gvec_bfdot helper,
so we can use it to add support for FEAT_EBF16.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper.h | 4 ++--
target/arm/tcg/translate-a64.c | 27 -
target/arm/tcg/transl
The main loop in rr_cpu_thread_fn() can never terminate, so the
code at the end of the function to clean up the RCU subsystem is
dead code. Replace it with g_assert_not_reached().
(This is different from the other cpu_thread_fn for e.g. MTTCG or
for the KVM accelerator -- those can exit, if the vC
Hi Maciej,
On 27/08/2024 20:54, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
This way both the start and end points of migrating a particular VFIO
device are known.
Add also a vfio_save_iterate_empty_hit trace event so it is
build fails on musl libc (alpine linux) with this error:
../util/cpuinfo-riscv.c: In function 'cpuinfo_init':
../util/cpuinfo-riscv.c:63:21: error: '__NR_riscv_hwprobe' undeclared (first
use in this function); did you mean 'riscv_hwprobe'?
63 | if (syscall(__NR_riscv_hwprobe, &pair, 1,
On Thu, 5 Sept 2024 at 14:19, Milan P. Stanić wrote:
>
> build fails on musl libc (alpine linux) with this error:
>
> ../util/cpuinfo-riscv.c: In function 'cpuinfo_init':
> ../util/cpuinfo-riscv.c:63:21: error: '__NR_riscv_hwprobe' undeclared (first
> use in this function); did you mean 'riscv_hw
On 27/08/2024 20:54, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
These SaveVMHandlers help device provide its own asynchronous
transmission of the remaining data at the end of a precopy phase.
In this use case the save_liv
This series allows to boot linux kernels and other efi binaries via
direct kernel load with secure boot enabled.
The series adds two new fw_cfg files: 'etc/boot/kernel' contains the
kernel without modifications (no setup header patching), and
'etc/boot/shim' contains shim.
The path to the shim bi
Add a new "etc/boot/kernel" fw_cfg file, containing the kernel without
the setup header patches. Intended use is booting in UEFI with secure
boot enabled, where the setup header patching breaks secure boot
verification.
Needs OVMF changes too to be actually useful.
Signed-off-by: Gerd Hoffmann
Load the complete kernel (including setup) into memory. Excluding the
setup is handled later when adding the FW_CFG_KERNEL_SIZE and
FW_CFG_KERNEL_DATA entries.
This is a preparation for the next patch which adds a new fw_cfg file
containing the complete, unpatched kernel. No functional change.
Signed-off-by: Gerd Hoffmann
---
system/vl.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/system/vl.c b/system/vl.c
index 01b8b8e77ad1..302ad81285b7 100644
--- a/system/vl.c
+++ b/system/vl.c
@@ -2426,15 +2426,15 @@ static void qemu_validate_options(const Q
If the binary loaded via -kernel is *not* a linux kernel (in which
case protocol == 0), do not patch the linux kernel header fields.
It's (a) pointless and (b) might break binaries by random patching
and (c) changes the binary hash which in turn breaks secure boot
verification.
Background: OVMF h
Add new -shim command line option, wire up for the x86 loader.
When specified load shim into the new "etc/boot/shim" fw_cfg file.
Needs OVMF changes too to be actually useful.
Signed-off-by: Gerd Hoffmann
---
include/hw/boards.h | 1 +
hw/core/machine.c| 20
hw/i386/x
On 27/08/2024 20:54, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
qemu_loadvm_load_state_buffer() and its load_state_buffer
SaveVMHandler allow providing device state buffer to explicitly
specified device via its idstr and i
Hi,
On Thu, 2024-09-05 at 14:45, Peter Maydell wrote:
> On Thu, 5 Sept 2024 at 14:19, Milan P. Stanić wrote:
> >
> > build fails on musl libc (alpine linux) with this error:
> >
> > ../util/cpuinfo-riscv.c: In function 'cpuinfo_init':
> > ../util/cpuinfo-riscv.c:63:21: error: '__NR_riscv_hwprobe'
Peter Maydell writes:
> On Wed, 4 Sept 2024 at 13:49, Fabiano Rosas wrote:
>>
>> The following changes since commit e638d685ec2a0700fb9529cbd1b2823ac4120c53:
>>
>> Open 9.2 development tree (2024-09-03 09:18:43 -0700)
>>
>> are available in the Git repository at:
>>
>> https://gitlab.com/far
On Thu, Sep 05, 2024 at 07:25:05AM +0200, Thomas Weißschuh wrote:
> On 2024-09-05 06:04:12+, Jason A. Donenfeld wrote:
> > On Thu, Sep 5, 2024 at 5:45 AM maobibo wrote:
> > >
> > > Jason,
> > >
> > > With the latest qemu 9.1 version, elf format booting is supported.
> >
> > Thanks, I just fig
On Thu, Sep 05, 2024 at 02:11:32PM +0800, maobibo wrote:
>
>
> On 2024/9/5 下午1:25, Thomas Weißschuh wrote:
> > On 2024-09-05 06:04:12+, Jason A. Donenfeld wrote:
> >> On Thu, Sep 5, 2024 at 5:45 AM maobibo wrote:
> >>>
> >>> Jason,
> >>>
> >>> With the latest qemu 9.1 version, elf format boo
On 2024-09-05 16:53:55+, Jason A. Donenfeld wrote:
> On Thu, Sep 05, 2024 at 07:25:05AM +0200, Thomas Weißschuh wrote:
> > On 2024-09-05 06:04:12+, Jason A. Donenfeld wrote:
> > > On Thu, Sep 5, 2024 at 5:45 AM maobibo wrote:
> > > >
> > > > Jason,
> > > >
> > > > With the latest qemu 9.1
build fails on musl libc (alpine linux) with this error:
../util/cpuinfo-riscv.c: In function 'cpuinfo_init':
../util/cpuinfo-riscv.c:63:21: error: '__NR_riscv_hwprobe' undeclared (first
use in this function); did you mean 'riscv_hwprobe'?
63 | if (syscall(__NR_riscv_hwprobe, &pair, 1,
On Thu, Sep 5, 2024 at 5:05 PM Thomas Weißschuh wrote:
>
> On 2024-09-05 16:53:55+, Jason A. Donenfeld wrote:
> > On Thu, Sep 05, 2024 at 07:25:05AM +0200, Thomas Weißschuh wrote:
> > > On 2024-09-05 06:04:12+, Jason A. Donenfeld wrote:
> > > > On Thu, Sep 5, 2024 at 5:45 AM maobibo wrote
On 27/08/2024 20:54, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
load_finish SaveVMHandler allows migration code to poll whether
a device-specific asynchronous device state loading operation had finished.
In order to avoid
On 2024-09-05 17:07:22+, Jason A. Donenfeld wrote:
> On Thu, Sep 5, 2024 at 5:05 PM Thomas Weißschuh wrote:
> >
> > On 2024-09-05 16:53:55+, Jason A. Donenfeld wrote:
> > > On Thu, Sep 05, 2024 at 07:25:05AM +0200, Thomas Weißschuh wrote:
> > > > On 2024-09-05 06:04:12+, Jason A. Donen
On Thu, Sep 05, 2024 at 02:41:09PM +0300, Avihai Horon wrote:
>
> On 04/09/2024 19:16, Peter Xu wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > On Wed, Sep 04, 2024 at 06:41:03PM +0300, Avihai Horon wrote:
> > > On 04/09/2024 16:00, Peter Xu wrote:
> > > > Externa
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