From: Sebastian Huber <sebastian.hu...@embedded-brains.de>
The system supports the Security Extensions (core and GIC). This change is
necessary to run tests which pass on the real hardware.
Signed-off-by: Sebastian Huber <sebastian.hu...@embedded-brains.de>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Message-id: 20240828005019.57705-1-sebastian.hu...@embedded-brains.de
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
hw/arm/xilinx_zynq.c | 8 --------
1 file changed, 8 deletions(-)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 3c56b9abe1c..37c234f5aba 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -219,14 +219,6 @@ static void zynq_init(MachineState *machine)
for (n = 0; n < smp_cpus; n++) {
Object *cpuobj = object_new(machine->cpu_type);
- /*
- * By default A9 CPUs have EL3 enabled. This board does not currently
- * support EL3 so the CPU EL3 property is disabled before realization.
- */
- if (object_property_find(cpuobj, "has_el3")) {
- object_property_set_bool(cpuobj, "has_el3", false, &error_fatal);
- }
-
object_property_set_int(cpuobj, "midr", ZYNQ_BOARD_MIDR,
&error_fatal);
object_property_set_int(cpuobj, "reset-cbar", MPCORE_PERIPHBASE,
--
2.34.1
