On 2023/8/7 23:13, Richard Henderson wrote:
On 8/7/23 02:45, Jiajie Chen wrote:
This commit adds loongarch32 mode to loongarch64-softmmu.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/loongarch/cpu.h b/target/loonga
On 8/7/23 02:45, Jiajie Chen wrote:
Add la132 as a loongarch32 cpu type and allow virt machine to be used
with la132 instead of la464.
Signed-off-by: Jiajie Chen
---
hw/loongarch/virt.c| 5 -
target/loongarch/cpu.c | 41 +
target/loongarch/cp
On 8/7/23 02:45, Jiajie Chen wrote:
GPRs and PC are 32-bit wide in loongarch32 mode.
Signed-off-by: Jiajie Chen
---
configs/targets/loongarch64-softmmu.mak | 2 +-
gdb-xml/loongarch-base32.xml| 45 +
target/loongarch/cpu.c | 10 +-
t
On Fri, 4 Aug 2023 at 18:41, Peter Maydell wrote:
>
> On Thu, 27 Jul 2023 at 08:31, Akihiko Odaki wrote:
> >
> > Some Arm systems such as Apple Silicon Macs have IPA size smaller than the
> > default used by KVM. Introduce our own default IPA size that fits on such a
> > system.
> >
> > When revi
On 07.08.23 13:48, Ilya Leoshkevich wrote:
PoP (Sequence of Storage References -> Instruction Fetching) says:
... if a store that is conceptually earlier is
made by the same CPU using the same effective
address as that by which the instruction is subse-
quently fetched, the u
On Fri, 21 Jul 2023 12:35:09 -0400
Gregory Price wrote:
> Create a new device to emulate the SK hynix Niagara MHSLD platform.
>
> This device has custom CCI commands that allow for applying isolation
> to each memory block between hosts. This enables an early form of
> dynamic capacity, whereby
On 8/7/23 02:44, Jiajie Chen wrote:
This patch series allow qemu-system-loongarch64 to emulate a LoongArch32
machine. A mode enum is added to CPUArchState to select LA32 or LA64 at
runtime. A new CPU model is added for loongarch32. Initial GDB support
is added.
Changes since v2:
- Fix typo in p
On 8/7/23 02:45, Jiajie Chen wrote:
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
zero in LoongArch32.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu-csr.h| 9 +
target/loongarch/tlb_helper.c | 17 -
2 files changed, 17 insertions(+),
On 2023/8/7 23:40, Richard Henderson wrote:
On 8/7/23 02:44, Jiajie Chen wrote:
This patch series allow qemu-system-loongarch64 to emulate a LoongArch32
machine. A mode enum is added to CPUArchState to select LA32 or LA64 at
runtime. A new CPU model is added for loongarch32. Initial GDB suppor
On 8/7/23 02:45, Jiajie Chen wrote:
LA32 uses a different encoding for CSR.DMW and a new direct mapping
mechanism.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu-csr.h| 7 +++
target/loongarch/tlb_helper.c | 31 ---
2 files changed, 31 insertions(+)
[ Adding Juan and Peter for their awareness ]
On 8/2/23 10:14, Avihai Horon wrote:
Changing the device state from STOP_COPY to STOP can take time as the
device may need to free resources and do other operations as part of the
transition. Currently, this is done in vfio_save_complete_precopy() an
On 8/7/23 08:43, Jiajie Chen wrote:
There are changes missing for the translator.
All of the doubleword (D) instructions must be rejected in LA32 mode.
I was trying to do this, but I failed to figure out how to read the current cpucfg when
translating instructions to TCP ops. This problem appli
This patchset replaces the remaining uses of target_ulong in the accel/
directory. Specifically, the address type of a few kvm/hvf functions
is widened to vaddr, and the address type of the cpu_[st|ld]*()
functions is changed to abi_ptr (which is re-typedef'd to vaddr in
system mode).
As a starti
Signed-off-by: Anton Johansson
Reviewed-by: Richard Henderson
---
accel/tcg/cputlb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 8e9dc51cd1..2f97ae2fda 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1108,7 +1108,
In system mode, abi_ptr is primarily used for representing addresses
when accessing guest memory with cpu_[st|ld]*(). Widening it from
target_ulong to vaddr reduces the target dependence of these functions
and is step towards building accel/ once for system mode.
Signed-off-by: Anton Johansson
Re
Widens the pc and saved_insn fields of hvf_sw_breakpoint from
target_ulong to vaddr. Other hvf_* functions accessing hvf_sw_breakpoint
are also widened to match.
Signed-off-by: Anton Johansson
Reviewed-by: Richard Henderson
---
include/sysemu/hvf.h | 6 +++---
accel/hvf/hvf-accel-ops.c | 4
Changes the signature of the target-defined functions for
inserting/removing kvm hw breakpoints. The address and length arguments
are now of vaddr type, which both matches the type used internally in
accel/kvm/kvm-all.c and makes the api target-agnostic.
Signed-off-by: Anton Johansson
---
includ
Widens the pc and saved_insn fields of kvm_sw_breakpoint from
target_ulong to vaddr. The pc argument of kvm_find_sw_breakpoint is also
widened to match.
Signed-off-by: Anton Johansson
Reviewed-by: Richard Henderson
---
include/sysemu/kvm.h | 6 +++---
accel/kvm/kvm-all.c | 3 +--
2 files chang
Changes the signature of the target-defined functions for
inserting/removing hvf hw breakpoints. The address and length arguments
are now of vaddr type, which both matches the type used internally in
accel/hvf/hvf-all.c and makes the api target-agnostic.
Signed-off-by: Anton Johansson
---
includ
Changes the address type of the guest memory read/write functions from
target_ulong to abi_ptr. (abi_ptr is currently typedef'd to target_ulong
but that will change in a following commit.) This will reduce the
coupling between accel/ and target/.
Note: Function pointers that point to cpu_[st|ld]*(
On 2023/8/7 23:56, Richard Henderson wrote:
On 8/7/23 08:43, Jiajie Chen wrote:
There are changes missing for the translator.
All of the doubleword (D) instructions must be rejected in LA32 mode.
I was trying to do this, but I failed to figure out how to read the
current cpucfg when translat
As we are now using vaddr for representing guest addresses, update the
static assert to check that vaddr fits in the run_on_cpu_data union.
Signed-off-by: Anton Johansson
Reviewed-by: Richard Henderson
---
accel/tcg/cputlb.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
tlb_addr is changed from target_ulong to uint64_t to match the type of
a CPUTLBEntry value, and the addressed is changed to vaddr.
Signed-off-by: Anton Johansson
Reviewed-by: Richard Henderson
---
include/exec/cpu-all.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/inc
On 8/7/23 01:26, Joel Stanley wrote:
On Sat, 5 Aug 2023 at 18:02, Richard Henderson
wrote:
Mirror the host_arch variable from meson.build, so that we
probe for the correct linux-user/include/host/ directory.
This broke all of the linux-user targets for me on a ppc64le host.
None show up when
On 8/7/23 02:22, Paolo Bonzini wrote:
container_hosts is matched against $cpu, so it must contain QEMU
canonical architecture names, not Debian architecture names.
Also do not set $container_hosts inside the loop, since it is
already set before.
Signed-off-by: Paolo Bonzini
---
configure | 3 +
On Mon, 7 Aug 2023 at 17:01, Richard Henderson
wrote:
>
> On 8/7/23 01:26, Joel Stanley wrote:
> > On Sat, 5 Aug 2023 at 18:02, Richard Henderson
> > wrote:
> >>
> >> Mirror the host_arch variable from meson.build, so that we
> >> probe for the correct linux-user/include/host/ directory.
> >
> >
07.08.2023 19:00, Richard Henderson пишет:
I'll figure out something else.
Paolo already sent a patchset, see "linux-user, configure: fix CPU
canonicalization"
r~
On 8/7/23 02:48, Paolo Bonzini wrote:
Paolo Bonzini (3):
linux-user: fix detection for x32
linux-user: cleanup unused linux-user/include/host directories
configure: unify case statements for CPU canonicalization
Reviewed-by: Richard Henderson
Thanks for cleaning this up.
r~
On Mon, 2023-08-07 at 17:31 +0200, David Hildenbrand wrote:
> On 07.08.23 13:48, Ilya Leoshkevich wrote:
> > PoP (Sequence of Storage References -> Instruction Fetching) says:
> >
> > ... if a store that is conceptually earlier is
> > made by the same CPU using the same effective
> >
On 07.08.23 18:13, Ilya Leoshkevich wrote:
On Mon, 2023-08-07 at 17:31 +0200, David Hildenbrand wrote:
On 07.08.23 13:48, Ilya Leoshkevich wrote:
PoP (Sequence of Storage References -> Instruction Fetching) says:
... if a store that is conceptually earlier is
made by the same CPU u
On Wed, 2 Aug 2023 at 22:08, Jean-Christophe Dubois
wrote:
>
> The SRC device is normaly used to start the secondary CPU.
"normally"
>
> When running Linux directly, Qemu is emulating a PSCI interface that UBOOT
"QEMU"
> is installing at boot time and therefore the fact that the SRC device is
On Wed, Aug 2, 2023 at 5:50 AM Rob Bradford wrote:
>
> These are WARL fields - zero out the bits for unavailable counters and
> special case the TM bit in mcountinhibit which is hardwired to zero.
> This patch achieves this by modifying the value written so that any use
> of the field will see the
Unlike most other instructions that contain an immediate element index,
VREP's one is 16-bit, and not 4-bit. The code uses only 8 bits, so
using, e.g., 0x101 does not lead to a specification exception.
Fix by checking all 16 bits.
Cc: qemu-sta...@nongnu.org
Fixes: 28d08731b1d8 ("s390x/tcg: Implem
Add a small test to prevent regressions.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target | 1 +
tests/tcg/s390x/vrep.c | 81 +
2 files changed, 82 insertions(+)
create mode 100644 tests/tcg/s390x/vrep.c
diff --git a/tests/tcg/s390x/
Ensure that the chosen values for mmap_next_start and
task_unmapped_base are within the guest address space.
Tested-by: Helge Deller
Reviewed-by: Akihiko Odaki
Signed-off-by: Richard Henderson
---
linux-user/user-mmap.h | 18 +-
linux-user/main.c | 28 +
On Wed, 2 Aug 2023 at 22:09, Jean-Christophe Dubois
wrote:
>
> * Add Addr and size definition for all i.MX6UL devices in i.MX6UL header file.
> * Use those newly defined named constants whenever possible.
> * Standardize the way we init a familly of unimplemented devices
> - SAI
> - PWM (add
Create a set of subroutines to collect a set of guest addresses,
all of which must be mappable on the host. Use this within the
renamed pgb_fixed subroutine to validate the user's choice of
guest_base specified by the -B command-line option.
Signed-off-by: Richard Henderson
---
linux-user/elflo
Copy each guest kernel's default value, then bound it
against reserved_va or the host address space.
Tested-by: Helge Deller
Reviewed-by: Helge Deller
Signed-off-by: Richard Henderson
---
linux-user/aarch64/target_mman.h | 3 +++
linux-user/alpha/target_mman.h | 3 +++
linux-user/a
Use this as extra protection for the guest mapping over
any qemu host mappings.
Tested-by: Helge Deller
Reviewed-by: Helge Deller
Reviewed-by: Akihiko Odaki
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/l
Provide default values that are as close as possible to the
values used by the guest's kernel.
Tested-by: Helge Deller
Reviewed-by: Helge Deller
Reviewed-by: Akihiko Odaki
Signed-off-by: Richard Henderson
---
linux-user/aarch64/target_mman.h | 10 ++
linux-user/alpha/target_mman.h
This is the second half of
https://patchew.org/QEMU/20230804220032.295411-1-richard.hender...@linaro.org/
which I held back because of regressions with s390x testing.
It turns out that patch 4, "Use MAP_FIXED_NOREPLACE for initial image mmap"
actually triggered EEXIST, which meant that probe_gue
Use pgb_addr_set to probe for all of the guest addresses,
not just the main executable. Handle the identity map
specially and separately from the search.
If /proc/self/maps is available, utilize the full power
of the interval tree search, rather than a linear search
through the address list.
If
Rely on target_mmap to handle guest vs host page size mismatch.
Tested-by: Helge Deller
Reviewed-by: Helge Deller
Reviewed-by: Akihiko Odaki
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 54 +++-
1 file changed, 23 insertions(+), 31 deleti
If p_filesz == 0, then vaddr_ef == vaddr. We can reuse the
code in zero_bss rather than incompletely duplicating it in
load_elf_image.
Tested-by: Helge Deller
Reviewed-by: Helge Deller
Reviewed-by: Akihiko Odaki
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 27 +++--
The proper logging for probe_guest_base is in the main function.
There is no need to duplicate that in the subroutines.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 19 ---
1 file changed, 19 deletions(-)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
in
The three sets of checks are identical, logically.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 50 +++-
1 file changed, 17 insertions(+), 33 deletions(-)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 400af4a4c0..484ab7131a
Remove TARGET_ELF_EXEC_PAGESIZE, and 3 other TARGET_ELF_PAGE* macros
based off of that. Rely on target_mmap to handle guest vs host page
size mismatch.
Tested-by: Helge Deller
Reviewed-by: Helge Deller
Reviewed-by: Akihiko Odaki
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 17
Follow the lead of the linux kernel in fs/binfmt_elf.c,
in which an ET_DYN executable which uses an interpreter
(usually a PIE executable) is loaded away from where the
interpreter itself will be loaded.
Tested-by: Helge Deller
Reviewed-by: Helge Deller
Reviewed-by: Akihiko Odaki
Signed-off-by:
We will want to be able to search the set of mappings.
For this patch, the two users iterate the tree in order.
Signed-off-by: Richard Henderson
---
include/qemu/selfmap.h | 20
linux-user/elfload.c | 14 +++--
linux-user/syscall.c | 15 +++---
util/selfmap.c | 114 ++
From: Helge Deller
While we attempt to load a ET_DYN executable far away from
TASK_UNMAPPED_BASE, we are not completely in control of the
address space layout. If the interpreter lands close to
the executable, leaving insufficient heap space, move brk.
Tested-by: Helge Deller
Signed-off-by: He
On Wed, 2 Aug 2023 at 22:09, Jean-Christophe Dubois
wrote:
>
> * Add Addr and size definition for all i.MX7 devices in i.MX7 header file.
> * Use those newly defined named constants whenever possible.
> * Standardize the way we init a familly of unimplemented devices
> - SAI
> - PWM
> - CAN
On Sun, Jul 23, 2023 at 7:35 PM Alistair Francis wrote:
>
> On Thu, Jul 20, 2023 at 12:35 PM Tomasz Jeznach wrote:
> >
> > Adding virt machine property 'iommu' to enable/disable IOMMU
> > support, with platform RISC-V IOMMU device implementation.
> >
> > Generate device tree entry for riscv-iommu
On 07.08.23 18:34, Ilya Leoshkevich wrote:
Unlike most other instructions that contain an immediate element index,
VREP's one is 16-bit, and not 4-bit. The code uses only 8 bits, so
using, e.g., 0x101 does not lead to a specification exception.
Fix by checking all 16 bits.
Cc: qemu-sta...@nongn
On Mon, 2023-08-07 at 19:00 +0200, David Hildenbrand wrote:
> On 07.08.23 18:34, Ilya Leoshkevich wrote:
> > Unlike most other instructions that contain an immediate element
> > index,
> > VREP's one is 16-bit, and not 4-bit. The code uses only 8 bits, so
> > using, e.g., 0x101 does not lead to a s
On 07.08.23 19:02, Ilya Leoshkevich wrote:
On Mon, 2023-08-07 at 19:00 +0200, David Hildenbrand wrote:
On 07.08.23 18:34, Ilya Leoshkevich wrote:
Unlike most other instructions that contain an immediate element
index,
VREP's one is 16-bit, and not 4-bit. The code uses only 8 bits, so
using, e.g
On Wed, 2 Aug 2023 at 18:02, Jean-Philippe Brucker
wrote:
>
> When FEAT_RME is implemented, these bits override the value of
> CNT[VP]_CTL_EL0.IMASK in Realm and Root state. Move the IRQ state update
> into a new gt_update_irq() function and test those bits every time we
> recompute the IRQ state.
On Mon, 2023-08-07 at 11:48 +0200, Paolo Bonzini wrote:
> Alpha and 31-bit s390 lack the assembly fragment to handle signals
> occurring at the same time as system calls, so they cannot run
> linux-user emulation anymore. Drop the host-signal.h files for
> them.
>
> Signed-off-by: Paolo Bonzini
On 04.08.23 22:28, Eric Blake wrote:
On Fri, Jun 16, 2023 at 09:48:18PM +0300, Vladimir Sementsov-Ogievskiy wrote:
On 08.06.23 16:56, Eric Blake wrote:
Although extended mode is not yet enabled, once we do turn it on, we
need to reply with extended headers to all messages. Update the low
level
On 07.08.23 19:02, Ilya Leoshkevich wrote:
..>> None that I know of, but I thought this was still nice to have, and at
the same time small enough to not cause any trouble.
Ilya, do you have an idea why your messages don't reach qemu-stable@?
I see e.g. David's replies to yuor messages in qemu
On 04.08.23 22:36, Eric Blake wrote:
On Tue, Jun 27, 2023 at 04:23:49PM +0300, Vladimir Sementsov-Ogievskiy wrote:
On 08.06.23 16:56, Eric Blake wrote:
The NBD spec states that if the client negotiates extended headers,
the server must avoid NBD_REPLY_TYPE_BLOCK_STATUS and instead use
NBD_REPLY
On 2023/8/7 23:50, Richard Henderson wrote:
On 8/7/23 02:45, Jiajie Chen wrote:
LA32 uses a different encoding for CSR.DMW and a new direct mapping
mechanism.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu-csr.h | 7 +++
target/loongarch/tlb_helper.c | 31
On Mon, Aug 7, 2023, 6:33 AM Niklas Cassel wrote:
> On Tue, Jul 25, 2023 at 03:00:56PM -0400, John Snow wrote:
> > On Tue, Jul 25, 2023 at 9:04 AM Philippe Mathieu-Daudé
> > wrote:
> > >
> > > Hi Niklas, John, Paolo, Kevin,
> > >
> > > On 19/7/23 12:47, Niklas Cassel wrote:
> > >
> > > >> Niklas
On 8/7/23 09:37, Richard Henderson wrote:
We will want to be able to search the set of mappings.
For this patch, the two users iterate the tree in order.
Signed-off-by: Richard Henderson
---
include/qemu/selfmap.h | 20
linux-user/elfload.c | 14 +++--
linux-user/syscall.c |
On 8/7/23 06:56, Ilya Leoshkevich wrote:
One of notdirty_write()'s responsibilities is detecting self-modifying
code. Some functions pass the full size of a write to it, some pass 1.
When a write to a code section begins before a TB start, but then
overlaps the TB, the paths that pass 1 don't flu
On 8/7/23 07:15, Peter Maydell wrote:
arm_hcr_el2_eff_secstate() takes a bool secure, which it uses to
determine whether EL2 is enabled in the current security state.
With the advent of FEAT_RME this is no longer sufficient, because
EL2 can be enabled for Secure state but not for Root, and both
o
On 8/7/23 07:15, Peter Maydell wrote:
Pass an ARMSecuritySpace instead of a bool secure to
arm_is_el2_enabled_secstate(). This doesn't change behaviour.
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 13 -
target/arm/helper.c | 2 +-
2 files changed, 9 insertions(+), 6 d
On 8/7/23 07:28, Helge Deller wrote:
The tcg uses tgen_arithi(ARITH_AND) during fast CPU TLB lookups,
which e.g. translates to:
0x7ff5b011556a: 48 81 e6 00 f0 ff ff andq $0xf000, %rsi
In case the upper 48 bits are all set, the shorter sequence to operate
on the lower 16 bit
Currently, if a file does not exist yet, file_ram_open() will create new
empty file and open it writable. However, it even does that when
readonly=true was specified. So instead of opening the file read-only,
we'll open it writable, implying that later fallocate() or ftruncate()
could succeed.
Spe
From: Thiner Logoer
Users may specify
* "-mem-path" or
* "-object memory-backend-file,share=off,readonly=off"
and expect such COW (MAP_PRIVATE) mappings to work, even if the user
does not have write permissions to open the file.
For now, we would always fail in that case, always requiring file w
Patch #1 is the result of the discussion of:
"[PATCH v2] softmmu/physmem: try opening file readonly before failure
in file_ram_open" [1]
Instead of handling it inside file_ram_open(), handle it in the caller
and only fallback to readonly in a MAP_PRIVATE mapping.
Patch #2 refuses to crea
open() does not fail on directories when opening them readonly (O_RDONLY).
Currently, we succeed opening such directories and fail later during
mmap(), resulting in a misleading error message.
$ ./qemu-system-x86_64 \
-object memory-backend-file,id=ram0,mem-path=tmp,readonly=true,size=1g
qem
On Tue, Jun 27, 2023 at 05:22:09PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> On 08.06.23 16:56, Eric Blake wrote:
> > Update the client code to be able to send an extended request, and
> > parse an extended header from the server. Note that since we reject
> > any structured reply with a too-la
On 8/7/23 20:57, Richard Henderson wrote:
On 8/7/23 07:28, Helge Deller wrote:
The tcg uses tgen_arithi(ARITH_AND) during fast CPU TLB lookups,
which e.g. translates to:
0x7ff5b011556a: 48 81 e6 00 f0 ff ff andq $0xf000, %rsi
In case the upper 48 bits are all set, the shor
On 8/7/23 10:32, Jiajie Chen wrote:
uint8_t da = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA);
uint8_t pg = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG);
+ /* Truncate high 32 bits for LA32 */
+ if (env->mode == LA32) {
+ address = (uint32_t)address;
+ }
You need to do this
Yes, found the same in CI. I will send V2 tomorrow.
Paolo
Il lun 7 ago 2023, 19:18 Ilya Leoshkevich ha scritto:
> On Mon, 2023-08-07 at 11:48 +0200, Paolo Bonzini wrote:
> > Alpha and 31-bit s390 lack the assembly fragment to handle signals
> > occurring at the same time as system calls, so the
On Tue, Jun 27, 2023 at 10:42:20PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> On 08.06.23 16:56, Eric Blake wrote:
> > Allow a client to request a subset of negotiated meta contexts. For
> > example, a client may ask to use a single connection to learn about
> > both block status and dirty bitma
On 8/7/23 04:54, Klaus Jensen wrote:
From: Klaus Jensen
Hi,
The following changes since commit 9400601a689a128c25fa9c21e932562e0eeb7a26:
Merge tag 'pull-tcg-20230806-3' ofhttps://gitlab.com/rth7680/qemu into
staging (2023-08-06 16:47:48 -0700)
are available in the Git repository at:
On 8/7/23 08:06, Peter Maydell wrote:
The architecture requires (R_TYTWB) that an attempt to return from EL3
when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This
enforces that the CPU can't ever be executing below EL3 with the
NSE,NS bits indicating an invalid security state.)
W
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1802
Signed-off-by: Werner de Carne
---
chardev/char-win.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/chardev/char-win.c b/chardev/char-win.c
index d4fb44c4dc..92a7016105 100644
--- a/chardev/char-w
From: Marc-André Lureau
This can help to debug connection issues.
Related to:
https://bugzilla.redhat.com/show_bug.cgi?id=2196182
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
Message-Id: <20230510072531.3937189-1-marcandre.lur...@redhat.com>
---
chardev/char-socket.c | 12
From: Dongli Zhang
The kdump-zlib data pages are not dumped from aarch64 host when the
'pvtime' is involved, that is, when the block->target_end is not aligned to
page_size. In the below example, it is expected to dump two blocks.
(qemu) info mtree -f
... ...
090a-090a0fff
From: Marc-André Lureau
Acked-by: Dongwon Kim
Signed-off-by: Marc-André Lureau
Message-Id: <20230726173929.690601-2-marcandre.lur...@redhat.com>
---
include/hw/virtio/virtio-gpu.h | 1 +
hw/display/virtio-gpu-base.c | 2 +-
hw/display/virtio-gpu.c| 10 ++
3 files changed, 1
From: Marc-André Lureau
Calling OpenGL from different threads can have bad consequences if not
carefully reviewed. It's not generally supported. In my case, I was
debugging a crash in glDeleteTextures from OPENGL32.DLL, where I asked
qemu for gl=es, and thus ANGLE implementation was expected. lib
From: Zongmin Zhou
The buttons value use macros instead of direct numbers.
If request relative mode, have to add this for
guest vmmouse driver to judge this is a relative packet.
otherwise,vmmouse driver will not match
the condition 'status & VMMOUSE_RELATIVE_PACKET',
and can't report events on
From: Marc-André Lureau
The following changes since commit 9400601a689a128c25fa9c21e932562e0eeb7a26:
Merge tag 'pull-tcg-20230806-3' of https://gitlab.com/rth7680/qemu into
staging (2023-08-06 16:47:48 -0700)
are available in the Git repository at:
https://gitlab.com/marcandre.lureau/qemu
From: Dongwon Kim
Fixing a regression (black screen) caused by a commit 92b58156e7
("ui/gtk: set scanout-mode right before scheduling draw").
The commit 92b58156e7 was made with an assumption that the scanout
mode needs to be set only if the guest scanout is a dmabuf but there
are cases (e.g. vi
Hi Werner
On Tue, Aug 8, 2023 at 12:46 AM Werner de Carne wrote:
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1802
> Signed-off-by: Werner de Carne
This changes the polling callback to return 0 when I/O can't be
processed. in util/main-loop.c, it results in an early break of
os_
On 8/6/23 20:53, Jordan Niethe wrote:
+tmp = tcg_out_need_prefix_align(s) * 4;
tcg_out_need_prefix_align() returns a bool, optionally might prefer
tmp = tcg_out_need_prefix_align(s) ? 4 : 0;
I suppose. C type promotion rules make the multiplication just the same though.
That said,
Hi Marc-André,
when processing 2 or more characters, the guest machine mps2-an386 (uart
has a 1 character fifo) will only process one character. Without the
loop break, the guest gets no computing time and no further character
can be processed. The guest gets no more computing time and so
eve
I do apologize, but I do not understand your remark at all. Could I trouble
you to spell this out.
In:
+snprintf(tmp, sizeof(tmp), "%d", dec->imm >> 12 & 0xf);
0xf is a mask which recovers the 20 bit field used to represent the
immediate in the instruction encoding.
You se
Lots of virtio functions that are on a hot path in data transmission
are initializing indirect descriptor cache at the point of stack
allocation. It's a 112 byte structure that is getting zeroed out on
each call adding unnecessary overhead. It's going to be correctly
initialized later via special
On 8/7/23 15:01, Richard Bagley wrote:
I do apologize, but I do not understand your remark at all. Could I trouble you to spell
this out.
In:
+ snprintf(tmp, sizeof(tmp), "%d", dec->imm >> 12 & 0xf);
0xf is a mask which recovers the 20 bit field used to represent the imme
On 8/7/23 03:56, Michael Tokarev wrote:
The following changes since commit 9400601a689a128c25fa9c21e932562e0eeb7a26:
Merge tag 'pull-tcg-20230806-3' of https://gitlab.com/rth7680/qemu into
staging (2023-08-06 16:47:48 -0700)
are available in the Git repository at:
https://gitlab.com/mjt
On 8/7/23 13:47, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
The following changes since commit 9400601a689a128c25fa9c21e932562e0eeb7a26:
Merge tag 'pull-tcg-20230806-3' ofhttps://gitlab.com/rth7680/qemu into
staging (2023-08-06 16:47:48 -0700)
are available in the Git repo
Add missing entry for pif ("protection information format").
Protection information size can be 8 or 16 bytes, Update the pil entry
as per the NVM command set specification.
Signed-off-by: Ankit Kumar
---
docs/system/devices/nvme.rst | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(
This series fixes two bugs
1. CRC64 generation when metadata buffer is used.
2. Protection information disable check for Type 3 protection.
This series also updates the documentaion for pi (protection information),
and adds missing pif (protection information format) entry.
Ankit Kumar (3):
hw/
As per the NVM command set specification, the protection information
checks for Type 3 protection are disabled, only when both application
and reference tag have all bits set to 1.
Signed-off-by: Ankit Kumar
---
hw/nvme/dif.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
The nvme CRC64 generator expects the caller to pass inverted seed value.
Pass inverted crc value for metadata buffer.
Signed-off-by: Ankit Kumar
---
hw/nvme/dif.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/nvme/dif.c b/hw/nvme/dif.c
index 63c44c86ab..01b19c3373 10
This patch series allow qemu-system-loongarch64 to emulate a LoongArch32
machine. A new CPU model is added for loongarch32. Initial GDB support
is added.
At the same time, VA32(32-bit virtual address) support is introduced for
LoongArch64.
LA32 support is tested using a small supervisor program a
Add object class for future loongarch32 cpus. It is derived from the
loongarch64 object class.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu.c | 24
target/loongarch/cpu.h | 11 +++
2 files changed, 35 insertions(+)
diff --git a/target/loongarch/cpu.c b/ta
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