On 8/7/23 02:45, Jiajie Chen wrote:
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
zero in LoongArch32.

Signed-off-by: Jiajie Chen<c...@jia.je>
---
  target/loongarch/cpu-csr.h    |  9 +++++----
  target/loongarch/tlb_helper.c | 17 ++++++++++++-----
  2 files changed, 17 insertions(+), 9 deletions(-)

With the test for LA64 vs LA32 corrected,

Reviewed-by: Richard Henderson <richard.hender...@linaro.org>


r~

Reply via email to