On 2023/8/7 23:40, Richard Henderson wrote:
On 8/7/23 02:44, Jiajie Chen wrote:
This patch series allow qemu-system-loongarch64 to emulate a LoongArch32
machine. A mode enum is added to CPUArchState to select LA32 or LA64 at
runtime. A new CPU model is added for loongarch32. Initial GDB support
is added.
Changes since v2:
- Fix typo in previous commit
- Fix VPPN width in TLBEHI/TLBREHI
Changes since v1:
- No longer create a separate qemu-system-loongarch32 executable, but
allow user to run loongarch32 emulation using qemu-system-loongarch64
- Add loongarch32 cpu support for virt machine
Full changes:
Jiajie Chen (6):
target/loongarch: Add loongarch32 mode for loongarch64-softmmu
target/loongarch: Add loongarch32 cpu la132
target/loongarch: Add GDB support for loongarch32 mode
target/loongarch: Support LoongArch32 TLB entry
target/loongarch: Support LoongArch32 DMW
target/loongarch: Support LoongArch32 VPPN
There are changes missing for the translator.
All of the doubleword (D) instructions must be rejected in LA32 mode.
I was trying to do this, but I failed to figure out how to read the
current cpucfg when translating instructions to TCP ops. This problem
applies to the mode-specific behavior below: VA32L1, BL, JIRL, PCADD*,
PWCH etc.
Virtual addresses must be zero-extended from 32 bits in 32-bit
addressing mode.
It is done in the TLB change.
I see a note about VA32L1/VA32L2/VA32L3 in CSR.MISC enabling 32-bit
address mode for LA64. You would want to implement this with a
HW_FLAGS bit which indicates to the translator whether 32-bit
addressing is enabled in the current mode. This would always be true
for LA32, and from MISC for the current priv level for LA64.
There are changes to BL, JIRL and PCADD* to sign-extend in 32-bit
address mode.
What happened to the PWCH adjustment from v1?
r~
