[PATCH v2] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}

- modify check for mcounteren to work in all less-privilege mode - modify check for scounteren to work only when S mode is enabled - distinguish the exception type raised by check for scounteren between U and VU mode Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- v2: - Rebase on patc

RE: [PATCH V4 RESEND] net/colo.c: Fix the pointer issue reported by Coverity.

Ping Jason and Peter, any comments for this patch? Thanks Chen > -Original Message- > From: Zhang, Chen > Sent: Tuesday, August 9, 2022 4:49 PM > To: Jason Wang ; Peter Maydell > ; Li Zhijian ; qemu-dev > > Cc: Zhang, Chen > Subject: [PATCH V4 RESEND] net/colo.c: Fix the pointer i

Re: [PATCH v10 14/21] jobs: protect job.aio_context with BQL and job_mutex

Am 05/08/2022 um 11:12 schrieb Kevin Wolf: > Am 25.07.2022 um 09:38 hat Emanuele Giuseppe Esposito geschrieben: >> In order to make it thread safe, implement a "fake rwlock", >> where we allow reads under BQL *or* job_mutex held, but >> writes only under BQL *and* job_mutex. > > Oh, so the "or

Re: [PATCH for-7.1 3/4] target/loongarch: rename the TCG CPU "la464" to "qemu64-v1.00"

在 2022/8/17 上午10:36, chen huacai 写道: Hi, Richard and Xuerui, On Mon, Aug 15, 2022 at 4:54 AM Richard Henderson wrote: On 8/14/22 09:55, WANG Xuerui wrote: From: WANG Xuerui The only LoongArch CPU implemented is modeled after the Loongson 3A5000, but it is not the real thing, ... The 3A50

Re: [PATCH v2] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}

On Wed, Aug 17, 2022 at 03:36:35PM +0800, Weiwei Li wrote: > - modify check for mcounteren to work in all less-privilege mode > - modify check for scounteren to work only when S mode is enabled > - distinguish the exception type raised by check for scounteren between U > and VU mode > > Signed-off

Re: [PATCH v10 13/21] job: detect change of aiocontext within job coroutine

Am 16.08.2022 um 17:09 hat Emanuele Giuseppe Esposito geschrieben: > > > Am 05/08/2022 um 10:37 schrieb Kevin Wolf: > > Am 25.07.2022 um 09:38 hat Emanuele Giuseppe Esposito geschrieben: > >> From: Paolo Bonzini > >> > >> We want to make sure access of job->aio_context is always done > >> under

[PATCH for 7.2] minor fixups in block code

These 2 patches are just minor improvements to make code a bit better. Signed-off-by: Denis V. Lunev CC: Kevin Wolf CC: Hanna Reitz CC: Stefan Hajnoczi CC: Fam Zheng CC: Ronnie Sahlberg CC: Paolo Bonzini CC: Peter Lieven CC: Vladimir Sementsov-Ogievskiy

[PATCH 2/2] block: make serializing requests functions 'void'

Return codes of the following functions are never used in the code: * bdrv_wait_serialising_requests_locked * bdrv_wait_serialising_requests * bdrv_make_request_serialising Signed-off-by: Denis V. Lunev CC: Kevin Wolf CC: Hanna Reitz CC: Stefan Hajnoczi CC: Fam Zheng CC: Ronnie Sahlberg CC:

[PATCH v3] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}

- modify check for mcounteren to work in all less-privilege mode - modify check for scounteren to work only when S mode is enabled - distinguish the exception type raised by check for scounteren between U and VU mode Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- v3: - remove unneces

[PATCH] x86: disable rng seeding via setup_data

Causes regressions when doing direct kernel boots with OVMF. At this point in the release cycle the only sensible action is to just disable this for 7.1 and sort it properly in the 7.2 devel cycle. Cc: Jason A. Donenfeld Cc: Marcel Apfelbaum Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo

[PATCH 1/2] block: use bdrv_is_sg() helper instead of raw bs->sg reading

I believe that if the helper exists, it must be used always for reading of the value. It breaks expectations in the other case. Signed-off-by: Denis V. Lunev CC: Kevin Wolf CC: Hanna Reitz CC: Stefan Hajnoczi CC: Fam Zheng CC: Ronnie Sahlberg CC: Paolo Bonzini CC: Peter Lieven CC: Vladimir

Re: [PATCH v10 11/21] jobs: group together API calls under the same job lock

Am 16.08.2022 um 16:54 hat Emanuele Giuseppe Esposito geschrieben: > Am 04/08/2022 um 19:10 schrieb Kevin Wolf: > > Am 25.07.2022 um 09:38 hat Emanuele Giuseppe Esposito geschrieben: > >> Now that the API offers also _locked() functions, take advantage > >> of it and give also the caller control to

Re: [PATCH] x86: disable rng seeding via setup_data

On Wed, Aug 17, 2022 at 10:39:40AM +0200, Gerd Hoffmann wrote: > Causes regressions when doing direct kernel boots with OVMF. > > At this point in the release cycle the only sensible action > is to just disable this for 7.1 and sort it properly in the > 7.2 devel cycle. > > Cc: Jason A. Donenfeld

Re: [PATCH for-7.1 3/4] target/loongarch: rename the TCG CPU "la464" to "qemu64-v1.00"

On 2022/8/17 16:11, gaosong wrote: 在 2022/8/17 上午10:36, chen huacai 写道: Hi, Richard and Xuerui, On Mon, Aug 15, 2022 at 4:54 AM Richard Henderson wrote: On 8/14/22 09:55, WANG Xuerui wrote: From: WANG Xuerui The only LoongArch CPU implemented is modeled after the Loongson 3A5000, but it

[PATCH v2] block: add missed block_acct_setup with new block device init procedure

Commit 5f76a7aac156ca75680dad5df4a385fd0b58f6b1 is looking harmless from the first glance, but it has changed things a lot. 'libvirt' uses it to detect that it should follow new initialization way and this changes things considerably. With this procedure followed, blockdev_init() is not called anym

[PATCH 1/2] block: pass OnOffAuto instead of bool to block_acct_setup()

We would have one more place for block_acct_setup() calling, which should not corrupt original value. Signed-off-by: Denis V. Lunev CC: Peter Krempa CC: Markus Armbruster CC: John Snow CC: Kevin Wolf CC: Hanna Reitz CC: Vladimir Sementsov-Ogievskiy --- block/accounting.c | 24 +

Re: [PATCH v10 11/21] jobs: group together API calls under the same job lock

Am 17/08/2022 um 10:46 schrieb Kevin Wolf: @@ -475,13 +477,15 @@ void *block_job_create(const char *job_id, const BlockJobDriver *driver, job->ready_notifier.notify = block_job_event_ready; job->idle_notifier.notify = block_job_on_idle; -notifier_li

[PATCH 2/2] block: add missed block_acct_setup with new block device init procedure

Commit 5f76a7aac156ca75680dad5df4a385fd0b58f6b1 is looking harmless from the first glance, but it has changed things a lot. 'libvirt' uses it to detect that it should follow new initialization way and this changes things considerably. With this procedure followed, blockdev_init() is not called anym

Re: [PATCH] can: fix Xilinx ZynqMP CAN RX FIFO logic

On [2022 Aug 12] Fri 17:25:28, Anton Kochkov wrote: > Function "update_rx_fifo()" should operate on the RX FIFO > registers, not the TX FIFO ones. Hi Anton, Should we update the git commit message to say this is done for readability / keeping it consistent? (the defines have the same values) Oth

Re: [PATCH v10 11/21] jobs: group together API calls under the same job lock

Am 17.08.2022 um 11:35 hat Emanuele Giuseppe Esposito geschrieben: > > > Am 17/08/2022 um 10:46 schrieb Kevin Wolf: > @@ -475,13 +477,15 @@ void *block_job_create(const char *job_id, const > BlockJobDriver *driver, > job->ready_notifier.notify = block_job_event_ready; >

Re: [RFC] hw/block/m25p80: implement Octal SPI commands

Hi Anton, On [2022 Aug 13] Sat 12:00:03, Anton Kochkov wrote: > * Implement Octal SPI commands based on Micron MT35X series > * Fix Micron 0x2C-based ID handling (incompatible with Numonyx) > * Fix Micron configuration registers handling Would it be ok for you to split the patch up into 3 patches

Re: [PATCH 2/2] pci: Sanity check mask argument to pci_set_*_by_mask()

On Wed, Jul 27, 2022 at 11:26:15AM +0100, Peter Maydell wrote: > On Tue, 26 Jul 2022 at 23:30, Richard Henderson > wrote: > > > > On 7/26/22 09:32, Peter Maydell wrote: > > > Coverity complains that in functions like pci_set_word_by_mask() > > > we might end up shifting by more than 31 bits. This

Re: [PATCH] hw/intc: Handle software disabling of APIC correctly

On Fri, Jul 29, 2022 at 11:04:47PM +0530, Jay Khandkar wrote: > On Fri, Jul 29, 2022 at 06:09:01PM +0100, Peter Maydell wrote: > > On Tue, 12 Jul 2022 at 19:38, Jay Khandkar > > wrote: > > > > > > When the local APIC is in a software disabled state, all local interrupt > > > sources must be maske

Re: [PATCH v2 1/4] hw/virtio: incorporate backend features in features

On Thu, Jul 28, 2022 at 02:55:00PM +0100, Alex Bennée wrote: > There are some extra bits used over a vhost-user connection which are > hidden from the device itself. We need to set them here to ensure we > enable things like the protocol extensions. > > Currently net/vhost-user.c has it's own insc

Re: [PATCH v2 2/4] hw/virtio: gracefully handle unset vhost_dev vdev

On Thu, Jul 28, 2022 at 02:55:01PM +0100, Alex Bennée wrote: > I've noticed asserts firing because we query the status of vdev after > a vhost connection is closed down. Rather than faulting on the NULL > indirect just quietly reply false. > > Signed-off-by: Alex Bennée > Message-Id: <20220726192

[PATCH v2] virtio-pci: don't touch pci on virtio reset

virtio level reset should not affect pci express registers such as PM, error or link. Fixes: 27ce0f3afc ("hw/virtio: fix Power Management Control Register for PCI Express virtio devices") Fixes: d584f1b9ca ("hw/virtio: fix Link Control Register for PCI Express virtio devices") Fixes: c2cabb3422

Re: [PATCH for-7.2 14/21] accel/tcg: Hoist get_page_addr_code out of tb_lookup

On Tue, 2022-08-16 at 20:42 -0500, Richard Henderson wrote: > On 8/16/22 18:43, Ilya Leoshkevich wrote: > > On Fri, 2022-08-12 at 11:07 -0700, Richard Henderson wrote: > > > We will want to re-use the result of get_page_addr_code > > > beyond the scope of tb_lookup. > > > > > > Signed-off-by: Rich

Re: [PATCH v10 13/21] job: detect change of aiocontext within job coroutine

Am 17/08/2022 um 10:34 schrieb Kevin Wolf: > Am 16.08.2022 um 17:09 hat Emanuele Giuseppe Esposito geschrieben: >> >> >> Am 05/08/2022 um 10:37 schrieb Kevin Wolf: >>> Am 25.07.2022 um 09:38 hat Emanuele Giuseppe Esposito geschrieben: From: Paolo Bonzini We want to make sure acce

Re: [BUG] cxl can not create region

On Mon, 15 Aug 2022 15:55:15 -0700 Dan Williams wrote: > Jonathan Cameron wrote: > > On Fri, 12 Aug 2022 16:44:03 +0100 > > Jonathan Cameron wrote: > > > > > On Thu, 11 Aug 2022 18:08:57 +0100 > > > Jonathan Cameron via wrote: > > > > > > > On Tue, 9 Aug 2022 17:08:25 +0100 > > > > Jonath

Re: [PATCH 0/2] hw/cxl: Two CXL emulation fixes.

On Mon, 8 Aug 2022 13:20:49 +0100 Jonathan Cameron wrote: > Peter Maydell reported both these issues, having looked into Coverity > identified issues. The memory leak was straight forward, but testing the > second patch identified a bug in the Linux kernel. > > This bug has been fixed in the ser

Re: [PATCH v2 03/33] linux-user/x86_64: Allocate vsyscall page as a commpage

On Tue, 2022-08-16 at 15:33 -0500, Richard Henderson wrote: > We're about to start validating PAGE_EXEC, which means that we've > got to the vsyscall page executable.  We had been special casing > this entirely within translate. > > Signed-off-by: Richard Henderson > --- >  linux-user/elfload.c |

Re: [PATCH 2/2] pci: Sanity check mask argument to pci_set_*_by_mask()

On Wed, 17 Aug 2022 at 11:48, Michael S. Tsirkin wrote: > > On Wed, Jul 27, 2022 at 11:26:15AM +0100, Peter Maydell wrote: > > On Tue, 26 Jul 2022 at 23:30, Richard Henderson > > wrote: > > > > > > On 7/26/22 09:32, Peter Maydell wrote: > > > > Coverity complains that in functions like pci_set_wo

[PATCH] linux-user/s390x: Save/restore fpc when handling a signal

Linux kernel does this in fpregs_store() and fpregs_load(), so qemu-user should do this as well. Found by running valgrind's none/tests/s390x/test_sig. Signed-off-by: Ilya Leoshkevich --- linux-user/s390x/signal.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/linux-user/s390x/signal.c b

Re: [PATCH v10 18/21] job.c: enable job lock/unlock and remove Aiocontext locks

Am 05/08/2022 um 15:01 schrieb Kevin Wolf: > Am 25.07.2022 um 09:38 hat Emanuele Giuseppe Esposito geschrieben: >> Change the job_{lock/unlock} and macros to use job_mutex. >> >> Now that they are not nop anymore, remove the aiocontext >> to avoid deadlocks. > > Okay, so this is the big bad pat

Re: [PATCH v10 14/21] jobs: protect job.aio_context with BQL and job_mutex

Am 17/08/2022 um 10:04 schrieb Emanuele Giuseppe Esposito: >>> +/* protect against read in job_do_yield_locked */ >>> +JOB_LOCK_GUARD(); >>> +/* ensure the coroutine is quiescent while the AioContext is changed */ >>> +assert(job->pause_count > 0); >> job->pause_count only shows

Re: [PATCH for-7.2 14/21] accel/tcg: Hoist get_page_addr_code out of tb_lookup

On 8/17/22 06:08, Ilya Leoshkevich wrote: @@ -2243,6 +2250,13 @@ void page_set_flags(target_ulong start, target_ulong end, int flags) (flags & PAGE_WRITE) && p->first_tb) { tb_invalidate_phys_page(addr, 0); +} else { +TranslationBlock

Re: [PATCH for-7.1 3/4] target/loongarch: rename the TCG CPU "la464" to "qemu64-v1.00"

On 8/17/22 04:10, WANG Xuerui wrote: From my own experiences, different use cases care about different aspects of the CPU, and that IMO is an argument in favor of providing both (high-fidelity models named after actual product model names, and virtual models named after ISA levels). But before

Re: [PATCH for-7.2 14/21] accel/tcg: Hoist get_page_addr_code out of tb_lookup

On Wed, 2022-08-17 at 08:15 -0500, Richard Henderson wrote: > On 8/17/22 06:08, Ilya Leoshkevich wrote: > > @@ -2243,6 +2250,13 @@ void page_set_flags(target_ulong start, > > target_ulong end, int flags) > >   (flags & PAGE_WRITE) && > >   p->first_tb) { > >   tb

Re: [PATCH] linux-user/s390x: Save/restore fpc when handling a signal

On 8/17/22 07:39, Ilya Leoshkevich wrote: Linux kernel does this in fpregs_store() and fpregs_load(), so qemu-user should do this as well. Found by running valgrind's none/tests/s390x/test_sig. Signed-off-by: Ilya Leoshkevich Reviewed-by: Richard Henderson r~

Re: [PATCH for-7.2 14/21] accel/tcg: Hoist get_page_addr_code out of tb_lookup

On 8/17/22 08:27, Ilya Leoshkevich wrote: On Wed, 2022-08-17 at 08:15 -0500, Richard Henderson wrote: On 8/17/22 06:08, Ilya Leoshkevich wrote: @@ -2243,6 +2250,13 @@ void page_set_flags(target_ulong start, target_ulong end, int flags)   (flags & PAGE_WRITE) &&   p->fi

Re: [RFC PATCH 00/13] PowerPC interrupt rework

On 15/08/2022 17:02, Cédric Le Goater wrote: [ Adding Fabiano who reworked all exception models for 7.0 and Nick   who rewrote the Linux side sometime ago ] On 8/15/22 18:20, Matheus Ferst wrote: Currently, PowerPC interrupts are handled as follows: 1) The CPU_INTERRUPT_HARD bit of cs->interr

Re: [PATCH for-7.2 14/21] accel/tcg: Hoist get_page_addr_code out of tb_lookup

On 8/17/22 06:08, Ilya Leoshkevich wrote: +static void cpu_tb_jmp_cache_remove(TranslationBlock *tb) +{ +CPUState *cpu; +uint32_t h; + +/* remove the TB from the hash list */ +if (TARGET_TB_PCREL) { +/* Any TB may be at any virtual address */ +CPU_FOREACH(cpu) { +

Re: [RFC PATCH 03/13] target/ppc: move interrupt masking out of ppc_hw_interrupt

On 15/08/2022 17:09, Fabiano Rosas wrote: Matheus Ferst writes: Move the interrupt masking logic to a new method, ppc_pending_interrupt, and only handle the interrupt processing in ppc_hw_interrupt. Signed-off-by: Matheus Ferst --- target/ppc/excp_helper.c | 228 ---

Re: [RFC PATCH 04/13] target/ppc: prepare to split ppc_interrupt_pending by excp_model

On 15/08/2022 17:25, Fabiano Rosas wrote: Matheus Ferst writes: Rename the method to ppc_interrupt_pending_legacy and create a new ppc_interrupt_pending that will call the appropriate interrupt masking method based on env->excp_model. Signed-off-by: Matheus Ferst --- target/ppc/excp_helper

Re: [RFC PATCH 05/13] target/ppc: create an interrupt masking method for POWER9/POWER10

On 15/08/2022 19:39, Fabiano Rosas wrote: Matheus Ferst writes: Create an interrupt masking method for the POWER9 and POWER10 processors. The new method is based on cpu_has_work_POWER{9,10} and ppc_pending_interrupt_legacy. Signed-off-by: Matheus Ferst --- target/ppc/excp_helper.c | 160 ++

Re: [RFC PATCH 06/13] target/ppc: remove embedded interrupts from ppc_pending_interrupt_p9

On 15/08/2022 18:23, Fabiano Rosas wrote: Matheus Ferst writes: Critical Input, Watchdog Timer, and Fixed Interval Timer are only defined for embedded CPUs. The Programmable Interval Timer is 40x-only. Signed-off-by: Matheus Ferst --- target/ppc/excp_helper.c | 18 -- 1 fi

Re: [RFC PATCH v2 2/8] qapi: golang: Generate qapi's alternate types in Go

Hi, On Tue, Jul 05, 2022 at 08:45:06AM -0700, Andrea Bolognani wrote: > Sorry it took me a while to find the time to look into this! (1.5 month later.. what can I say!) :) > Overall this second iteration is a significant improvement over the > initial one. There are still a few things that I thi

Re: [PATCH] error handling: Use TFR() macro where applicable

Hi! Are there any updates? I have not received any comments since the last email. On Mon, Aug 8, 2022 at 9:03 PM Nikita Ivanov wrote: > And summing up the discussion about TEMP_FAILURE_RETRY() usage examples, > I've come up with a new patch for TFR() to TEMP_FAILURE_RETRY() > refactoring. I've d

Re: [PATCH for-7.2 14/21] accel/tcg: Hoist get_page_addr_code out of tb_lookup

On Wed, 2022-08-17 at 08:38 -0500, Richard Henderson wrote: > On 8/17/22 08:27, Ilya Leoshkevich wrote: > > On Wed, 2022-08-17 at 08:15 -0500, Richard Henderson wrote: > > > On 8/17/22 06:08, Ilya Leoshkevich wrote: > > > > @@ -2243,6 +2250,13 @@ void page_set_flags(target_ulong start, > > > > targ

Re: [PATCH] error handling: Use TFR() macro where applicable

On Wed, 17 Aug 2022 at 15:06, Nikita Ivanov wrote: > > Hi! Are there any updates? I have not received any comments since the last > email. Looking at the thread, I don't think we (yet) have consensus on the right thing to do here... thanks -- PMM

[PATCH v2] hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic

For consistency, function "update_rx_fifo()" should use the RX FIFO register names, not the TX FIFO ones even if they refer to the same memory region. Signed-off-by: Anton Kochkov Reviewed-by: Francisco Iglesias Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1123 --- hw/net/can/xlnx-zy

Re: [RFC PATCH v2 0/8] qapi: add generator for Golang interface

Hi, On Tue, Jul 05, 2022 at 08:46:34AM -0700, Andrea Bolognani wrote: > I've commented in detail to the single patches, just a couple of > additional points. > > On Fri, Jun 17, 2022 at 02:19:24PM +0200, Victor Toso wrote: > > * 7) Flat structs by removing embed types. Discussion with Andrea > >

Re: [PATCH v2] hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic

On Wed, 17 Aug 2022 at 15:24, Anton Kochkov wrote: > > For consistency, function "update_rx_fifo()" should use > the RX FIFO register names, not the TX FIFO ones even if "register field names" > they refer to the same memory region. "same bit positions in the register". (No need to spin a v3 j

[PATCH v2] meson: be strict for boolean options

While Meson buildsystem accepts the 'false' as a value for boolean options, it's not covered by the specification and in general invalid. Some alternative Meson implementations, like Muon, do not accept 'false' or 'true' as a valid value for the boolean options. See https://mesonbuild.com/Build-op

Re: [PATCH] .gitlab-ci.d/buildtest.yml: Increase the check-gprof-gcov job timeout

On 17/08/2022 05.46, Bin Meng wrote: Current project timeout is 1 hour, but the check-gprof-gcov job never completes within 1 hour. Increase the job timeout to 90 minutes. Signed-off-by: Bin Meng --- .gitlab-ci.d/buildtest.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitlab-ci.d

Re: [PATCH] error handling: Use TFR() macro where applicable

Well... What exactly is still under discussion? In my perspective, the main pitfalls have been resolved: 0. All possible places where TFR() macro could be applied are covered. 1. Macro has been renamed in order to be more transparent. The name has been chosen in comparison with a similar glibc ma

[PATCH 0/3] QEMU/CXL: A few more fixes for 7.1 related to LSA

The recent addition of CXL Region setup to the 6.0-rc1 Linux kernel has allowed us to test a few paths that weren't exercised fully until now. That threw up a mixture of bugs in QEMU emulation and the kernel (kernel fixes already posted). The first patch is down to a wrong assumption about RO Mem

[PATCH 1/3] hw/cxl: Add stub write function for RO MemoryRegionOps entries.

There is no checking on the availability of a write callback. Hence QEMU crashes if a write does occur to one of these regions. Discovered whilst chasing a Linux kernel bug that incorrectly wrote into one of these regions. Fixes: 6364adacdf ("hw/cxl/device: Implement the CAP array (8.2.8.1-2)") R

[PATCH 3/3] hw/cxl: Correctly handle variable sized mailbox input payloads.

A placeholder of ~0 is used to indicate variable payload size. Whilst the checks for output payload correctly took this into account, those for input payload did not. This results in failure of the Set LSA command. Fixes: 464e14ac43 ("hw/cxl/device: Implement basic mailbox (8.2.8.4)") Signed-off-

[PATCH 2/3] hw/cxl: Fix Get LSA input payload size which should be 8 bytes.

Get LSA needs 4 byte offset and 4 byte length arguments. CXL rev 2.0 Table 178. Fixes: 3ebe676a34 ("hw/cxl/device: Implement get/set Label Storage Area (LSA)") Signed-off-by: Jonathan Cameron --- hw/cxl/cxl-mailbox-utils.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/cx

Re: [RFC PATCH v2 7/8] qapi: golang: Add CommandResult type to Go

Hi, On Tue, Jul 05, 2022 at 05:49:22PM +0100, Daniel P. Berrangé wrote: > On Tue, Jul 05, 2022 at 08:46:21AM -0700, Andrea Bolognani wrote: > > On Fri, Jun 17, 2022 at 02:19:31PM +0200, Victor Toso wrote: > > > +type EmptyCommandReturn struct { > > > +CommandId string `json:"id,omitem

[PATCH v5 2/4] target/s390x: Make translator stop before the end of a page

Right now translator stops right *after* the end of a page, which breaks reporting of fault locations when the last instruction of a multi-insn translation block crosses a page boundary. Signed-off-by: Ilya Leoshkevich Reviewed-by: Richard Henderson --- target/s390x/tcg/translate.c | 15 +++

[PATCH v5 0/4] linux-user: Fix siginfo_t contents when jumping to non-readable pages

Hi, I noticed that when we get a SEGV due to jumping to non-readable memory, sometimes si_addr and program counter in siginfo_t are slightly off. I tracked this down to the assumption that translators stop before the end of a page, while in reality they may stop right after it. Patch 1 fixes an i

[PATCH v5 4/4] tests/tcg: Test siginfo_t contents when jumping to non-readable pages

Add x86_64 and s390x tests to prevent regressions. Signed-off-by: Ilya Leoshkevich --- tests/tcg/multiarch/noexec.h | 114 tests/tcg/s390x/Makefile.target | 1 + tests/tcg/s390x/noexec.c | 145 +++ tests/tcg/x86_64/Makefile.targ

[PATCH v5 3/4] target/i386: Make translator stop before the end of a page

Right now translator stops right *after* the end of a page, which breaks reporting of fault locations when the last instruction of a multi-insn translation block crosses a page boundary. An implementation, like the one arm and s390x have, would require an i386 length disassembler, which is burdens

[PATCH v2 03/31] ppc/ppc405: QOM'ify GPT

From: Cédric Le Goater The GPT controller is currently modeled as a SysBus device with a unique memory region, a couple of IRQs and a timer. Signed-off-by: Cédric Le Goater [balaton: ppc4xx_dcr_register changes, add finalize method] Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 22 +

[PATCH v2 00/31] QOMify PPC4xx devices and minor clean ups

Hello, This is based on gitlab.com/danielhb/qemu/tree/ppc-7.2 This series contains the rest of Cédric's OOM'ify patches modified according my review comments and some other clean ups I've noticed along the way. v2 now also includes the sdram changes after some clean up to simplify it. This shoul

[PATCH v5 1/4] linux-user: Clear tb_jmp_cache on mprotect()

Currently it's possible to execute pages that do not have PAGE_EXEC if there is an existing translation block. Fix by clearing tb_jmp_cache, which forces HELPER(lookup_tb_ptr)() to recheck permission bits the next time. Signed-off-by: Ilya Leoshkevich --- linux-user/mmap.c | 14 ++ 1

[PATCH v2 17/31] hw/intc/ppc-uic: Convert ppc-uic to a PPC4xx DCR device

Make ppc-uic a subclass of ppc4xx-dcr-device which will handle the cpu link and make it uniform with the other PPC4xx devices. Signed-off-by: BALATON Zoltan Reviewed-by: Cédric Le Goater --- hw/intc/ppc-uic.c | 26 ++ hw/ppc/ppc405_uc.c| 6 ++ hw/ppc

[PATCH v2 04/31] ppc/ppc405: QOM'ify OCM

From: Cédric Le Goater The OCM controller is currently modeled as a simple DCR device with a couple of memory regions. Signed-off-by: Cédric Le Goater [balaton: ppc4xx_dcr_register changes] Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h| 16 ++ hw/ppc/ppc405_uc.c | 77 +

[PATCH v2 11/31] ppc/ppc405: QOM'ify MAL

From: Cédric Le Goater The Memory Access Layer (MAL) controller is currently modeled as a DCR device with 4 IRQs. Also drop the ppc4xx_mal_init() helper and adapt the sam460ex machine. Signed-off-by: Cédric Le Goater [balaton: ppc4xx_dcr_register changes, add finalize method] Signed-off-by: BAL

[PATCH v2 02/31] ppc/ppc405: QOM'ify CPC

From: Cédric Le Goater The CPC controller is currently modeled as a DCR device. Now that all clock settings are handled at the CPC level, change the SoC "sys-clk" property to be an alias on the same property in the CPC model. Signed-off-by: Cédric Le Goater [balaton: ppc4xx_dcr_register change

[PATCH v2 01/31] ppc/ppc4xx: Introduce a DCR device model

From: Cédric Le Goater The Device Control Registers (DCR) of on-SoC devices are accessed by software through the use of the mtdcr and mfdcr instructions. These are converted in transactions on a side band bus, the DCR bus, which connects the on-SoC devices to the CPU. Ideally, we should model th

[PATCH v2 13/31] ppc4xx: Rename ppc405-plb to ppc4xx-plb

This device is shared between different 4xx socs. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 2 +- hw/ppc/ppc405_uc.c | 2 +- hw/ppc/ppc4xx_devs.c| 12 ++-- hw/ppc/sam460ex.c | 2 +- include/hw/ppc/ppc4xx.h | 6 +++--- 5 files changed, 12 insertions(+)

[PATCH v2 05/31] ppc/ppc405: QOM'ify GPIO

From: Cédric Le Goater The GPIO controller is currently modeled as a simple SysBus device with a unique memory region. Signed-off-by: Cédric Le Goater [balaton: Simplify sysbus device casts for readability] Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 21 +++ hw/ppc

[PATCH v2 06/31] ppc/ppc405: QOM'ify DMA

From: Cédric Le Goater The DMA controller is currently modeled as a DCR device with a couple of IRQs. Signed-off-by: Cédric Le Goater [balaton: ppc4xx_dcr_register changes] Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h| 19 ++ hw/ppc/ppc405_uc.c | 141

[PATCH v2 07/31] ppc/ppc405: QOM'ify EBC

From: Cédric Le Goater EBC is currently modeled as a DCR device. Also drop the ppc405_ebc_init() helper and adapt the sam460ex machine. Signed-off-by: Cédric Le Goater [balaton: ppc4xx_dcr_register changes] Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h| 17 - hw/ppc/ppc405

[PATCH v2 27/31] ppc4xx_sdram: Get rid of the init RAM hack

The do_init parameter of ppc4xx_sdram_init() is used to map memory regions that is normally done by the firmware by programming the SDRAM controller. This is needed when booting a kernel directly from -kernel without a firmware. Do this from board code accesing normal SDRAM controller registers the

[PATCH v2 15/31] ppc4xx: Rename ppc405-ebc to ppc4xx-ebc

This device is shared between different 4xx socs. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 2 +- hw/ppc/ppc405_uc.c | 2 +- hw/ppc/ppc4xx_devs.c| 12 ++-- hw/ppc/sam460ex.c | 2 +- include/hw/ppc/ppc4xx.h | 6 +++--- 5 files changed, 12 insertions(+)

[PATCH v2 08/31] ppc/ppc405: QOM'ify OPBA

From: Cédric Le Goater The OPB arbitrer is currently modeled as a simple SysBus device with a unique memory region. Signed-off-by: Cédric Le Goater [balaton: ppc4xx_dcr_register changes] Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 12 +++ hw/ppc/ppc405_uc.c | 49 +

[PATCH v2 14/31] ppc4xx: Move EBC model to ppc4xx_devs.c

The EBC is shared between 405 and 440 so move it to shared file. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 15 hw/ppc/ppc405_uc.c | 191 hw/ppc/ppc4xx_devs.c| 191 include/hw/ppc/pp

[PATCH v2 19/31] ppc/ppc405: QOM'ify FPGA

From: Cédric Le Goater Signed-off-by: Cédric Le Goater Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405_boards.c | 56 +- 1 file changed, 39 insertions(+), 17 deletions(-) diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 3677793adc..7af

[PATCH v2 30/31] ppc4xx_sdram: Move size check to ppc4xx_sdram_init()

Instead of checking if memory size is valid in board code move this check to ppc4xx_sdram_init() as this is a restriction imposed by the SDRAM controller. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 2 -- hw/ppc/ppc405_boards.c | 10 -- hw/ppc/ppc405_uc.c | 11 ++--

[PATCH v2 10/31] ppc/ppc405: QOM'ify PLB

From: Cédric Le Goater PLB is currently modeled as a simple DCR device. Also drop the ppc4xx_plb_init() helper and adapt the sam460ex machine. Signed-off-by: Cédric Le Goater [balaton: ppc4xx_dcr_register changes] Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h| 14 -- hw/ppc/pp

[PATCH v2 21/31] hw/ppc/Kconfig: Remove PPC405 dependency from sam460ex

Now that shared PPC4xx devices are separated from PPC405 ones we can drop this depencency. Signed-off-by: BALATON Zoltan Reviewed-by: Cédric Le Goater --- hw/ppc/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig index 400511c6b7..205f9f98d7 100644 --- a/

[PATCH v2 18/31] ppc/ppc405: Use an explicit I2C object

From: Cédric Le Goater Having an explicit I2C model object will help if one day we want to add I2C devices on the bus from the machine init routine. Signed-off-by: Cédric Le Goater [balaton: Symplify sysbus device casts for readibility] Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h|

[PATCH v2 09/31] ppc/ppc405: QOM'ify POB

From: Cédric Le Goater POB is currently modeled as a simple DCR device. Signed-off-by: Cédric Le Goater [balaton: ppc4xx_dcr_register changes] Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h| 12 ++ hw/ppc/ppc405_uc.c | 56 ++ 2 files

[PATCH v2 26/31] ppc4xx: Introduce Ppc4xxSdramBank struct

Instead of storing sdram bank parameters in unrelated arrays put them in a struct so it's clear they belong to the same bank and simplify the state struct using this bank type. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc440_uc.c | 49 +- hw/ppc/ppc4xx_devs.c

[PATCH v2 22/31] hw/ppc/Kconfig: Move imply before select

In pegasos2 section move imply before select to match other sections. Signed-off-by: BALATON Zoltan Reviewed-by: Cédric Le Goater --- hw/ppc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig index 205f9f98d7..3a4418a69e 100644 --- a/hw/p

[PATCH v2 25/31] ppc440_bamboo: Remove unnecessary memsets

In ppc4xx_sdram_init() the struct is allocated with g_new0() so no need to clear its elements. In the bamboo machine init memset can be replaced with array initialiser which is shorter. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc440_bamboo.c | 6 ++ hw/ppc/ppc4xx_devs.c | 8 ++-- 2 fi

[PATCH v2 12/31] ppc4xx: Move PLB model to ppc4xx_devs.c

The PLB is shared between 405 and 440 so move it to the shared file. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 11 - hw/ppc/ppc405_uc.c | 93 hw/ppc/ppc4xx_devs.c| 94 + include/hw/ppc

[PATCH v2 28/31] ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks()

Change ppc4xx_sdram_banks() to take one Ppc4xxSdramBank array instead of the separate arrays and adjust ppc4xx_sdram_init() and ppc440_sdram_init() accordingly as well as machines using these. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 4 +--- hw/ppc/ppc405_uc.c | 10 +

[PATCH v2 23/31] ppc/ppc4xx: Fix sdram trace events

From: Cédric Le Goater Signed-off-by: Cédric Le Goater Signed-off-by: BALATON Zoltan --- hw/ppc/ppc4xx_devs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 37e3b87c2e..27ebbb2ffc 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/

[PATCH v2 16/31] ppc/ppc405: Use an embedded PPCUIC model in SoC state

From: Cédric Le Goater Signed-off-by: Cédric Le Goater [balaton: Simplify sysbus device casts for readability] Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h| 3 ++- hw/ppc/ppc405_uc.c | 28 ++-- 2 files changed, 16 insertions(+), 15 deletions(-) diff --git a/h

[PATCH v2 20/31] ppc405: Move machine specific code to ppc405_boards.c

These are only used by the board code so move out from the shared SoC model and put it in the boards file. Signed-off-by: BALATON Zoltan Reviewed-by: Cédric Le Goater --- hw/ppc/ppc405.h| 38 - hw/ppc/ppc405_boards.c | 375 +++-- hw/ppc/ppc405_uc

[PATCH v2 31/31] ppc4xx_sdram: QOM'ify

Change the ppc4xx_sdram model to a QOM class derived from the PPC4xx-dcr-device and name it ppc4xx-sdram-ddr. This is mostly modelling the DDR SDRAM controller found in the 440EP (used on the bamboo board) but also backward compatible with the older DDR controllers on some 405 SoCs so we also use i

[PATCH 2/2] target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered

Starting with RVV1.0, the original vf[w]redsum_vs instruction was renamed to vf[w]redusum_vs. The distinction between ordered and unordered is also more consistent with other instructions, although there is no difference in implementation between the two for QEMU. Signed-off-by: Yang Liu --- tar

RE: AST2600 support in QEMU

Hi Dan, Responding on behalf of Shivi. >> "So what does the "PCIe RC support" means? the BMC will be the PCIe RC?" Yes, BMC will be the PCIe RC to control downstream PCIe devices (end-points). - Amit -Original Message- From: Dan Zhang Sent: 15 August 2022 11:18 To: Cédric Le Goater C

[PATCH v2 24/31] ppc4xx: Fix code style problems reported by checkpatch

Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405_uc.c | 5 +++-- hw/ppc/ppc440_bamboo.c | 27 ++-- hw/ppc/ppc440_uc.c | 3 ++- hw/ppc/ppc4xx_devs.c | 48 +++--- hw/ppc/ppc4xx_pci.c| 31 +-- 5 files chan

Re: [PATCH 00/22] QOMify PPC4xx devices and minor clean ups

On Tue, 16 Aug 2022, Cédric Le Goater wrote: On 8/13/22 17:34, BALATON Zoltan wrote: Hello, This is mased on gitlab.com/danielhb/qemu/tree/ppc-7.2 This series contains the rest of Cédric's patches modified according my review comments and some other small clean ups I've noticed along the way.

  1   2   >