Re: [PATCH 01/24] bsd-user/arm/target_arch_sysarch.h: Use consistent include guards

On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote: > > As part of upstreaming, the include guards have been made more > consistent. Update this file to use the new guards. > > Signed-off-by: Warner Losh > --- > bsd-user/arm/target_arch_sysarch.h | 6 +++--- > 1 file changed, 3 insertions(+), 3

Re: [PATCH 02/24] bsd-user/arm/target_syscall.h: Add copyright and update name

On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote: > > The preferred name for the 32-bit arm is now armv7. Update the name to > reflect that. In addition, add Stacey's copyright to this file and > update the include guards to the new convention. > > Signed-off-by: Stacey Son > Signed-off-by: War

Re: [PATCH 05/24] bsd-user/arm/target_arch_cpu.h: Implement target_cpu_clone_regs

On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote: > > Implement target_cpu_clone_regs to clone the resister state on a fork. > > Signed-off-by: Stacey Son > Signed-off-by: Warner Losh > --- > bsd-user/arm/target_arch_cpu.h | 8 > 1 file changed, 8 insertions(+) > > diff --git a/bsd-u

Re: [PATCH 09/24] bsd-user/arm/target_arch_cpu.h: Implement system call dispatch

On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote: > > Implement the system call dispatch. This implements all three kinds of > system call: direct and the two indirect variants. It handles all the > special cases for thumb as well. > > Signed-off-by: Stacey Son > Signed-off-by: Klye Evans > Si

Re: [PATCH 04/24] bsd-user/arm/target_arch_cpu.h: CPU Loop definitions

On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote: > > target_arch_cpu.h is for CPU loop definitions. Create the file and > define target_cpu_init and target_cpu_reset for arm. > > Signed-off-by: Olivier Houchard > Signed-off-by: Stacey Son > Signed-off-by: Warner Losh > --- > bsd-user/arm/ta

Re: [PATCH 03/24] bsd-user/arm/target_arch_cpu.c: Target specific TLS routines

On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote: > > Target specific TLS routines to get and set the TLS values. > > Signed-off-by: Klye Evans s/Klye/Kyle/ :-) > Signed-off-by: Stacey Son > Signed-off-by: Warner Losh > --- > bsd-user/arm/target_arch.h | 28 >

Re: [PATCH 06/24] bsd-user/arm/target_arch_cpu.h: Dummy target_cpu_loop implementation

On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote: > > Add a boiler plate CPU loop that does nothing except return an error for > all traps. > > Signed-off-by: Sean Bruno > Signed-off-by: Stacey Son > Signed-off-by: Warner Losh > --- > bsd-user/arm/target_arch_cpu.h | 22 +

Re: [PATCH 3/3] target/mips: Fix Loongson-3A4000 MSAIR config register

On 10/22/21 19:45, Philippe Mathieu-Daudé wrote: > When using the Loongson-3A4000 CPU, the MSAIR is returned with a > zero value (because unimplemented). Checking on real hardware, > this value appears incorrect: > > $ cat /proc/cpuinfo > system type : generic-loongson-machine > machine

[PATCH v3 00/22] QEMU RISC-V AIA support

The advanced interrupt architecture (AIA) extends the per-HART local interrupt support. Along with this, it also adds IMSIC (MSI contrllor) and Advanced PLIC (wired interrupt controller). The latest AIA draft specification can be found here: https://github.com/riscv/riscv-aia/releases/download/0.2

[PATCH v3 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode

We should be returning illegal instruction trap when RV64 HS-mode tries to access RV32 HS-mode CSR. Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions") Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+),

[PATCH v3 03/22] target/riscv: Implement hgeie and hgeip CSRs

The hgeie and hgeip CSRs are required for emulating an external interrupt controller capable of injecting virtual external interrupt to Guest/VM running at VS-level. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.c| 61 --

[PATCH v3 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs

A hypervsior can optionally take guest external interrupts using SGEIP bit of hip and hie CSRs. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 ++- target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c | 18 +++--- 3 files changed, 16 in

[PATCH v3 05/22] target/riscv: Allow setting CPU feature from machine/device emulation

The machine or device emulation should be able to force set certain CPU features because: 1) We can have certain CPU features which are in-general optional but implemented by RISC-V CPUs on the machine. 2) We can have devices which require a certain CPU feature. For example, AIA IMSIC devices

[PATCH v3 06/22] target/riscv: Add AIA cpu feature

We define a CPU feature for AIA CSR support in RISC-V CPUs which can be set by machine/device emulation. The RISC-V CSR emulation will also check this feature for emulating AIA CSRs. Signed-off-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 3 ++- 1

[PATCH v3 04/22] target/riscv: Improve delivery of guest external interrupts

The guest external interrupts from an interrupt controller are delivered only when the Guest/VM is running (i.e. V=1). This means any guest external interrupt which is triggered while the Guest/VM is not running (i.e. V=0) will be missed on QEMU resulting in Guest with sluggish response to serial c

[PATCH v3 12/22] target/riscv: Implement AIA interrupt filtering CSRs

The AIA specificaiton adds interrupt filtering support for M-mode and HS-mode. Using AIA interrupt filtering M-mode and H-mode can take local interrupt 13 or above and selectively inject same local interrupt to lower privilege modes. At the moment, we don't have any local interrupts above 12 so we

[PATCH v3 09/22] target/riscv: Implement AIA local interrupt priorities

The AIA spec defines programmable 8-bit priority for each local interrupt at M-level, S-level and VS-level so we extend local interrupt processing to consider AIA interrupt priorities. The AIA CSRs which help software configure local interrupt priorities will be added by subsequent patches. Signed

[PATCH v3 15/22] target/riscv: Implement AIA IMSIC interface CSRs

The AIA specification defines IMSIC interface CSRs for easy access to the per-HART IMSIC registers without using indirect xiselect and xireg CSRs. This patch implements the AIA IMSIC interface CSRs. Signed-off-by: Anup Patel --- target/riscv/csr.c | 199 ++

[PATCH v3 07/22] target/riscv: Add defines for AIA CSRs

The RISC-V AIA specification extends RISC-V local interrupts and introduces new CSRs. This patch adds defines for the new AIA CSRs. Signed-off-by: Anup Patel --- target/riscv/cpu_bits.h | 128 1 file changed, 128 insertions(+) diff --git a/target/riscv/c

[PATCH v3 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32

The AIA specification adds new CSRs for RV32 so that RISC-V hart can support 64 local interrupts on both RV32 and RV64. Signed-off-by: Anup Patel --- target/riscv/cpu.h| 14 +- target/riscv/cpu_helper.c | 10 +- target/riscv/csr.c| 560 +++--- ta

[PATCH v3 20/22] hw/intc: Add RISC-V AIA IMSIC device emulation

The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for MSIs (message signal interrupts) called IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC is per-HART device and also suppport virtualizaiton of MSIs using dedicated VS-level guest interrupt files.

[PATCH v3 13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs

The AIA specification introduces new [m|s|vs]topi CSRs for reporting pending local IRQ number and associated IRQ priority. Signed-off-by: Anup Patel --- target/riscv/csr.c | 154 + 1 file changed, 154 insertions(+) diff --git a/target/riscv/csr.c b/ta

[PATCH v3 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback

The AIA device emulation (such as AIA IMSIC) should be able to set (or provide) AIA ireg read-modify-write callback for each privilege level of a RISC-V HART. Signed-off-by: Anup Patel --- target/riscv/cpu.h| 19 +++ target/riscv/cpu_helper.c | 14 ++ 2 files

[PATCH v3 14/22] target/riscv: Implement AIA xiselect and xireg CSRs

The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs which allow indirect access to interrupt priority arrays and per-HART IMSIC registers. This patch implements AIA xiselect and xireg CSRs. Signed-off-by: Anup Patel --- target/riscv/cpu.h | 7 ++ target/riscv/csr.c | 17

[PATCH v3 16/22] hw/riscv: virt: Use AIA INTC compatible string when available

We should use the AIA INTC compatible string in the CPU INTC DT nodes when the CPUs support AIA feature. This will allow Linux INTC driver to use AIA local interrupt CSRs. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- hw/riscv/virt.c | 13 +++-- 1 file changed, 11 insertio

[PATCH v3 22/22] docs/system: riscv: Document AIA options for virt machine

We have two new machine options "aia" and "aia-guests" available for the RISC-V virt machine so let's document these options. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- docs/system/riscv/virt.rst | 16 1 file changed, 16 insertions(+) diff --git a/docs/system/

[PATCH v3 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs

The AIA hvictl and hviprioX CSRs allow hypervisor to control interrupts visible at VS-level. This patch implements AIA hvictl and hviprioX CSRs. Signed-off-by: Anup Patel --- target/riscv/cpu.h | 1 + target/riscv/csr.c | 126 + target/riscv/mach

[PATCH v3 17/22] target/riscv: Allow users to force enable AIA CSRs in HART

We add "x-aia" command-line option for RISC-V HART using which allows users to force enable CPU AIA CSRs without changing the interrupt controller available in RISC-V machine. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 + target/riscv/cpu.h | 1 + 2 f

[PATCH v3 18/22] hw/intc: Add RISC-V AIA APLIC device emulation

The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for wired interrupts called APLIC (Advanced Platform Level Interrupt Controller). The APLIC is capabable of forwarding wired interupts to RISC-V HARTs directly or as MSIs (Message Signaled Interupts). This patch ad

[PATCH v3 19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine

We extend virt machine to emulate AIA APLIC devices only when "aia=aplic" parameter is passed along with machine name in QEMU command-line. When "aia=none" or not specified then we fallback to original PLIC device emulation. Signed-off-by: Anup Patel --- hw/riscv/Kconfig| 1 + hw/riscv

[PATCH v3 21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine

We extend virt machine to emulate both AIA IMSIC and AIA APLIC devices only when "aia=aplic-imsic" parameter is passed along with machine name in the QEMU command-line. The AIA IMSIC is only a per-HART MSI controller so we use AIA APLIC in MSI-mode to forward all wired interrupts as MSIs to the AIA

Re: [PATCH 15/33] target/ppc: Implement Vector Insert from GPR using GPR index insns

On Fri, 22 Oct 2021, Richard Henderson wrote: On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: +#if defined(TARGET_PPC64) +return do_vinsx(ctx, a->vrt, size, right, cpu_gpr[a->vra], cpu_gpr[a->vrb], +gen_helper); +#else +bool ok; +TCGv_i64 val; + +

Re: [PATCH 3/3] target/mips: Fix Loongson-3A4000 MSAIR config register

在 2021/10/22 18:45, Philippe Mathieu-Daudé 写道: When using the Loongson-3A4000 CPU, the MSAIR is returned with a zero value (because unimplemented). Checking on real hardware, this value appears incorrect: $ cat /proc/cpuinfo system type : generic-loongson-machine machine :

Re: Looking for advise on debugging a non-boot kernel on qemu-system-sh4

Hello, On Sat, 23 Oct 2021, John Paul Adrian Glaubitz wrote: On 10/23/21 03:07, BALATON Zoltan wrote: I can confirm that the default config works for me, too. Both with gcc-8 and gcc-11. OK with your config I can reproduce the problem too but the kernel with that config is 177MB and the r2d

Re: [PATCH v2 1/2] vfio/pci: Fix vfio-pci sub-page MMIO BAR mmaping in live migration

Hi Kunkun, On 10/22/21 12:01 PM, Kunkun Jiang wrote: > Hi Eric, > > On 2021/10/22 0:15, Eric Auger wrote: >> Hi Kunkun, >> >> On 9/14/21 3:53 AM, Kunkun Jiang wrote: >>> We expand MemoryRegions of vfio-pci sub-page MMIO BARs to >>> vfio_pci_write_config to improve IO performance. >> s/to vfio_pci_

Re: [PATCH 09/24] bsd-user/arm/target_arch_cpu.h: Implement system call dispatch

On Sat, Oct 23, 2021 at 1:34 AM Kyle Evans wrote: > On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote: > > > > Implement the system call dispatch. This implements all three kinds of > > system call: direct and the two indirect variants. It handles all the > > special cases for thumb as well. >

[PATCH] tests/tcg: Fix some targets default cross compiler path

We do not want a shell command substitution, but a parameter substitution (with assignment). Replace $() -> ${}, otherwise the expanded command return an empty string and the $cross_cc variable is not set. Fixes: 634ef789f8e ("tests/tcg: add more default compilers to configure.sh") Signed-off-by:

Re: [PATCH] tests/tcg: Fix some targets default cross compiler path

Philippe Mathieu-Daudé writes: > We do not want a shell command substitution, but a parameter > substitution (with assignment). Replace $() -> ${}, otherwise > the expanded command return an empty string and the $cross_cc > variable is not set. Queued to testing/next, thanks. -- Alex Bennée

Re: [PATCH] tests/tcg: Fix some targets default cross compiler path

On Sat, Oct 23, 2021 at 7:47 PM Alex Bennée wrote: > Philippe Mathieu-Daudé writes: > > > We do not want a shell command substitution, but a parameter > > substitution (with assignment). Replace $() -> ${}, otherwise > > the expanded command return an empty string and the $cross_cc > > variable i

Re: [PATCH v3 33/48] tcg/optimize: Add type to OptContext

On 10/22/21 3:11 PM, Luis Fernando Fujita Pires wrote: From: Richard Henderson @@ -1392,18 +1408,18 @@ void tcg_optimize(TCGContext *s) /* Proceed with possible constant folding. */ break; } -if (opc == INDEX_op_sub_

[PULL 09/11] README: Fix some documentation URLs

From: Greg Kurz All of these pages live in the wiki, not in the main web site. Signed-off-by: Greg Kurz Reviewed-by: Laurent Vivier Tested-by: Laurent Vivier Message-Id: <163456470882.196333.17366490695504718038.stgit@bahia.huguette> Signed-off-by: Laurent Vivier --- README.rst | 14 +++

[PULL 01/11] po: update turkish translation

From: Oğuz Ersen Message-Id: Signed-off-by: Oğuz Ersen Reviewed-by: Laurent Vivier [lv,pb: s/K_opyala/_Kopyala/;s/Se_kmeleri/_Sekmeleri/] Signed-off-by: Laurent Vivier --- po/tr.po | 25 - 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/po/tr.po b/po/

[PULL 00/11] Trivial branch for 6.2 patches

branch-for-6.2-pull-request for you to fetch changes up to 2c92be50bcfa8b7529a39fc99078ef14dcfc71aa: analyze-migration.py: fix extract contents ('-x') errors (2021-10-23 20:28:56 +0200) Trivial patches p

[PULL 05/11] softmmu/physmem.c: Fix typo in comment

From: Greg Kurz Fix the comment to match what the code is doing, as explained in the changelog of commit 86cf9e154632cb28d749db0ea47946fba8cf3f09 that introduced the change: Commit 9458a9a1df1a4c719e24512394d548c1fc7abd22 added synchronization of vCPU and migration operations through cal

[PULL 02/11] disas/nios2: Fix style in print_insn_nios2()

From: Philippe Mathieu-Daudé We are going to modify this function, fix its style first. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Reviewed-by: Thomas Huth Message-Id: <20210807110939.95853-2-f4...@amsat.org> Signed-off-by: Laurent Vivier --- disas/nios2.c | 55 ++

[PULL 03/11] disas/nios2: Simplify endianess conversion

From: Philippe Mathieu-Daudé Since commit 12b6e9b27d4 ("disas: Clean up CPUDebug initialization") the disassemble_info->bfd_endian enum is set for all targets in target_disas(). We can directly call print_insn_nios2() and simplify. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivi

[PULL 04/11] MAINTAINERS: Add myself as reviewer of 'Machine core' API

From: Philippe Mathieu-Daudé In order to help Eduardo and Marcel with the machine core API, add myself as reviewer. That will also help me to learn more about this subsystem :) Signed-off-by: Philippe Mathieu-Daudé Reviewed by: Marcel Apfelbaum Message-Id: <20211007093108.323223-1-phi...@redha

[PULL 10/11] analyze-migration.py: fix a long standing typo

From: Laurent Vivier The parameters of '-d' can be either 'state' or 'desc', not 'dump' as it is reported in the error message. Fixes: b17425701d66 ("Add migration stream analyzation script") Signed-off-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211015131645.501281-2

[PULL 11/11] analyze-migration.py: fix extract contents ('-x') errors

From: Laurent Vivier When we try to use 'analyze-migration.py -x' with python3, we have the following errors: Traceback (most recent call last): File "scripts/analyze-migration.py", line 593, in f.write(jsonenc.encode(dump.vmsd_desc)) TypeError: a bytes-like object is required, no

[PULL 06/11] hw/nvram: Fix Memory Leak in Xilinx eFuse QOM

From: Tong Ho Signed-off-by: Tong Ho Reviewed-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211015203532.2463705-2-tong...@xilinx.com> Signed-off-by: Laurent Vivier --- hw/nvram/xlnx-efuse.c | 9 ++--- 1 file changed, 6 insertio

Re: [PATCH 15/33] target/ppc: Implement Vector Insert from GPR using GPR index insns

On 10/23/21 3:12 AM, BALATON Zoltan wrote: You mentioning target_ulong reminded me a question I had. Currently we have qemu-system-ppc and qemu-system-ppc64 but the latter includes all machines of the former too so you could run for example sam460ex with qemu-system-ppc64 (except mac99 which be

[PULL 08/11] hw/nvram: Fix Memory Leak in Xilinx ZynqMP eFuse device

From: Tong Ho Signed-off-by: Tong Ho Reviewed-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211015203532.2463705-4-tong...@xilinx.com> Signed-off-by: Laurent Vivier --- hw/nvram/xlnx-zynqmp-efuse.c | 18 -- 1 file ch

[PULL 07/11] hw/nvram: Fix Memory Leak in Xilinx Versal eFuse device

From: Tong Ho Signed-off-by: Tong Ho Reviewed-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211015203532.2463705-3-tong...@xilinx.com> Signed-off-by: Laurent Vivier --- hw/nvram/xlnx-versal-efuse-ctrl.c | 20 +++- 1

[PATCH] linux-user/signal: Map exit signals in SIGCHLD siginfo_t

When converting a siginfo_t from waitid(), the interpretation of si_status depends on the value of si_code: For CLD_EXITED, it is an exit code and should be copied verbatim. For other codes, it is a signal number (possibly with additional high bits from ptrace) that should be mapped. This code was

Re: [PATCH 19/33] target/ppc: Implement Vector Extract Double to VSR using GPR index insns

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Implement the following PowerISA v3.1 instructions: vextdubvlx: Vector Extract Double Unsigned Byte to VSR using GPR-specified Left-Index vextduhvlx: Vector Extract Double Unsigned Halfword to VSR using

Re: [PATCH 15/33] target/ppc: Implement Vector Insert from GPR using GPR index insns

On Sat, 23 Oct 2021, Richard Henderson wrote: On 10/23/21 3:12 AM, BALATON Zoltan wrote: You mentioning target_ulong reminded me a question I had. Currently we have qemu-system-ppc and qemu-system-ppc64 but the latter includes all machines of the former too so you could run for example sam460ex

Re: [PATCH 15/33] target/ppc: Implement Vector Insert from GPR using GPR index insns

On 10/23/21 1:02 PM, BALATON Zoltan wrote: So may question was not if it's possible but if having target_ulong different from what we had in qemu-system-ppc could cause any problems? I have no experience running 32-bit guests with qemu-system-ppc64 but previously when this came up one difference

Re: [PATCH 20/33] target/ppc: Introduce REQUIRE_VSX macro

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: "Bruno Larsen (billionai)" Introduce the macro to centralize checking if the VSX facility is enabled and handle it correctly. Signed-off-by: Bruno Larsen (billionai) Signed-off-by: Luis Pires Signed-off-by: Matheus Ferst --- tar

Re: [PATCH v8 07/10] ACPI ERST: create ACPI ERST table for pc/x86 machines

On Sat, Oct 23, 2021 at 07:52:21AM +0530, Ani Sinha wrote: > > > On Fri, 22 Oct 2021, Eric DeVolder wrote: > > > Ani, inline below. > > eric > > > > On 10/22/21 05:18, Ani Sinha wrote: > > > > > > > > > On Fri, 15 Oct 2021, Eric DeVolder wrote: > > > > > > > This change exposes ACPI ERST support

Re: [RESEND PATCH 2/2] hw/i386: Rename default_bus_bypass_iommu

On Fri, Oct 22, 2021 at 03:58:28PM +0100, Jean-Philippe Brucker wrote: > On Fri, Oct 22, 2021 at 10:46:08AM -0400, Michael S. Tsirkin wrote: > > On Wed, Oct 13, 2021 at 05:06:08PM +0100, Jean-Philippe Brucker wrote: > > > Since commit d8fb7d0969d5 ("vl: switch -M parsing to keyval"), machine > > >

Re: [PATCH 21/33] target/ppc: moved stxv and lxv from legacy to decodtree

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: +static bool do_lstxv(DisasContext *ctx, int ra, int displ, + int rt, bool store) You need an int64_t displ before you add PLXV et al. What happened to passing in arg_D as for the other integer instructions? +

Re: [PATCH 22/33] target/ppc: moved stxvx and lxvx from legacy to decodtree

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: @@ -2075,7 +1969,7 @@ static void gen_xvxsigdp(DisasContext *ctx) tcg_temp_free_i64(xbl); } -static bool do_lstxv(DisasContext *ctx, int ra, int displ, +static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ,

Re: [PATCH 21/33] target/ppc: moved stxv and lxv from legacy to decodtree

On 10/23/21 1:34 PM, Richard Henderson wrote: On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: +static bool do_lstxv(DisasContext *ctx, int ra, int displ, + int rt, bool store) You need an int64_t displ before you add PLXV et al.  What happened to passing in arg_D

Re: [PATCH 21/33] target/ppc: moved stxv and lxv from legacy to decodtree

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: +if (ctx->le_mode) { +gen_addr_add(ctx, ea, ea, 8); +offset = -8; +} else { +offset = 8; +} + +if (store) { +get_cpu_vsrh(xt, rt); +tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop); +

Re: [PATCH 23/33] target/ppc: added the instructions LXVP and STXVP

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: if (ctx->le_mode) { -gen_addr_add(ctx, ea, ea, 8); +gen_addr_add(ctx, ea, ea, paired ? 24 : 8); Still questioning the address of the fault, but the rest of it looks ok. r~

Re: [PATCH 24/33] target/ppc: added the instructions LXVPX and STXVPX

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: "Lucas Mateus Castro (alqotel)" Implemented the instructions lxvpx and stxvpx using decodetree Signed-off-by: Lucas Mateus Castro (alqotel) Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 3 +++ target/p

Re: [PATCH 25/33] target/ppc: added the instructions PLXV and PSTXV

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: "Lucas Mateus Castro (alqotel)" Implemented the instructions plxv and pstxv using decodetree Signed-off-by: Lucas Mateus Castro (alqotel) Signed-off-by: Matheus Ferst --- target/ppc/insn64.decode| 10 ++ tar

Re: [PATCH 26/33] target/ppc: added the instructions PLXVP and PSTXVP

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: "Lucas Mateus Castro (alqotel)" Implemented the instructions plxvp and pstxvp using decodetree Signed-off-by: Lucas Mateus Castro (alqotel) Signed-off-by: Matheus Ferst --- target/ppc/insn64.decode| 9 + tar

Re: [PATCH 27/33] target/ppc: moved XXSPLTW to using decodetree

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: "Bruno Larsen (billionai)" Changed the function that handles XXSPLTW emulation to using decodetree, but still using the same logic. Signed-off-by: Bruno Larsen (billionai) Signed-off-by: Matheus Ferst --- target/ppc/insn32.decod

Re: [PATCH 28/33] target/ppc: moved XXSPLTIB to using decodetree

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: "Bruno Larsen (billionai)" Changed the function that handles XXSPLTIB emulation to using decodetree, but still use the same logic as before Signed-off-by: Bruno Larsen (billionai) Signed-off-by: Matheus Ferst --- target/ppc/insn

Re: [PATCH 29/33] target/ppc: implemented XXSPLTI32DX

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: "Bruno Larsen (billionai)" Implemented XXSPLTI32DX emulation using decodetree Signed-off-by: Bruno Larsen (billionai) Signed-off-by: Matheus Ferst --- target/ppc/insn64.decode| 11 target/ppc/translate/v

Re: [PATCH 30/33] target/ppc: Implemented XXSPLTIW using decodetree

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: "Bruno Larsen (billionai)" Implemented the XXSPLTIW instruction, using decodetree. Signed-off-by: Bruno Larsen (billionai) Signed-off-by: Matheus Ferst --- target/ppc/insn64.decode| 6 ++ target/ppc/translate/v

Re: [PATCH 31/33] target/ppc: implemented XXSPLTIDP instruction

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: "Bruno Larsen (billionai)" Implemented the instruction XXSPLTIDP using decodetree. Signed-off-by: Bruno Larsen (billionai) Signed-off-by: Matheus Ferst --- target/ppc/insn64.decode| 2 ++ target/ppc/translate/vsx-i

Re: [PATCH 32/33] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Bruno Larsen (billionai) Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 4 +++ target/ppc/insn64.decode| 19 ++ target/ppc/int_helper.c | 15

Re: [PATCH 33/33] target/ppc: Implement lxvkq instruction

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote: +static bool trans_LXVKQ(DisasContext *ctx, arg_X_uim5 *a) +{ +static const uint32_t valid_values = 0b00010010; All of the specified values are non-zero, so this kinda duplicates the values table. Otherwise,

[PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree

Hi, This series converts 2000+ lines of switch() code to decodetree description, so this hard-to-review/modify switch is auto generated by the decodetree script. This is a big win for maintenance (and indeed the convertion revealed 2 bugs). Massive convertions are - beside being often boring - bu

[PATCH 01/33] tests/tcg: Fix some targets default cross compiler path

We do not want a shell command substitution, but a parameter substitution (with assignment). Replace $() -> ${}, otherwise the expanded command return an empty string and the $cross_cc variable is not set. Fixes: 634ef789f8e ("tests/tcg: add more default compilers to configure.sh") Signed-off-by:

[PATCH 04/33] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation

The following commits added various user-mode tests for various MSA instructions: - 0fdd986a6c8 ("Add tests for MSA integer add instructions") - 1be82d89011 ("Add tests for MSA integer average instructions") - 1d336c87a3c ("Add tests for MSA bit set instructions") - 1e6bea794c8 ("Add tests for

[PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree

Convert the LDI opcode (Immediate Load) to decodetree. Since it overlaps with the generic MSA handler, use a decodetree overlap group. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/

[PATCH 19/33] target/mips: Convert MSA VEC instruction format to decodetree

Convert 3-register instructions with implicit data formats to decodetree. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 8 target/mips/tcg/msa_translate.c | 82 +++-- 2 files changed, 24 insertions(+), 66 deletions(-) diff --git a/

[PATCH 03/33] target/mips: Fix MSA MSUBV.B opcode

The result of the 'Vector Multiply and Subtract' opcode is incorrect with Byte vectors. Probably due to a copy/paste error, commit 5f148a02327 mistakenly used the $wt (target register) instead of $wd (destination register) as first operand. Fix that. Cc: Aleksandar Rikalo Fixes: 5f148a02327 ("ta

[PATCH 02/33] target/mips: Fix MSA MADDV.B opcode

The result of the 'Vector Multiply and Add' opcode is incorrect with Byte vectors. Probably due to a copy/paste error, commit 7a7a162adde mistakenly used the $wt (target register) instead of $wd (destination register) as first operand. Fix that. Cc: Aleksandar Rikalo Fixes: 7a7a162adde ("target/m

[PATCH 10/33] target/mips: Extract df_extract() helper

Extract the common code which parses data formats to an helper. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa_translate.c | 68 +++-- 1 file changed, 39 insertions(+), 29 deletions(-) diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_

[PATCH 05/33] target/mips: Have check_msa_access() return a boolean

Have check_msa_access() return a boolean value so we can return early if MSA is not enabled. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa_translate.c | 20 +--- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/target/mips/tcg/msa_translate.c b/targe

[PATCH 06/33] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum

Replace magic DataFormat value by the corresponding enum from CPUMIPSMSADataFormat. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa_translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.

[PATCH 12/33] target/mips: Convert MSA BIT instruction format to decodetree

Convert instructions with an immediate bit index and data format df/m to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 15 + target/mips/tcg/msa_tr

[PATCH 23/33] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)

Convert 3-register operations to decodetree. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 11 ++ target/mips/tcg/msa_translate.c | 213 +--- 2 files changed, 66 insertions(+), 158 deletions(-) diff --git a/target/mips/tcg/msa.decode b/

[PATCH 09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers

Similar to the TRANS() macro introduced in commit fb3164e412d, introduce TRANS_CHECK() which takes a boolean expression as argument. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h | 9 + 1 file changed, 9 insertions(+) diff --git a/target/mips/tcg/translate.h b/ta

[PATCH 22/33] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)

Convert 3-register operations to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 6 ++ target/mips/tcg/msa_translate.c | 35 ++--

[PATCH 07/33] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v

This 'shift amount' format is not always 16-bit, so name it generically as 'sa'. This will help to unify the various arg_msa decodetree generated structures. Rename the @bz format -> @bz_v (specific @bz with df=3) and @bz_df -> @bz (generic @bz). Signed-off-by: Philippe Mathieu-Daudé --- target

[PATCH 13/33] target/mips: Convert MSA SHF opcode to decodetree

Convert the SHF opcode (Immediate Set Shuffle Elements) to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 3 +++ target/mips/tcg/msa_translate.c | 47 +

[PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree

Convert instructions with a 5-bit immediate value to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 15 + target/mips/tcg/msa_translate.c | 99 +

[PATCH 31/33] target/mips: Remove generic MSA opcode

All opcodes have been converted to decodetree. The generic MSA handler is now pointless, remove it. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 2 -- target/mips/tcg/msa_translate.c | 7 --- 2 files changed, 9 deletions(-) diff --git a/target/mips/tcg/msa.dec

[PATCH 16/33] target/mips: Convert MSA 2RF instruction format to decodetree

Convert 2-register floating-point operations to decodetree. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 19 ++ target/mips/tcg/msa_translate.c | 109 2 files changed, 46 insertions(+), 82 deletions(-) diff --git a/target/mips

[PATCH 18/33] target/mips: Convert MSA 2R instruction format to decodetree

Convert 2-register operations to decodetree. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 3 ++ target/mips/tcg/msa_translate.c | 91 + 2 files changed, 28 insertions(+), 66 deletions(-) diff --git a/target/mips/tcg/msa.decode b/ta

[PATCH 14/33] target/mips: Convert MSA I8 instruction format to decodetree

Convert instructions with an 8-bit immediate value and either implicit data format or data format df to decodetree. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 8 target/mips/tcg/msa_translate.c | 72 + 2 files changed, 26 ins

[PATCH 20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)

Convert 3-register floating-point or fixed-point operations to decodetree. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 8 target/mips/tcg/msa_translate.c | 70 +++-- 2 files changed, 39 insertions(+), 39 deletions(-) diff --git a

[PATCH 26/33] target/mips: Convert MSA ELM instruction format to decodetree

Convert instructions with an immediate element index and data format df/n to decodetree. Since the 'data format' and 'n' fields are constant values, use tcg_constant_i32() instead of a TCG temporaries. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 6 + target/

[PATCH 15/33] target/mips: Convert MSA load/store instruction format to decodetree

Convert load/store instructions to decodetree. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 4 ++ target/mips/tcg/msa_translate.c | 99 + 2 files changed, 44 insertions(+), 59 deletions(-) diff --git a/target/mips/tcg/msa.decode b/

[PATCH 27/33] target/mips: Convert MSA COPY_U opcode to decodetree

Convert the COPY_U opcode (Element Copy to GPR Unsigned) to decodetree. Since the 'n' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 1 + target/mips/tcg/msa_translate.c | 90

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