Convert load/store instructions to decodetree.
Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
---
target/mips/tcg/msa.decode | 4 ++
target/mips/tcg/msa_translate.c | 99 +++++++++++++--------------------
2 files changed, 44 insertions(+), 59 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 3dd07dced57..5fe6923ace5 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -17,6 +17,7 @@
&msa_ldst df wd ws sa
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
+@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_ldst
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_ldst
@@ -73,5 +74,8 @@ BNZ 010001 111 .. ..... ................
@bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
+ LD 011110 .......... ..... ..... 1000 .. @ldst
+ ST 011110 .......... ..... ..... 1001 .. @ldst
+
MSA 011110 --------------------------
}
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 2866687635d..52af99636a4 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -38,16 +38,6 @@ enum {
OPC_MSA_3RF_1B = 0x1B | OPC_MSA,
OPC_MSA_3RF_1C = 0x1C | OPC_MSA,
OPC_MSA_VEC = 0x1E | OPC_MSA,
-
- /* MI10 instruction */
- OPC_LD_B = (0x20) | OPC_MSA,
- OPC_LD_H = (0x21) | OPC_MSA,
- OPC_LD_W = (0x22) | OPC_MSA,
- OPC_LD_D = (0x23) | OPC_MSA,
- OPC_ST_B = (0x24) | OPC_MSA,
- OPC_ST_H = (0x25) | OPC_MSA,
- OPC_ST_W = (0x26) | OPC_MSA,
- OPC_ST_D = (0x27) | OPC_MSA,
};
enum {
@@ -298,6 +288,10 @@ static inline bool check_msa_access(DisasContext *ctx)
#define TRANS_MSA(NAME, trans_func, gen_func) \
TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, gen_func)
+#define TRANS_DF_E(NAME, trans_func, gen_func) \
+ TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
+ gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d)
+
static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
TCGCond cond)
{
@@ -2104,55 +2098,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
case OPC_MSA_VEC:
gen_msa_vec(ctx);
break;
- case OPC_LD_B:
- case OPC_LD_H:
- case OPC_LD_W:
- case OPC_LD_D:
- case OPC_ST_B:
- case OPC_ST_H:
- case OPC_ST_W:
- case OPC_ST_D:
- {
- int32_t s10 = sextract32(ctx->opcode, 16, 10);
- uint8_t rs = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
- uint8_t df = (ctx->opcode >> 0) & 0x3;
-
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv taddr = tcg_temp_new();
- gen_base_offset_addr(ctx, taddr, rs, s10 << df);
-
- switch (MASK_MSA_MINOR(opcode)) {
- case OPC_LD_B:
- gen_helper_msa_ld_b(cpu_env, twd, taddr);
- break;
- case OPC_LD_H:
- gen_helper_msa_ld_h(cpu_env, twd, taddr);
- break;
- case OPC_LD_W:
- gen_helper_msa_ld_w(cpu_env, twd, taddr);
- break;
- case OPC_LD_D:
- gen_helper_msa_ld_d(cpu_env, twd, taddr);
- break;
- case OPC_ST_B:
- gen_helper_msa_st_b(cpu_env, twd, taddr);
- break;
- case OPC_ST_H:
- gen_helper_msa_st_h(cpu_env, twd, taddr);
- break;
- case OPC_ST_W:
- gen_helper_msa_st_w(cpu_env, twd, taddr);
- break;
- case OPC_ST_D:
- gen_helper_msa_st_d(cpu_env, twd, taddr);
- break;
- }
-
- tcg_temp_free_i32(twd);
- tcg_temp_free(taddr);
- }
- break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
@@ -2162,6 +2107,42 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
return true;
}
+static bool trans_msa_ldst(DisasContext *ctx, arg_msa_ldst *a,
+ void (*gen_msa_b)(TCGv_ptr, TCGv_i32, TCGv),
+ void (*gen_msa_h)(TCGv_ptr, TCGv_i32, TCGv),
+ void (*gen_msa_w)(TCGv_ptr, TCGv_i32, TCGv),
+ void (*gen_msa_d)(TCGv_ptr, TCGv_i32, TCGv))
+{
+
+ TCGv_i32 twd = tcg_const_i32(a->wd);
+ TCGv taddr = tcg_temp_new();
+
+ gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df);
+
+ switch (a->df) {
+ case DF_BYTE:
+ gen_msa_b(cpu_env, twd, taddr);
+ break;
+ case DF_HALF:
+ gen_msa_h(cpu_env, twd, taddr);
+ break;
+ case DF_WORD:
+ gen_msa_w(cpu_env, twd, taddr);
+ break;
+ case DF_DOUBLE:
+ gen_msa_d(cpu_env, twd, taddr);
+ break;
+ }
+
+ tcg_temp_free_i32(twd);
+ tcg_temp_free(taddr);
+
+ return true;
+}
+
+TRANS_DF_E(LD, trans_msa_ldst, gen_helper_msa_ld);
+TRANS_DF_E(ST, trans_msa_ldst, gen_helper_msa_st);
+
static bool trans_LSA(DisasContext *ctx, arg_r *a)
{
return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
--
2.31.1
