On Tue, 19 Jan 2021 10:14:55 +0530
Bharata B Rao wrote:
> On Fri, Jan 15, 2021 at 06:30:05PM +0100, Greg Kurz wrote:
> > On Fri, 15 Jan 2021 14:01:28 +0530
> > Bharata B Rao wrote:
> >
> > > On Wed, Jan 13, 2021 at 05:22:56PM +0100, Greg Kurz wrote:
> > > > Hi Bharata,
> > > >
> > > > On Wed,
On 21-01-19 08:32:21, Klaus Jensen wrote:
> On Jan 17 23:53, Minwoo Im wrote:
> > Volatile Write Cache(VWC) feature is set in nvme_ns_setup() in the
> > initial time. This feature is related to block device backed, but this
> > feature is controlled in controller level via Set/Get Features comman
On Mon, 18 Jan 2021 19:47:30 +
"Dr. David Alan Gilbert" wrote:
> * David Gibson (da...@gibson.dropbear.id.au) wrote:
> > The platform specific details of mechanisms for implementing
> > confidential guest support may require setup at various points during
> > initialization. Thus, it's not r
On Fri, 15 Jan 2021 10:55:14 -0800
Ram Pai wrote:
> On Wed, Jan 13, 2021 at 09:06:29AM +0100, Cornelia Huck wrote:
> > On Tue, 12 Jan 2021 10:55:11 -0800
> > Ram Pai wrote:
> >
> > > On Tue, Jan 12, 2021 at 09:19:43AM +0100, Cornelia Huck wrote:
> > > > On Mon, 11 Jan 2021 11:58:30 -0800
>
On 18.01.21 18:39, Dr. David Alan Gilbert wrote:
> * David Gibson (da...@gibson.dropbear.id.au) wrote:
>> On Thu, Jan 14, 2021 at 11:25:17AM +, Daniel P. Berrangé wrote:
>>> On Wed, Jan 13, 2021 at 12:42:26PM +, Dr. David Alan Gilbert wrote:
* Cornelia Huck (coh...@redhat.com) wrote
On Tue, 19 Jan 2021 09:28:22 +0100
Christian Borntraeger wrote:
> On 18.01.21 18:39, Dr. David Alan Gilbert wrote:
> > * David Gibson (da...@gibson.dropbear.id.au) wrote:
> >> On Thu, Jan 14, 2021 at 11:25:17AM +, Daniel P. Berrangé wrote:
> >>> On Wed, Jan 13, 2021 at 12:42:26PM +, D
From: Peter Maydell
The next_irq() function is global, but isn't actually used anywhere
outside next-cube.c. Make it static.
Signed-off-by: Peter Maydell
Message-Id: <20210115201206.17347-2-peter.mayd...@linaro.org>
Signed-off-by: Thomas Huth
---
hw/m68k/next-cube.c | 2 +-
include/hw
From: Peter Maydell
Move the registers handled by the scr_ops struct into the NeXTPC
device.
Signed-off-by: Peter Maydell
Message-Id: <20210115201206.17347-5-peter.mayd...@linaro.org>
Signed-off-by: Thomas Huth
---
hw/m68k/next-cube.c | 50 ++---
1 file
Hi Peter,
the following changes since commit e43d564fa3a0d1e133935c8180ad4f4ccf699f33:
Merge remote-tracking branch
'remotes/vivier2/tags/trivial-branch-for-6.0-pull-request' into staging
(2021-01-18 15:19:06 +)
are available in the Git repository at:
https://gitlab.com/huth/qemu.git
From: Peter Maydell
Currently the next-cube board code open-codes a lot of handling of
interrupts and some miscellaneous registers. Move this into a proper
QOM device.
In the real hardware this functionality seems to be the
responsibility of the Peripheral Controller (PC) chip, so name the
devi
From: Peter Maydell
Make the next_irq function be GPIO inputs to the NEXT_PC
device, rather than a freestanding set of qemu_irq lines.
This fixes a minor Coverity issue where it correctly points
out the trivial memory leak of the memory allocated in the
call to qemu_allocate_irqs().
Fixes: CID
From: Peter Maydell
Make the next_irq function take a NeXTPC* as its opaque rather than
the M68kCPU*. This will make it simpler to turn the next_irq
function into a gpio input line of the NeXTPC device in the next
commit.
For this to work we have to pass the CPU to the NeXTPC device via a
link
From: Peter Maydell
All the code which accesses int_status and int_mask is now doing
so via the NeXTPC->NeXTState indirection, so we can move these
fields into the NeXTPC struct where they belong.
Signed-off-by: Peter Maydell
Message-Id: <20210115201206.17347-7-peter.mayd...@linaro.org>
Signed-
From: Peter Maydell
Move the registers handled by the mmio_ops struct into the NeXTPC
device. This allows us to also move the scr1 and scr2 data fields.
Signed-off-by: Peter Maydell
Message-Id: <20210115201206.17347-4-peter.mayd...@linaro.org>
Signed-off-by: Thomas Huth
---
hw/m68k/next-cube
From: Peter Maydell
The next-cube.h file is missing the usual copyright-and-license
header; add it (same as the next-cube.c one).
Signed-off-by: Peter Maydell
Message-Id: <20210115201206.17347-12-peter.mayd...@linaro.org>
Signed-off-by: Thomas Huth
---
include/hw/m68k/next-cube.h | 10 +++
From: Peter Maydell
Add the vmstate for the new NeXTPC devic; this is in theory
a migration compatibility break, but this machine doesn't have
working migration currently anyway.
Signed-off-by: Peter Maydell
Message-Id: <20210115201206.17347-11-peter.mayd...@linaro.org>
Signed-off-by: Thomas Hu
From: Peter Maydell
Move the rtc into the NeXTPC struct. Since this is the last
use of the 'backdoor' NextState pointer we can now remove that.
Probably the RTC should be its own device at some point: in hardware
there is a separate MCS1850 RTC chip connected to the Peripheral
Controller via a 1
From: Peter Maydell
The fields scsi_irq, scsi_dma, scsi_reset and fd_irq in
NeXTState are all unused, except in commented out
"this should do something like this" code. Remove the
unused fields. As and when the functionality that might
use them is added, we can put in the correct kind of
wiring (
On Mon, Jan 18, 2021 at 04:03:12PM +, Dr. David Alan Gilbert wrote:
* Stefano Garzarella (sgarz...@redhat.com) wrote:
Commit 9d7bd0826f introduced a new 'use-disabled-flag' property
set to true by default.
To allow the migration, we set this property to false in the hw_compat,
but in the wro
* Philippe Mathieu-Daudé (f4...@amsat.org) wrote:
> Add vmstate_qdev_no_state_to_migrate, which is simply a
> pointer to vmstate_no_state_to_migrate. This way all
> qdev devices (including "hw/qdev-core.h") don't have to
> include "migration/vmstate.h".
>
> Signed-off-by: Philippe Mathieu-Daudé
>
Am 18.01.21 um 23:33 schrieb Jason Dillaman:
> On Fri, Jan 15, 2021 at 10:39 AM Peter Lieven wrote:
>> Am 15.01.21 um 16:27 schrieb Jason Dillaman:
>>> On Thu, Jan 14, 2021 at 2:59 PM Peter Lieven wrote:
Am 14.01.21 um 20:19 schrieb Jason Dillaman:
> On Sun, Dec 27, 2020 at 11:42 AM Pete
Currently, the website is rebuilt on qemu-project.org using
an update hook. We can reuse instead the Jekyll output of
GitLab's CI.
To do so, a new user qemu-deploy has been created on qemu.org.
The private key is stored into a file variable SSH_PRIVATE_KEY_FILE
(be careful to include the trailing
On Mon, 18 Jan 2021 16:30:35 -0300
Daniel Henrique Barboza wrote:
> Commit 47c8c915b162 fixed a problem where multiple spapr_drc_detach()
> requests were breaking QEMU. The solution was to just spapr_drc_detach()
> once, and use spapr_drc_unplug_requested() to filter whether we
> already detached
On Tue, Jan 19, 2021 at 10:37:46AM +0100, Paolo Bonzini wrote:
> Currently, the website is rebuilt on qemu-project.org using
> an update hook. We can reuse instead the Jekyll output of
> GitLab's CI.
Are there any files present on the qemu-project.org webroot
other than the published output of Je
On 19/01/2021 10.37, Paolo Bonzini wrote:
Currently, the website is rebuilt on qemu-project.org using
an update hook. We can reuse instead the Jekyll output of
GitLab's CI.
To do so, a new user qemu-deploy has been created on qemu.org.
The private key is stored into a file variable SSH_PRIVATE_
On Fri, Jan 15, 2021 at 10:55:14AM -0800, Ram Pai wrote:
> On Wed, Jan 13, 2021 at 09:06:29AM +0100, Cornelia Huck wrote:
> > On Tue, 12 Jan 2021 10:55:11 -0800
> > Ram Pai wrote:
> >
> > > On Tue, Jan 12, 2021 at 09:19:43AM +0100, Cornelia Huck wrote:
> > > Actually the two options are inherentl
On 19/01/21 10:58, Thomas Huth wrote:
On 19/01/2021 10.37, Paolo Bonzini wrote:
Currently, the website is rebuilt on qemu-project.org using
an update hook. We can reuse instead the Jekyll output of
GitLab's CI.
To do so, a new user qemu-deploy has been created on qemu.org.
The private key is s
Philippe Mathieu-Daudé writes:
> Hi Alex,
>
> On Fri, Jan 15, 2021 at 2:08 PM Alex Bennée wrote:
>>
>> For prettier output.
>>
>> Signed-off-by: Alex Bennée
>> Reviewed-by: Willian Rampazzo
>> Reviewed-by: Philippe Mathieu-Daudé
>> Message-Id: <20210114165730.31607-6-alex.ben...@linaro.org>
On 19/01/21 10:53, Daniel P. Berrangé wrote:
On Tue, Jan 19, 2021 at 10:37:46AM +0100, Paolo Bonzini wrote:
Currently, the website is rebuilt on qemu-project.org using
an update hook. We can reuse instead the Jekyll output of
GitLab's CI.
Are there any files present on the qemu-project.org we
From: Klaus Jensen
Use the correct field names.
Reviewed-by: Minwoo Im
Signed-off-by: Klaus Jensen
---
include/block/nvme.h | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/include/block/nvme.h b/include/block/nvme.h
index 86d7fc2f905c..f3cbe17d0971 100644
From: Klaus Jensen
This is a resend of "hw/block/nvme: allow cmb and pmr to coexist" with
some more PMR work added (PMR RDS/WDS support).
This includes a resurrection of Andrzej's series[1] from back July.
Andrzej's main patch basically moved the CMB from BAR 2 into an offset
in BAR 4 (located
From: Klaus Jensen
Add the size of the mmio read/write to the trace event.
Signed-off-by: Klaus Jensen
Reviewed-by: Minwoo Im
---
hw/block/nvme.c | 4 ++--
hw/block/trace-events | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
in
From: Andrzej Jakowski
This patch sets CMBS bit in controller capabilities register when user
configures NVMe driver with CMB support, so capabilites are correctly
reported to guest OS.
Signed-off-by: Andrzej Jakowski
Reviewed-by: Maxim Levitsky
Reviewed-by: Minwoo Im
Signed-off-by: Klaus Jen
From: Klaus Jensen
64 bit registers like ASQ and ACQ should be writable by both a hi/lo 32
bit write combination as well as a plain 64 bit write. The spec does not
define ordering on the hi/lo split, but the code currently assumes that
the low order bits are written first. Additionally, the code
From: Klaus Jensen
With BAR 4 now free to use, allow PMR and CMB to be enabled
simultaneously.
Reviewed-by: Minwoo Im
Signed-off-by: Klaus Jensen
---
hw/block/nvme.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 6
From: Klaus Jensen
In the interest of supporting both CMB and PMR to be enabled on the same
device, move the MSI-X table and pending bit array out of BAR 4 and into
BAR 0.
This is a simplified version of the patch contributed by Andrzej
Jakowski (see [1]). Leaving the CMB at offset 0 removes the
From: Klaus Jensen
The PMR should not be enabled at boot up. Disable the PMR MemoryRegion
initially and implement MMIO for PMRCTL, allowing the host to enable the
PMR explicitly.
Signed-off-by: Klaus Jensen
---
hw/block/nvme.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(
From: Klaus Jensen
The controller registers are initially zero. Remove the redundant
zeroing.
Signed-off-by: Klaus Jensen
---
hw/block/nvme.c | 34 --
1 file changed, 34 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index e4fb89c88e23..85b6617a0ce
From: Padmakar Kalghatgi
Implement v1.4 logic for configuring the Controller Memory Buffer. This
is not backward compatible with v1.3, so drivers that only support v1.3
will not be able to use the CMB anymore.
Signed-off-by: Padmakar Kalghatgi
Signed-off-by: Klaus Jensen
---
hw/block/nvme.h
From: Naveen Nagar
Add support for the PMRMSCL and PMRMSCU MMIO registers. This allows
adding RDS/WDS support for PMR as well.
Signed-off-by: Naveen Nagar
Signed-off-by: Klaus Jensen
---
hw/block/nvme.h | 6 ++-
include/block/nvme.h | 1 +
hw/block/nvme.c | 122 +
Eduardo Habkost writes:
> On Thu, Jan 14, 2021 at 02:39:35PM +0100, Markus Armbruster wrote:
>> John Snow writes:
>>
>> > On 1/13/21 10:39 AM, Markus Armbruster wrote:
>> >> Spelling nitpick: s/builtin/built-in/ in the title.
>> >>
>> >
>> > Sure.
>> >
>> >> John Snow writes:
>> >>
>> >>> We
From: Klaus Jensen
The controller now implements v1.4 and we can lift the restrictions on
CMB Data Pointer and Command Independent Locations Support (CDPCILS) and
CMB Data Pointer Mixed Locations Support (CDPMLS) since the device
really does not care about mixed host/cmb pointers in those cases.
From: Klaus Jensen
With the new CMB logic in place, bump the implemented specification
version to v1.4 by default.
This requires adding the setting the CNTRLTYPE field and modifying the
VWC field since 0x00 is no longer a valid value for bits 2:1.
Signed-off-by: Klaus Jensen
---
include/block
On 19/01/2021 11.00, Paolo Bonzini wrote:
On 19/01/21 10:58, Thomas Huth wrote:
On 19/01/2021 10.37, Paolo Bonzini wrote:
Currently, the website is rebuilt on qemu-project.org using
an update hook. We can reuse instead the Jekyll output of
GitLab's CI.
To do so, a new user qemu-deploy has bee
Currently, the website is rebuilt on qemu-project.org using
an update hook. We can reuse instead the Jekyll output of
GitLab's CI.
To do so, a new user qemu-deploy has been created on qemu.org.
The private key is stored into a file variable SSH_PRIVATE_KEY_FILE
(be careful to include the trailing
Hello all,
When testing with the ZNS code that is in nvme-next,
I can zone append, targeting the first zone by specifying zslba 0,
and then just put that call it in a while loop, it will
manage to fill up not just zone0, but the whole drive.
Since zslba is defined as:
"Zone Start Logical Block A
On Mon, 11 Jan 2021 at 23:57, Richard Henderson
wrote:
>
> The architected pauth algorithm is quite slow without
> hardware support, and boot times for kernels that enable
> use of the feature have been significantly impacted.
>
> Version 7 changes:
> * Fix rebase error (drjones).
>
> Version 6
The qemu-web.git repository on git.qemu.org is now a mirror of gitlab.
The git mirror is updated every 15 minutes.
Pushing new changes to qemu.org therefore must now be done via
g...@gitlab.org:qemu-project/qemu-web.git. The GitLab qemu-project
organization is configured so that CI/CD jobs fo
On 19/01/2021 11.43, Paolo Bonzini wrote:
The qemu-web.git repository on git.qemu.org is now a mirror of gitlab. The
git mirror is updated every 15 minutes.
Pushing new changes to qemu.org therefore must now be done via
g...@gitlab.org:qemu-project/qemu-web.git.
I think that should be gitlab.c
On Tue, Jan 19, 2021 at 11:15:49AM +0100, Paolo Bonzini wrote:
> Currently, the website is rebuilt on qemu-project.org using
> an update hook. We can reuse instead the Jekyll output of
> GitLab's CI.
>
> To do so, a new user qemu-deploy has been created on qemu.org.
> The private key is stored in
On 19/01/21 11:49, Thomas Huth wrote:
On 19/01/2021 11.43, Paolo Bonzini wrote:
The qemu-web.git repository on git.qemu.org is now a mirror of gitlab.
The git mirror is updated every 15 minutes.
Pushing new changes to qemu.org therefore must now be done via
g...@gitlab.org:qemu-project/qemu-w
On Tue, 12 Jan 2021 at 10:59, Rémi Denis-Courmont
wrote:
>
> Hi,
>
> This adds Secure EL2.
>
> Changes since version 4:
> - Fix NS unitialised in secure state stage 2 translation.
> - Remove EEL2 translation block flag in 32-bit mode.
> - Clarify comments on arm_is_el2_enabled().
Looking
On 27/10/2020 14.20, Daniel P. Berrangé wrote:
When the browser window is narrow, but not yet switched into the mobile
layout, the page header nav will line wrap. This breaks layout
assumptions resulting in overlapping/obscured text.
This deals with the probem by reducing padding between the lin
On Jan 19 10:38, Niklas Cassel wrote:
> Hello all,
>
>
> When testing with the ZNS code that is in nvme-next,
> I can zone append, targeting the first zone by specifying zslba 0,
> and then just put that call it in a while loop, it will
> manage to fill up not just zone0, but the whole drive.
>
Philippe Mathieu-Daudé writes:
> Fix a variable rename mistake from commit 5e33f7fead5:
>
> Traceback (most recent call last):
> File "./tests/docker/docker.py", line 710, in
> sys.exit(main())
> File "./tests/docker/docker.py", line 706, in main
> return args.cmdobj.run(
Philippe Mathieu-Daudé writes:
> To have the variable properly passed, we need to set it,
> ie. NOUSER=1. Fix the message displayed by 'make docker'.
>
> Signed-off-by: Philippe Mathieu-Daudé
Queued to testing/next, thanks.
> ---
> tests/docker/Makefile.include | 2 +-
> 1 file changed, 1 i
On Wed, 13 Jan 2021 at 06:26, Richard Henderson
wrote:
>
> There was an inconsistency between encoding, which uses
> SIMD_DATA_SHIFT, and decoding which used SIMD_OPRSZ_BITS.
> This happened to be ok, until e2e7168a214, which reduced
> the size of SIMD_OPRSZ_BITS, which lead to truncating all
> pr
Philippe Mathieu-Daudé writes:
> When using the Docker engine, build fails because the container is
> unable to resolve hostnames:
>
> $ make docker-image-debian-s390x-cross NETWORK=host ENGINE=docker
> BUILD debian10
> #6 9.679 Err:1 http://deb.debian.org/debian buster InRelease
>
Peter Maydell writes:
> On Fri, 15 Jan 2021 at 15:45, Markus Armbruster wrote:
>>
>> The .realize() method realizes the child at (1). It should use
>> qdev_realize() like we do everywhere else, since commit ce189ab230
>> "qdev: Convert bus-less devices to qdev_realize() with Coccinelle".
>>
>>
On Fri, 15 Jan 2021 at 10:11, Maxim Uvarov wrote:
>
> Implement gpio-pwr driver to allow reboot and poweroff machine.
> This is simple driver with just 2 gpios lines. Current use case
> is to reboot and poweroff virt machine in secure mode. Secure
> pl066 gpio chip is needed for that.
>
> Signed-o
On Fri, 15 Jan 2021 at 10:11, Maxim Uvarov wrote:
>
> No functional change. Just refactor code to better
> support secure and normal world gpios.
>
> Signed-off-by: Maxim Uvarov
> ---
> @@ -847,21 +873,22 @@ static void create_gpio(const VirtMachineState *vms)
> qemu_fdt_setprop_string(vms-
On Mon 18 Jan 2021 11:15:17 AM CET, Vladimir Sementsov-Ogievskiy wrote:
>> +static int bdrv_reopen_parse_file(BDRVReopenState *reopen_state,
>> + GSList **tran,
>> + Error **errp)
>> +{
>> +BlockDriverState *bs = reopen_state->bs
On 18/01/2021 16.12, Thomas Huth wrote:
On 18/01/2021 15.50, Daniel P. Berrangé wrote:
On Mon, Jan 18, 2021 at 03:44:49PM +0100, Thomas Huth wrote:
On 18/01/2021 14.37, Jiaxun Yang wrote:
On Mon, Jan 18, 2021, at 6:11 PM, Daniel P. Berrangé wrote:
On Mon, Jan 18, 2021 at 02:38:08PM +0800, J
00)
>
> are available in the Git repository at:
>
> https://gitlab.com/dgibson/qemu.git tags/ppc-for-6.0-20210119
>
> for you to fetch changes up to 2a05350e90ba09b6f42f5cff81f4aa7580a998be:
>
> spapr_cpu_core.c: use g_auto*
The qemu.git repository on git.qemu.org is now a mirror of gitlab. The
git mirror is updated every 15 minutes.
New changes to qemu.git therefore must go through
g...@gitlab.com:qemu-project/qemu.git.
As a result, the "qemu" and "qemu-stable" groups on the qemu.org server
do not exist anymore
Device code shouldn't mess with QOM property "realized" since we have
proper interfaces (merge commit 6675a653). Commit 8ddab8dd3d
"usb/hcd-xhci: Split pci wrapper for xhci base model" and commit
f00ff136ee "usb: hcd-xhci-sysbus: Attach xhci to sysbus device"
reintroduced two instances. Clean the
On 13/01/21 15:57, Daniel P. Berrangé wrote:
On Wed, Jan 13, 2021 at 03:54:51PM +0100, Paolo Bonzini wrote:
I am going to apply patches 1-3, so that I can play with doing the
final deployment via gitlab pipelines.
Probably worth taking the 16th patch too, since the CONTRIBUTING
file described
On Tue, Jan 12, 2021 at 10:07:35PM -0800, Hill Ma wrote:
> This prevents illegal instruction on cpus do not support xgetbv.
>
> Buglink: https://bugs.launchpad.net/qemu/+bug/1758819
> Signed-off-by: Hill Ma
> ---
> v3: addressed feedback.
> v2: xgetbv() modified based on feedback.
>
> target/i3
On Tue, Jan 19, 2021 at 8:01 PM Paolo Bonzini wrote:
>
> The qemu.git repository on git.qemu.org is now a mirror of gitlab. The
> git mirror is updated every 15 minutes.
>
> New changes to qemu.git therefore must go through
> g...@gitlab.com:qemu-project/qemu.git.
>
> As a result, the "qemu" and "
Am 18.01.2021 um 17:30 hat Paolo Bonzini geschrieben:
> Looking at all merge-lists QemuOptsList, here is how they access their
> QemuOpts:
>
> reopen_opts in qemu-io-cmds.c ("qemu-img reopen -o")
> qemu_opts_find(&reopen_opts, NULL)
>
> empty_opts in qemu-io.c ("qemu-io open -o")
> qe
When management applications (like Libvirt) want to check whether
memory-backend-file.pmem is supported they can list object
properties using 'qom-list-properties'. However, 'pmem' is
declared always (and thus reported always) and only at runtime
QEMU errors out if it was built without libpmem (and
Sometimes interrupt event comes at the same time with
the virtual timers. In this case replay tries to proceed
the timers, because deadline for them is zero.
This patch allows processing interrupts and exceptions
by entering the vCPU execution loop, when deadline is zero,
but checkpoint associated
On 21-01-19 11:15:02, Klaus Jensen wrote:
> From: Padmakar Kalghatgi
>
> Implement v1.4 logic for configuring the Controller Memory Buffer. This
> is not backward compatible with v1.3, so drivers that only support v1.3
> will not be able to use the CMB anymore.
Reviewed the legacy-cmb paramete,
On Jan 19 21:44, Minwoo Im wrote:
> On 21-01-19 11:15:02, Klaus Jensen wrote:
> > From: Padmakar Kalghatgi
> >
> > Implement v1.4 logic for configuring the Controller Memory Buffer. This
> > is not backward compatible with v1.3, so drivers that only support v1.3
> > will not be able to use the CM
Hi Bin,
On [2021 Jan 18] Mon 20:32:19, Bin Meng wrote:
> Hi Francisco,
>
> On Mon, Jan 18, 2021 at 6:06 PM Francisco Iglesias
> wrote:
> >
> > Hi Bin,
> >
> > On [2021 Jan 15] Fri 22:38:18, Bin Meng wrote:
> > > Hi Francisco,
> > >
> > > On Fri, Jan 15, 2021 at 8:26 PM Francisco Iglesias
> > >
This patch adds support to toggle the accuracy in m25p80 between dummy
clock cycle to dummy byte. By being able to do this the SPI controllers
transfering through a txfifo will be able to support commands with dummy
clock cycles.
Signed-off-by: Francisco Iglesias
---
hw/block/m25p80.c | 112
Dear all,
This small RFC patch series attempts to make it possible to support the
SPI commands requiring dummy clock cycles in the SPI controllers that
currently do not support them.
There are two ways SPI controllers transfer dummy clock cycles. In one way
the dummy clock cycles to be used with
This patch introduces ssi_txfifo_transfer aimed to be used by SPI
controllers transfering through a txfifo. When interacting with a SPI
flash (m25p80), ssi_txfifo_transfer will toggle the accuracy from dummy
clock cycles to dummy bytes and by doing this above mentioned SPI
controllers will obtain s
This patch changes the SPI controller to use the ssi_txfifo_transfer for
being able to support SPI flash commands requiring dummy clock cycles.
Signed-off-by: Francisco Iglesias
---
hw/ssi/xilinx_spi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ssi/xilinx_spi.c b/hw/s
On 1/19/21 6:50 AM, Greg Kurz wrote:
On Mon, 18 Jan 2021 16:30:35 -0300
Daniel Henrique Barboza wrote:
Commit 47c8c915b162 fixed a problem where multiple spapr_drc_detach()
requests were breaking QEMU. The solution was to just spapr_drc_detach()
once, and use spapr_drc_unplug_requested() to
On Fri, 15 Jan 2021 at 10:11, Maxim Uvarov wrote:
>
> Add secure pl061 for reset/power down machine from
> the secure world (Arm Trusted Firmware). Connect it
> with gpio-pwr driver.
>
> Signed-off-by: Maxim Uvarov
> ---
> hw/arm/Kconfig| 1 +
> hw/arm/virt.c | 50 ++
On Fri, 15 Jan 2021 at 19:21, Mihai Carabas wrote:
>
> To ease the PCI device addition in next patches, split the code as follows:
> - generic code (read/write/setup) is being kept in pvpanic.c
> - ISA dependent code moved to pvpanic-isa.c
>
> Also, rename:
> - ISA_PVPANIC_DEVICE -> PVPANIC_ISA_DE
On Fri, 15 Jan 2021 at 19:23, Mihai Carabas wrote:
>
> Add a test case for pvpanic-pci device. The scenario is the same as pvpapnic
"pvpanic"
> ISA device, but is using the PCI bus.
>
> Signed-off-by: Mihai Carabas
Otherwise
Reviewed-by: Peter Maydell
thanks
-- PMM
On Fri, 15 Jan 2021 at 19:23, Mihai Carabas wrote:
>
> Add PCI interface support for PVPANIC device. Create a new file pvpanic-pci.c
> where the PCI specific routines reside and update the build system with the
> new
> files and config structure.
>
> Signed-off-by: Mihai Carabas
Reviewed-by: Pe
On 01/19/21 13:25, Bin Meng wrote:
> On Tue, Jan 19, 2021 at 8:01 PM Paolo Bonzini wrote:
>>
>> The qemu.git repository on git.qemu.org is now a mirror of gitlab. The
>> git mirror is updated every 15 minutes.
>>
>> New changes to qemu.git therefore must go through
>> g...@gitlab.com:qemu-project/
On Fri, 15 Jan 2021 at 19:23, Mihai Carabas wrote:
>
> Add pvpanic PCI device support details in docs/specs/pvpanic.txt.
>
> Signed-off-by: Mihai Carabas
> ---
> docs/specs/pvpanic.txt | 13 -
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/docs/specs/pvpanic.txt b
Currently, the website is rebuilt on qemu-project.org using
a separate container (https://github.com/stefanha/qemu-docs/)
cron job hook. We can instead reuse the GitLab's CI artifacts.
To do so, we use the same mechanism that is already in place for
qemu-web.git.
Signed-off-by: Paolo Bonzini
--
On Fri, 15 Jan 2021 at 19:21, Mihai Carabas wrote:
>
> This patchset adds support for pvpanic pci device.
>
> v3 applied feedback:
>
> - patch 1: made pvpanic isa device available only for PC, compile pvpanic-test
> only when isa device is present
>
> - patch 2: fixed device id to 0x0011, used O
On Sun, 17 Jan 2021 at 19:25, Philippe Mathieu-Daudé wrote:
>
> Add vmstate_qdev_no_state_to_migrate, which is simply a
> pointer to vmstate_no_state_to_migrate. This way all
> qdev devices (including "hw/qdev-core.h") don't have to
> include "migration/vmstate.h".
>
> Signed-off-by: Philippe Math
On 19/01/21 13:25, Bin Meng wrote:
I see the following error in a previously cloned repo:
$ git fetch origin
fatal: remote error: access denied or repository not exported: /qemu.git
$ git remote -v
origin git://git.qemu.org/qemu.git (fetch)
origin git://git.qemu.org/qemu.git (push)
Is this e
On Montag, 18. Januar 2021 15:22:59 CET Greg Kurz wrote:
> The fid_list is currently open-coded. This doesn't seem to serve any
> purpose that cannot be met with QEMU's generic lists. Let's go for a
> QSIMPLEQ : this will allow to add new fids at the end of the list and
> to improve the logic in v9
Hi Alex,
after updating to latest master today, I am getting the following error with
make check-tcg
qemu-system-aarch64: -gdb
unix:path=/tmp/tmp9ru5tgk8qemu-gdbstub/gdbstub.socket,server: info: QEMU
waiting for connection on:
disconnected:unix:/tmp/tmp9ru5tgk8qemu-gdbstub/gdbstub.socket,serv
From: Philippe Mathieu-Daudé
'burst_length' is cleared in imx_spi_reset(), which is called
after imx_spi_realize(). Remove the initialization to simplify.
Reviewed-by: Juan Quintela
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210115153049.3353008-3-f4...@amsat.org>
Reviewed-by: Bin Me
From: Philippe Mathieu-Daudé
When the block is disabled, all registers are reset with the
exception of the ECSPI_CONREG. It is initialized to zero
when the instance is created.
Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM),
chapter 21.7.3: Control Register (ECSPIx_CONREG)
From: Bin Meng
This v8 series is based on the following 2 versions:
- v5 series sent from Bin
http://patchwork.ozlabs.org/project/qemu-devel/list/?series=223919
- v7 series sent from Philippe
http://patchwork.ozlabs.org/project/qemu-devel/list/?series=224612
This series fixes a bunch of bug
From: Bin Meng
Usually the approach is that the device on the other end of the line
is going to reset its state anyway, so there's no need to actively
signal an irq line change during the reset hook.
Move imx_spi_update_irq() out of imx_spi_reset(), to a new function
imx_spi_soft_reset() that is
From: Xuzhou Cheng
When a write to ECSPI_CONREG register to disable the SPI controller,
imx_spi_reset() is called to reset the controller, but chip select
lines should have been disabled, otherwise the state machine of any
devices (e.g.: SPI flashes) connected to the SPI master is stuck to
its la
On 1/19/21 12:27 PM, Alex Bennée wrote:
> Philippe Mathieu-Daudé writes:
>
>> When using the Docker engine, build fails because the container is
>> unable to resolve hostnames:
>>
>> $ make docker-image-debian-s390x-cross NETWORK=host ENGINE=docker
>> BUILD debian10
>> #6 9.679 Err:1 ht
From: Philippe Mathieu-Daudé
When the block is disabled, it stay it is 'internal reset logic'
(internal clocks are gated off). Reading any register returns
its reset value. Only update this value if the device is enabled.
Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM),
cha
From: Bin Meng
Avoid using a magic number (4) everywhere for the number of chip
selects supported.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Juan Quintela
---
(no changes since v1)
include/hw/ssi/imx_spi.h | 5 -
hw/ssi/imx_
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