This patch changes the SPI controller to use the ssi_txfifo_transfer for being able to support SPI flash commands requiring dummy clock cycles.
Signed-off-by: Francisco Iglesias <frasse.igles...@gmail.com> --- hw/ssi/xilinx_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c index 49ff275593..ae34cdc436 100644 --- a/hw/ssi/xilinx_spi.c +++ b/hw/ssi/xilinx_spi.c @@ -179,7 +179,7 @@ static void spi_flush_txfifo(XilinxSPI *s) while (!fifo8_is_empty(&s->tx_fifo)) { tx = (uint32_t)fifo8_pop(&s->tx_fifo); DB_PRINT("data tx:%x\n", tx); - rx = ssi_transfer(s->spi, tx); + rx = ssi_txfifo_transfer(s->spi, tx); DB_PRINT("data rx:%x\n", rx); if (fifo8_is_full(&s->rx_fifo)) { s->regs[R_IPISR] |= IRQ_DRR_OVERRUN; -- 2.20.1