From: Philippe Mathieu-Daudé <f4...@amsat.org> When the block is disabled, all registers are reset with the exception of the ECSPI_CONREG. It is initialized to zero when the instance is created.
Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Reviewed-by: Juan Quintela <quint...@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org> Message-Id: <20210115153049.3353008-4-f4...@amsat.org> Reviewed-by: Bin Meng <bin.m...@windriver.com> Signed-off-by: Bin Meng <bin.m...@windriver.com> --- (no changes since v7) Changes in v7: - remove the RFC tag Changes in v6: - new patch: [RFC] rework imx_spi_reset() to keep CONREG register value hw/ssi/imx_spi.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 8fb3c9b..c952a3d 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -231,12 +231,23 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) static void imx_spi_reset(DeviceState *dev) { IMXSPIState *s = IMX_SPI(dev); + int i; DPRINTF("\n"); - memset(s->regs, 0, sizeof(s->regs)); - - s->regs[ECSPI_STATREG] = 0x00000003; + for (i = 0; i < ARRAY_SIZE(s->regs); i++) { + switch (i) { + case ECSPI_CONREG: + /* CONREG is not updated on reset */ + break; + case ECSPI_STATREG: + s->regs[i] = 0x00000003; + break; + default: + s->regs[i] = 0; + break; + } + } imx_spi_rxfifo_reset(s); imx_spi_txfifo_reset(s); -- 2.7.4