Hi,
> - If the get_next() invocation is simple, then style (1) is perfectly fine.
Fully agree. Duplicating a single line is perfectly fine if it is
simple enough that you can hardly get it wrong.
> - Style (2) is the worst of all.
Yes, especially because the break is three lines not two due
On Jul 30 09:48, Peter Maydell wrote:
> On Wed, 29 Jul 2020 at 23:19, Emanuele Giuseppe Esposito
> wrote:
> >
> > pci_dma_rw currently always returns 0, regardless
> > of the result of dma_memory_rw. Adjusted to return
> > the correct value.
> >
> > Signed-off-by: Emanuele Giuseppe Esposito
>
>
On Wed, 12 Aug 2020 16:29:38 -0500
Michael Roth wrote:
> Quoting Tomáš Golembiovský (2020-08-06 04:03:06)
> > The command guest-get-fsinfo can be used to list information about disks and
> > partitions but it is limited only to mounted disks with filesystem. This new
> > command allows listing in
On Thu, 13 Aug 2020 18:25:56 -0400
Eduardo Habkost wrote:
> The macro was incorrectly defined using OBJECT_CHECK.
>
> Signed-off-by: Eduardo Habkost
> ---
> hw/s390x/virtio-ccw.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/s390x/virtio-ccw.h b/hw/s390x/virt
On Thu, 13 Aug 2020 18:26:05 -0400
Eduardo Habkost wrote:
> Move typedef closer to the type check macros, to make it easier
> to convert the code to OBJECT_DEFINE_TYPE() in the future.
>
> Signed-off-by: Eduardo Habkost
> ---
> include/hw/s390x/s390_flic.h | 1 +
> hw/intc/s390_flic_kvm.c
Hi,
> > > +static const uint8_t qemu_wacom_hid_report_descriptor[] = {
> > > + 0x05, 0x01,
> > > + 0x09, 0x02,
> >
> > Where does this come from? Created from scratch? Copied from real
>
> No, there are dump of several descriptor on github. I will put in the
> commit message
A commen
On 16.08.20 16:22, Li Qiang wrote:
> If error occurs while processing the virtio request we should call
> 'virtqueue_detach_element' to detach the element from the virtqueue
> before free the elem.
>
> Signed-off-by: Li Qiang
Fixes: 910b25766b ("virtio-mem: Paravirtualized memory hot(un)plug")
Ping?
On 11.08.2020 16:10, Kamil Rytarowski wrote:
> From: Maxime Villard
>
> Adds support for the NetBSD Virtual Machine Monitor (NVMM) stubs and
> introduces the nvmm.h sysemu API for managing the vcpu scheduling and
> management.
>
> Signed-off-by: Maxime Villard
> Signed-off-by: Kamil Ryta
On 13.08.20 18:29, Kevin Wolf wrote:
> Signed-off-by: Kevin Wolf
> ---
> include/block/nbd.h | 2 --
> nbd/server.c| 5 -
> 2 files changed, 7 deletions(-)
Reviewed-by: Max Reitz
signature.asc
Description: OpenPGP digital signature
On Wed, Jun 24, 2020 at 05:14:22PM +0200, Thomas Huth wrote:
On 14/06/2020 20.39, Coiby Xu wrote:
This test case has the same tests as tests/virtio-blk-test.c except for
tests have block_resize. Since vhost-user server can only server one
client one time, two instances of qemu-storage-daemon are
On Thu, Jun 18, 2020 at 09:28:44AM +0100, Stefan Hajnoczi wrote:
On Tue, Jun 16, 2020 at 02:52:16PM +0800, Coiby Xu wrote:
On Sun, Jun 14, 2020 at 12:16:28PM -0700, no-re...@patchew.org wrote:
> Patchew URL:
https://patchew.org/QEMU/20200614183907.514282-1-coiby...@gmail.com/
>
>
>
> Hi,
>
> Th
On Fri, Jun 19, 2020 at 01:13:00PM +0100, Stefan Hajnoczi wrote:
On Mon, Jun 15, 2020 at 02:39:04AM +0800, Coiby Xu wrote:
+/*
+ * a wrapper for vu_kick_cb
+ *
+ * since aio_dispatch can only pass one user data pointer to the
+ * callback function, pack VuDev and pvt into a struct. Then unpack i
Hi Kamil,
On 8/17/20 9:59 AM, Kamil Rytarowski wrote:
> Ping?
1/ Your series misses a cover letter, see:
https://wiki.qemu.org/Contribute/SubmitAPatch#Include_a_meaningful_cover_letter
(no need to repost though).
2/ Please wait at least 1 week between pings
(except for critical bug fixes in pre-
On 13.08.20 18:29, Kevin Wolf wrote:
> Move all block export related types and commands from block-core to the
> new QAPI module block-export.
>
> Signed-off-by: Kevin Wolf
> ---
> qapi/block-core.json | 166 --
> qapi/block-export.json | 172
From: Frank Chang
This patchset implements the vector extension v1.0 for RISC-V on QEMU.
This patchset is sent as RFC because RVV v1.0 is still in draft state.
v2 patchset was sent for RVV v0.9 and bumped to RVV v1.0 since v3 patchset.
The port is available here:
https://github.com/sifive/qemu/
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 793af990673..43ba272c09b 100644
--- a/target/riscv/
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/cpu.h| 6 ++
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 16 +++-
target/riscv/csr.c| 25 -
4 files
From: Frank Chang
As in RVV 1.0 design, MLEN is hardcoded with value 1 (Section 4.5).
Thus, remove all MLEN related calculations.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.inc.c | 35 +---
target/riscv/internals.h| 9 +-
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 10 +-
target/riscv/cpu.h | 2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 228b9bdb5d
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index a8b3120
From: Frank Chang
Implementations may have a writable misa.v field. Analogous to the way
in which the floating-point unit is handled, the mstatus.vs field may
exist even if misa.v is clear.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/csr.c | 2 +-
1 file changed
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/cpu_bits.h | 7 +++
target/riscv/csr.c | 21 +
2 files changed, 28 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.inc.c | 69 -
target/riscv/translate.c| 33
2 files changed, 90 insertions(+), 12 deletions(-)
diff
From: Frank Chang
* Remove VXRM and VXSAT fields from FCSR register as they are only
presented in VCSR register.
* Remove RVV loose check in fs() predicate function.
Signed-off-by: Frank Chang
---
target/riscv/csr.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/target/ris
From: Frank Chang
Unlike other vector instructions, load/store vector instructions return
the maximum vector size calculated with EMUL.
For other vector instructions, return VLMAX as the maximum vector size.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 57 ++
From: Frank Chang
Replace ETYPE from signed int to unsigned int to prevent index overflow
issue, which would lead to wrong index address.
Signed-off-by: Frank Chang
---
target/riscv/vector_helper.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/vector_
From: Frank Chang
If VS field is off, accessing vector csr registers should raise an
illegal-instruction exception.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/csr.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
From: Greentime Hu
Signed-off-by: Greentime Hu
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 7 +++
2 files changed, 8 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7afdd4814bb..
Hi,I have add QEMU_IFLA_INFO_KIND nested type for sit.But I still can't open
Google browser.
And there are still the following errors:
qemu: uncaught target signal 5 (Trace/breakpoint trap) - core dumped
qemu: uncaught target signal 5 (Trace/breakpoint trap) - core dumped
[1661:1661:0806/074307.5
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index f142aa5d073..a800c989050 100644
--- a/target/riscv/insn32
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 27 +++-
target/riscv/insn32.decode | 14 +++
target/riscv/insn_trans/trans_rvv.inc.c | 31 --
target/riscv/vector_helper.c| 56 +
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 2 +-
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.inc.c | 7 ---
target/riscv/vector_helper.c| 6 +++---
4 files chang
From: Frank Chang
Introduce the concepts of fractional LMUL for RVV 1.0.
In RVV 1.0, LMUL bits are contiguous in vtype register.
Signed-off-by: Frank Chang
---
target/riscv/cpu.h | 15 ---
target/riscv/translate.c | 16 ++--
target/riscv/vector_helper.c |
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 100 +++---
target/riscv/insn32-64.decode | 18 +-
target/riscv/insn32.decode | 36 +++-
target/riscv/insn_trans/trans_rvv.inc.c | 220 ++
target/riscv/vec
From: Frank Chang
* Add fp16 nan-box check generator function, if a 16-bit input is not
properly nanboxed, then the input is replaced with the default qnan.
* Add do_nanbox() helper function to utilize gen_check_nanbox_X() to
generate the NaN-boxed floating-point values based on SEW setting.
From: Frank Chang
* Remove "vmv.s.x: dothing if rs1 == 0" constraint.
* Add vmv.x.s instruction.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvv.inc.c | 45 -
2 files chang
From: Frank Chang
Add the following instructions:
* vzext.vf2
* vzext.vf4
* vzext.vf8
* vsext.vf2
* vsext.vf4
* vsext.vf8
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 14
target/riscv/insn32.decode | 8 +++
target/
From: Frank Chang
Immediate value in translator function is extended not only
zero-extended and sign-extended but with more modes to be applicable
with multiple formats of vector instructions.
* IMM_ZX: Zero-extended
* IMM_SX: Sign-extended
* IMM_TRUNC_SEW: Truncate to log(SEW)
From: Frank Chang
Add the following instructions:
* vlre.v
* vsr.v
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 21
target/riscv/insn32.decode | 22
target/riscv/insn_trans/trans_rvv.inc.c | 72 +
target/riscv/
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.inc.c | 12
target/riscv/vector_helper.c| 14 +-
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_
From: Frank Chang
Add the following instructions:
* vaaddu.vv
* vaaddu.vx
* vasubu.vv
* vasubu.vx
Remove the following instructions:
* vadd.vi
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 16 ++
target/riscv/insn32.decode | 13 +++--
target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 7a10fc27c5f..15afc469cb0 100644
--- a/target/riscv/insn32
From: Frank Chang
Update check functions with RVV 1.0 rules.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 708
1 file changed, 476 insertions(+), 232 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_tra
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 129 +++---
target/riscv/insn32.decode | 43 +++--
target/riscv/insn_trans/trans_rvv.inc.c | 221 +++-
target/riscv/vector_helper.c| 188 ++---
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 67
target/riscv/insn32.decode | 21 ++-
target/riscv/insn_trans/trans_rvv.inc.c | 193
target/riscv/vector_helper.c| 89 ++-
4 files
From: Frank Chang
Add the following instructions:
* vqmaccu.vv
* vqmaccu.vx
* vqmacc.vv
* vqmacc.vx
* vqmaccsu.vv
* vqmaccsu.vx
* vqmaccus.vx
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 15
target/riscv/insn32.decode | 7 ++
target/riscv/insn_
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 24 ++--
target/riscv/insn32.decode | 12 +-
target/riscv/insn_trans/trans_rvv.inc.c | 30 -
target/riscv/vecto
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 2 +-
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.inc.c | 4 ++--
target/riscv/vector_helper.c| 6 +++---
4 files changed,
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 6 +++---
target/riscv/insn_trans/trans_rvv.inc.c | 5 -
target/riscv/vector_helper.c| 4
3 files changed, 7 insertions(+), 8 deletions(-)
diff --git
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/vector_helper.c | 8
1 file changed, 8 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index e6441f18465..766622d3878 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c4fe9767585..2e305d492d8 100644
--- a/target/riscv/
From: Frank Chang
Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into
calculation for RVV 1.0.
Signed-off-by: Frank Chang
---
target/riscv/cpu.h | 43 ++---
target/riscv/insn_trans/trans_rvv.inc.c | 12 ++-
2 files changed, 42 insertion
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c99575d1360..f142aa5d073 100644
--- a/target/riscv/insn32
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/translate.c | 2 ++
3 files changed, 4 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 085381fee00..8844975bf94 100644
--- a/target/riscv/cpu.c
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 3 ++-
target/riscv/vector_helper.c| 4
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
i
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0992d6ac86d..7a10fc27c5f 100644
--- a/target/riscv/insn32
From: Frank Chang
Add the following instructions:
* vfslide1up.vf
* vfslide1down.vf
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 7 ++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.inc.c | 4 +
target/riscv/vector_helper.c
From: Frank Chang
Sign-extend vsaddu.vi immediate value.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 809280f4c
From: Frank Chang
For some vector instructions (e.g. vmv.s.x), the element is loaded with
sign-extended.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.inc.c | 32 +
1 file changed, 22 insertions(+), 10 deletions(-)
dif
From: Frank Chang
* Add vrgatherei16.vv instruction.
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 4
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 21 +++--
target/riscv/vector_helper.c| 2
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 24 ++--
target/riscv/insn32.decode | 12 +++---
target/riscv/insn_trans/trans_rvv.inc.c | 12 +++---
target/riscv/vector_helper.c| 52
From: Frank Chang
NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/risc
From: Frank Chang
* Sign-extend vmselu.vi and vmsgtu.vi immediate values.
* Remove "set tail elements to zeros" as tail elements can be unchanged
for either VTA to have undisturbed or agnostic setting.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 4 ++--
target/ri
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 41a60cf2fb9..2ebe2373237 100644
--- a/target/risc
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 19 ---
1 file changed, 19 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index f80c13b0857..e6441f18465 100644
--- a/target/ri
From: Frank Chang
NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 4 +--
target/riscv/insn_trans/trans_rvv.inc.c | 42 ++---
2 files changed, 25 insertions(+), 21 deletions(-)
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 6 --
target/riscv/insn32.decode | 2 --
target/riscv/insn_trans/trans_rvv.inc.c | 2 --
target/riscv/vector_helper.c| 13 -
4 f
From: Frank Chang
* Remove clear function from helper functions as the tail elements
are unchanged in RVV 1.0.
Signed-off-by: Frank Chang
---
target/riscv/vector_helper.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/target/riscv/vector_helper.c b/t
From: Frank Chang
Add the following instructions:
* vmv1r.v
* vmv2r.v
* vmv4r.v
* vmv8r.v
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 4
target/riscv/insn_trans/trans_rvv.inc.c | 25 +
2 files changed, 29 insertions(+)
diff --git a/t
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 1 -
target/riscv/insn_trans/trans_rvv.inc.c | 23 ---
2 files changed, 24 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.
From: Frank Chang
log(SEW) truncate vssra.vi immediate value.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index
From: Frank Chang
Add the following instructions:
* vfcvt.rtz.xu.f.v
* vfcvt.rtz.x.f.v
Also adjust GEN_OPFV_TRANS() to accept multiple floating-point rounding
modes.
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 6 ++
target/riscv/insn32.decode |
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/fpu_helper.c | 12 ++--
target/riscv/insn_trans/trans_rvv.inc.c | 18 +-
target/riscv/internals.h| 9 +
3 files changed, 24 insertions(+), 15 deletions(-)
diff --git a/t
From: Frank Chang
Clear tail elements only if VTA is agnostic.
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 20 ++--
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
target/riscv/vector_helper.c| 14 --
3 files changed, 15 ins
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 22 ---
target/riscv/insn32.decode | 7 -
target/riscv/insn_trans/trans_rvv.inc.c | 9 --
target/riscv/vector_helper.c| 205 --
From: Frank Chang
Add the following instructions:
* vfwcvt.rtz.xu.f.v
* vfwcvt.rtz.x.f.v
Also adjust GEN_OPFV_WIDEN_TRANS() to accept multiple floating-point
rounding modes.
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 6 +++
target/riscv/insn32.decode
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/vector_helper.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 600d2b53353..4d9a1cf3651 100644
--- a/target/riscv/vecto
From: Frank Chang
Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.inc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/tra
From: Frank Chang
helper_set_rounding_mode() is responsible for SIGILL, and "round to odd"
should be an interface private to translation, so add a new independent
helper_set_rod_rounding_mode().
Signed-off-by: Frank Chang
---
target/riscv/fpu_helper.c | 5 +
target/riscv/helper.h | 1 +
From: Greentime Hu
This patch adds vector support for rv32 gdb. It allows gdb client to access
vector registers correctly.
Signed-off-by: Greentime Hu
Signed-off-by: Frank Chang
---
gdb-xml/riscv-32bit-csr.xml | 7 +++
1 file changed, 7 insertions(+)
diff --git a/gdb-xml/riscv-32bit-csr.
Hi,
> > --- a/drivers/gpu/drm/virtio/virtgpu_display.c
> > +++ b/drivers/gpu/drm/virtio/virtgpu_display.c
> > @@ -100,6 +100,7 @@ static void virtio_gpu_crtc_atomic_enable(struct
> > drm_crtc *crtc,
> > struct virtio_gpu_output *output = drm_crtc_to_virtio_gpu_output(crtc);
> >
> > outp
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 30 ++
target/riscv/insn32.decode | 15 +++--
target/riscv/insn_trans/trans_rvv.inc.c | 51 ++---
target/riscv/vector_helper.c| 76 ++---
4
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/vector_helper.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 15a646af361..00743cbce34 100644
--- a/target/riscv/vector_helper.c
+++
Hi all!
Here is a filter, which does preallocation on write.
In Virtuozzo we have to deal with some custom distributed storage
solution, where allocation is relatively expensive operation. We have to
workaround it in Qemu, so here is a new filter.
Patches 1-10 introduces the new filter and sugge
On Fri, Aug 14, 2020 at 12:02:39PM -0400, Pan Nengyuan wrote:
> local_err is not initialized to NULL, it will cause a assert error as below:
> qemu/util/error.c:59: error_setv: Assertion `*errp == NULL' failed.
>
> Fixes: c6447510690
> Reported-by: Euler Robot
> Signed-off-by: Pan Nengyuan
> ---
From: Hsiangkai Wang
Signed-off-by: Hsiangkai Wang
Signed-off-by: Frank Chang
---
gdb-xml/riscv-32bit-csr.xml | 11 ++-
gdb-xml/riscv-64bit-csr.xml | 11 ++-
target/riscv/gdbstub.c | 4 ++--
3 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/gdb-xml/riscv-32
On Thu, Jun 18, 2020 at 03:29:26PM +0200, Kevin Wolf wrote:
Am 14.06.2020 um 20:39 hat Coiby Xu geschrieben:
Sharing QEMU devices via vhost-user protocol.
Only one vhost-user client can connect to the server one time.
Signed-off-by: Coiby Xu
---
util/Makefile.objs | 1 +
util/vhost-u
The comments states, that on misaligned request we should have already
been waiting. But for bdrv_padding_rmw_read, we called
bdrv_mark_request_serialising with align = request_alignment, and now
we serialise with align = cluster_size. So we may have to wait again
with larger alignment.
Note, that
From: Frank Chang
As GVEC only supports MAXSZ and OPRSZ in the range of: [8..256] bytes
and LMUL could be a fractional number. The maximum vector size can be
operated might be less than 8 bytes or larger than 256 bytes.
Skip to use GVEC if maximum vector size <= 8 or >= 256 bytes.
Signed-off-by:
On Fri, Aug 14, 2020 at 10:28:34AM +0200, Philippe Mathieu-Daudé wrote:
> Trivial block patches:
> - Fix a typo
> - Replace '1 << 30' by '1 * GiB' in null-co
> - Replace 512 by BDRV_SECTOR_SIZE when appropriate.
>
> Philippe Mathieu-Daudé (7):
> block/null: Make more explicit the driver defaul
From: Hsiangkai Wang
Signed-off-by: Hsiangkai Wang
Signed-off-by: Frank Chang
---
gdb-xml/riscv-64bit-csr.xml | 7 ++
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 25 +++
target/riscv/gdbstub.c | 126 +++-
4 files changed, 157 i
On 13.08.20 18:29, Kevin Wolf wrote:
> The name BlockExport will be used for the struct containing the runtime
> state of block exports, so change the name of export creation options.
>
> Signed-off-by: Kevin Wolf
> ---
> qapi/block-export.json | 12 ++--
> block/monitor/block-hm
Add flag to make serialising request no wait: if there are conflicting
requests, just return error immediately. It's will be used in upcoming
preallocate filter.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/block/block.h | 9 -
block/io.c| 13 -
2 file
1. BDRV_REQ_NO_SERIALISING doesn't exist already, don't mention it.
2. We are going to add one more user of BDRV_REQ_SERIALISING, so
comment about backup becomes a bit confusing here. The use case in
backup is documented in block/backup.c, so let's just drop
duplication here.
3. The fact
To be reused in separate.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/io.c | 71 +++---
1 file changed, 41 insertions(+), 30 deletions(-)
diff --git a/block/io.c b/block/io.c
index b18680a842..5b96715058 100644
--- a/block/io.c
+++ b/blo
It's intended to be inserted between format and protocol nodes to
preallocate additional space (expanding protocol file) on writes
crossing EOF. It improves performance for file-systems with slow
allocation.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
docs/system/qemu-block-drivers.rst.inc |
bs is linked in req, so no needs to pass it separately. Most of
tracked-requests API doesn't have bs argument. Actually, after this
patch only tracked_request_begin has it, but it's for purpose.
While being here, also add a comment about what "_locked" is.
Signed-off-by: Vladimir Sementsov-Ogievs
Add a function to check, is it a file-posix node on top of file in
FUSE file system.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/block/block.h | 2 ++
block/file-posix.c| 21 +
2 files changed, 23 insertions(+)
diff --git a/include/block/block.h b/include/bl
We'll need a separate function, which will only "mark" request
serialising with specified align but not wait for conflicting
requests. So, it will be like old bdrv_mark_request_serialising(),
before merging bdrv_wait_serialising_requests_locked() into it.
To reduce the possible mess, let's do the
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/298 | 50 ++
tests/qemu-iotests/298.out | 6 +
tests/qemu-iotests/group | 1 +
3 files changed, 57 insertions(+)
create mode 100644 tests/qemu-iotests/298
create mode 100644 tests/
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