Most (by far) crashes end with the same bug check code:
Loading Dump File [\\Lw\arndt\Kanzlei\Mini061612-01.dmp]
BugCheck 3B, {8003, f800016a6700, fa6002c89e60, 0}
Probably caused by : afd.sys ( afd!AfdIssueDeviceControl+18f )
-
Loading Dump File [\\Lw\arndt\Kanzlei\Mini061612-
agrhhh. sha1 of the patch changed after rebasing :)
Added (msi|msix)_(set|get)_message() function for whoever might
want to use them.
Currently msi_notify()/msix_notify() write to these vectors to
signal the guest about an interrupt so the correct values have to
written there by the guest or Q
On Thu, Jun 21, 2012 at 08:02:06AM +1000, Benjamin Herrenschmidt wrote:
> On Wed, 2012-06-20 at 16:40 -0500, Anthony Liguori wrote:
>
> > Well let's return void in the DMA methods and let the IOMMUs assert on
> > error.
> > At least that will avoid surprises until someone decides they care enoug
On 2012-06-21 09:18, Alexey Kardashevskiy wrote:
>
> agrhhh. sha1 of the patch changed after rebasing :)
>
>
>
> Added (msi|msix)_(set|get)_message() function for whoever might
> want to use them.
>
> Currently msi_notify()/msix_notify() write to these vectors to
> signal the guest about an in
On 20 June 2012 23:59, Anthony Liguori wrote:
> On 06/20/2012 05:26 PM, Peter Maydell wrote:
>> On 20 June 2012 22:14, Anthony Liguori wrote:
>> ...for that matter weren't we tossing around the idea of just
>> making target_phys_addr_t 64 bits for everything? (I actually
>> want to do this for ta
Add two interfaces hotplug() and hot_unplug() to scsi bus info.
The embody scsi bus can implement these two interfaces to signal the HBA driver
of guest kernel to add/remove the scsi device in question.
Signed-off-by: Cong Meng
Signed-off-by: Sen Wang
---
hw/scsi-bus.c | 16 +++-
On 06/19/2012 09:58 PM, Blue Swirl wrote:
>>> At least qemu-ifup/down scripts, migration exec and smbd have been
>>> mentioned. Only the system calls made by smbd (for some version of it)
>>> can be known. The user could specify arbitrary commands for the
>>> others, those could be assumed to use s
> + * OpenRISC simulator for use as an ISS.
^^^
Shoudld be IIS?
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.
On Thu, Jun 21, 2012 at 12:58 PM, Jia Liu wrote:
> Add a IIS dummy board.
>
> Signed-off-by: Jia Liu
> ---
> hw/openrisc/Makefile.objs | 2 +-
> hw/openrisc_sim.c | 160
> +
> 2 files changed, 161 insertions(+), 1 deletion(-)
> create mod
On Thu, Jun 21, 2012 at 12:19 PM, 陳韋任 (Wei-Ren Chen)
wrote:
>> + * OpenRISC simulator for use as an ISS.
> ^^^
> Shoudld be IIS?
I guess it stands for Instruction Set Simulator, so rather the subject
should be changed.
--
Thanks.
-- Max
Hello Wei-Ren,
On Thu, Jun 21, 2012 at 4:19 PM, 陳韋任 (Wei-Ren Chen)
wrote:
>> + * OpenRISC simulator for use as an ISS.
>^^^
> Shoudld be IIS?
>
Instruction Set Sim
Instruction Level Sim
What ever, I'll make it more clear :)
> Regards,
> chenwj
>
> --
>
On Thu, Jun 21, 2012 at 8:54 AM, Cong Meng wrote:
> +static int scsi_qdev_unplug(DeviceState *qdev)
> +{
> + SCSIDevice *dev = SCSI_DEVICE(qdev);
> + SCSIBus *bus = scsi_bus_from_device(dev);
> +
> + if (bus->info->hot_unplug)
> + bus->info->hot_unplug(bus, dev);
Please use script
On 06/20/12 14:41, Gerd Hoffmann wrote:
> Commit 4be23939ab0d7019c7e59a37485b416fbbf0f073 makes ehci instantly
> zap any unlinked queue heads when the guest rings the dorbell.
[ ... ]
> Simply not zapping queue heads on doorbell rings fixes the issue, but of
> course
> re-introduces the risk of
On 06/20/2012 03:28 PM, Jan Kiszka wrote:
On 2012-06-20 14:59, Igor Mammedov wrote:
Chain of exception handlers are currently unused feature, drop it
for now to avoid moving prev_debug_excp_handler variable at global
scope when moving tcg initialization into target-i386/cpu.c
Later we probably
On 06/20/2012 03:35 PM, Andreas Färber wrote:
Am 20.06.2012 14:59, schrieb Igor Mammedov:
It's not correct to make CPU runnable (i.e. calling x86_cpu_realize())
when not all properties are set (APIC in this case).
Fix it by calling x86_cpu_realize() at board level after APIC is
initialized, rig
20.06.2012 16:24, Daniel P. Berrange wrote:
delete mode 100644 ui/vnc-jobs-async.c
delete mode 100644 ui/vnc-jobs-sync.c
create mode 100644 ui/vnc-jobs.c
Is there a reason to rename vnc-jobs-foo.c to vnc-jobs.c ?
I'd leave it alone at this stage, omiting just the rename...
/mjt
On Thu, Jun 21, 2012 at 12:57:44PM +0300, Michael Tokarev wrote:
> 20.06.2012 16:24, Daniel P. Berrange wrote:
> > delete mode 100644 ui/vnc-jobs-async.c
> > delete mode 100644 ui/vnc-jobs-sync.c
> > create mode 100644 ui/vnc-jobs.c
>
> Is there a reason to rename vnc-jobs-foo.c to vnc-jobs.c ?
On 20 June 2012 13:41, Gerd Hoffmann wrote:
> Commit 4be23939ab0d7019c7e59a37485b416fbbf0f073 makes ehci instantly
> zap any unlinked queue heads when the guest rings the dorbell.
Should be "doorbell" here and in the Subject, worth fixing up when
you do a next version / pullreq.
-- PMM
Am 21.06.2012 11:43, schrieb Igor Mammedov:
> On 06/20/2012 03:35 PM, Andreas Färber wrote:
>> Am 20.06.2012 14:59, schrieb Igor Mammedov:
>>> It's not correct to make CPU runnable (i.e. calling x86_cpu_realize())
>>> when not all properties are set (APIC in this case).
>>>
>>> Fix it by calling x8
On 06/21/12 11:59, Daniel P. Berrange wrote:
> On Thu, Jun 21, 2012 at 12:57:44PM +0300, Michael Tokarev wrote:
>> 20.06.2012 16:24, Daniel P. Berrange wrote:
>>> delete mode 100644 ui/vnc-jobs-async.c
>>> delete mode 100644 ui/vnc-jobs-sync.c
>>> create mode 100644 ui/vnc-jobs.c
>>
>> Is there
On Thu, Jun 21, 2012 at 6:58 AM, Jia Liu wrote:
> Add OpenRISC instruction tanslation routines.
>
> Signed-off-by: Jia Liu
[...]
> + case 0x0009:
> + switch (op1) {
> + case 0x03: /*l.div*/
> + LOG_DIS("l.div r%d, r%d, r%d\n", rd, ra, rb);
> + {
> +
Am 21.06.2012 12:04, schrieb Peter Maydell:
> On 20 June 2012 13:41, Gerd Hoffmann wrote:
>> Commit 4be23939ab0d7019c7e59a37485b416fbbf0f073 makes ehci instantly
>> zap any unlinked queue heads when the guest rings the dorbell.
>
> Should be "doorbell" here and in the Subject, worth fixing up whe
On 21/06/12 17:39, Jan Kiszka wrote:
> On 2012-06-21 09:18, Alexey Kardashevskiy wrote:
>>
>> agrhhh. sha1 of the patch changed after rebasing :)
>>
>>
>>
>> Added (msi|msix)_(set|get)_message() function for whoever might
>> want to use them.
>>
>> Currently msi_notify()/msix_notify() write to thes
Am 21.06.2012 05:22, schrieb Alexey Kardashevskiy:
> I am trying to compile the very last qemu with vfio_pci enabled. VFIO_PCI is
> added as below:
>
> ./configure:
>
> case "$target_arch2" in
> i386|x86_64|ppc64)
> if test "$vfio_pci" = "yes" -a "$target_softmmu" = "yes" ; then
>
On 2012-06-21 12:28, Alexey Kardashevskiy wrote:
> On 21/06/12 17:39, Jan Kiszka wrote:
>> On 2012-06-21 09:18, Alexey Kardashevskiy wrote:
>>>
>>> agrhhh. sha1 of the patch changed after rebasing :)
>>>
>>>
>>>
>>> Added (msi|msix)_(set|get)_message() function for whoever might
>>> want to use the
On 21/06/12 20:38, Jan Kiszka wrote:
> On 2012-06-21 12:28, Alexey Kardashevskiy wrote:
>> On 21/06/12 17:39, Jan Kiszka wrote:
>>> On 2012-06-21 09:18, Alexey Kardashevskiy wrote:
agrhhh. sha1 of the patch changed after rebasing :)
Added (msi|msix)_(set|get)_message()
On Wed, Jun 20, 2012 at 7:47 AM, Cong Meng wrote:
> Implement the hotplug() and hot_unplug() interfaces in virtio-scsi, by signal
> the virtio_scsi.ko in guest kernel via event virtual queue.
>
> The counterpart patch of virtio_scsi.ko will be sent soon in another thread.
>
> Signed-off-by: Cong M
On 2012-06-21 12:50, Alexey Kardashevskiy wrote:
> On 21/06/12 20:38, Jan Kiszka wrote:
>> On 2012-06-21 12:28, Alexey Kardashevskiy wrote:
>>> On 21/06/12 17:39, Jan Kiszka wrote:
On 2012-06-21 09:18, Alexey Kardashevskiy wrote:
>
> agrhhh. sha1 of the patch changed after rebasing :)
On 21/06/12 20:36, Andreas Färber wrote:
> Am 21.06.2012 05:22, schrieb Alexey Kardashevskiy:
>> I am trying to compile the very last qemu with vfio_pci enabled. VFIO_PCI is
>> added as below:
>>
>> ./configure:
>>
>> case "$target_arch2" in
>> i386|x86_64|ppc64)
>> if test "$vfio_pci" = "
On 06/21/2012 01:27 PM, Andreas Färber wrote:
Am 21.06.2012 12:04, schrieb Peter Maydell:
On 20 June 2012 13:41, Gerd Hoffmann wrote:
Commit 4be23939ab0d7019c7e59a37485b416fbbf0f073 makes ehci instantly
zap any unlinked queue heads when the guest rings the dorbell.
Should be "doorbell" here
Added (msi|msix)_set_message() functions.
Currently msi_notify()/msix_notify() write to these vectors to
signal the guest about an interrupt so the correct values have to
written there by the guest or QEMU.
For example, POWER guest never initializes MSI/MSIX vectors, instead
it uses RTAS hypercal
On 2012-06-21 13:39, Alexey Kardashevskiy wrote:
> Added (msi|msix)_set_message() functions.
>
> Currently msi_notify()/msix_notify() write to these vectors to
> signal the guest about an interrupt so the correct values have to
> written there by the guest or QEMU.
>
> For example, POWER guest ne
I've forgot to include hunk with hw/qdev.h in cpu.c.
I'll repost.
--
-
Igor
On 06/21/2012 12:14 PM, Andreas Färber wrote:
Am 21.06.2012 11:43, schrieb Igor Mammedov:
On 06/20/2012 03:35 PM, Andreas Färber wrote:
Am 20.06.2012 14:59, schrieb Igor Mammedov:
It's not correct to make CPU runnable (i.e. calling x86_cpu_realize())
when not all properties are set (APIC in th
(Sorry for breaking the thread).
> This avoids the problem associated with having multiple target specific files
> in a single directory with the current build system.
What is exactly the problem?
I saw something about dependencies, I think that should be solved with
something like
$(foreach va
Am 21.06.2012 13:21, schrieb Alexey Kardashevskiy:
> On 21/06/12 20:36, Andreas Färber wrote:
>> Am 21.06.2012 05:22, schrieb Alexey Kardashevskiy:
>>> I am trying to compile the very last qemu with vfio_pci enabled. VFIO_PCI
>>> is added as below:
>>>
>>> ./configure:
>>>
>>> case "$target_arch2
On Wed, Jun 20, 2012 at 02:48:38PM -0300, Luiz Capitulino wrote:
> Yet another thread fork.
>
> After talking with Daniel and Markus about QMP errors (which is not just about
> QMP, as this affects QEMU as whole), I've put together the proposal below.
>
> I'll discuss three points. First, the err
Am 21.06.2012 02:21, schrieb Peter Crosthwaite:
> Ping!
>
> Id really appreciate some input on this issue (rather than going ahead
> and doing it to discover that someone disagrees with the approach).
>
> On Mon, Jun 18, 2012 at 3:13 PM, Peter Crosthwaite
> wrote:
>> So here are the nitty-gritty
On 06/21/2012 02:33 AM, Michael S. Tsirkin wrote:
On Thu, Jun 21, 2012 at 08:02:06AM +1000, Benjamin Herrenschmidt wrote:
On Wed, 2012-06-20 at 16:40 -0500, Anthony Liguori wrote:
Well let's return void in the DMA methods and let the IOMMUs assert on error.
At least that will avoid surprises u
On 06/21/2012 07:31 AM, Paolo Bonzini wrote:
(Sorry for breaking the thread).
This avoids the problem associated with having multiple target specific files
in a single directory with the current build system.
What is exactly the problem?
Peter's got an ARM specific KVM device he wants to st
On 21/06/12 22:19, Andreas Färber wrote:
> Am 21.06.2012 13:21, schrieb Alexey Kardashevskiy:
>> On 21/06/12 20:36, Andreas Färber wrote:
>>> Am 21.06.2012 05:22, schrieb Alexey Kardashevskiy:
I am trying to compile the very last qemu with vfio_pci enabled. VFIO_PCI
is added as below:
>>
On Wed, Jun 20, 2012 at 10:42 AM, wrote:
> From: Zhi Yong Wu
>
> All comments have been addressed and stefan has completed one more reviewing.
>
> For this patchset, my git repo:
>
> g...@github.com:wuzhy/qemu.git for-anthony
>
> Changelog from v5:
> 1.) cleanup VLANState in other targets files
On 06/21/2012 08:10 AM, Alexey Kardashevskiy wrote:
On 21/06/12 22:19, Andreas Färber wrote:
Am 21.06.2012 13:21, schrieb Alexey Kardashevskiy:
On 21/06/12 20:36, Andreas Färber wrote:
Am 21.06.2012 05:22, schrieb Alexey Kardashevskiy:
I am trying to compile the very last qemu with vfio_pci e
On Sat, Jun 16, 2012 at 03:20:57PM +1000, Peter A. G. Crosthwaite wrote:
> Patch 1 is trival, just deleted a redundant include that shouldn't be there.
> Patch 2 is a major bugfix for Microblaze platforms - the timer was deadlocking
> the system.
>
> Peter A. G. Crosthwaite (2):
> xilinx_timer:
Am 11.05.2012 03:49, schrieb Andreas Färber:
> Am 29.04.2012 20:57, schrieb Anthony Liguori:
>> We'll run this release much like the last one. All bug fixing will
>> happen in master until 1.1 is released. If you plan on maintaining a
>> subsystem tree while we're in feature freeze, please respon
On 64bit capable systems, MAS2 can actually hold a 64bit virtual page
address. So increase the mask for its EPN.
Signed-off-by: Alexander Graf
---
target-ppc/cpu.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 652a35a..ca2fc21
The BookE variant of MSR_SF is MSR_CM. Implement everything it takes in TCG to
support running 64bit code with MSR_CM set.
Signed-off-by: Alexander Graf
---
target-ppc/cpu.h |9 +
target-ppc/excp_helper.c |9 +
target-ppc/mem_helper.c |2 +-
target-ppc/transl
IVPR can either hold 32 or 64 bit addresses, depending on the CPU type. Let
the CPU initialization function pass in its mask itself, so we can easily
extend it.
Signed-off-by: Alexander Graf
---
target-ppc/translate_init.c |9 +
1 files changed, 5 insertions(+), 4 deletions(-)
diff
Am 21.06.2012 15:10, schrieb Alexey Kardashevskiy:
> On 21/06/12 22:19, Andreas Färber wrote:
>> Am 21.06.2012 13:21, schrieb Alexey Kardashevskiy:
>>> On 21/06/12 20:36, Andreas Färber wrote:
Am 21.06.2012 05:22, schrieb Alexey Kardashevskiy:
> I am trying to compile the very last qemu wi
On Thu, Jun 21, 2012 at 07:55:58AM -0500, Anthony Liguori wrote:
> On 06/21/2012 02:33 AM, Michael S. Tsirkin wrote:
> >On Thu, Jun 21, 2012 at 08:02:06AM +1000, Benjamin Herrenschmidt wrote:
> >>On Wed, 2012-06-20 at 16:40 -0500, Anthony Liguori wrote:
> >>
> >>>Well let's return void in the DMA m
This patch moves the debug #ifdef'ed SPR trace generation into its
own function, so we can call it from multiple places.
Signed-off-by: Alexander Graf
---
target-ppc/translate_init.c | 30 ++
1 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/target-pp
The number of SPRs avaiable in different PowerPC chip is still increasing. Add
definitions for the MAS7_MAS3 SPR and all currently known bits in EPCR.
Signed-off-by: Alexander Graf
---
target-ppc/cpu.h | 22 ++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --git a
This patch set adds support to emulate an e5500 based virtual machine. We don't
have a machine model for that one yet, but with this patch set applied we can
fake the compatibility property of the MPC8544DS model into P5020DS, which
gets guest kernels working for me.
The patch set is based on my r
Device trees usually have a node /compatible, which indicate which machine
type we're looking at. For quick prototyping, it can be very useful to change
the contents of that node via the command line.
Thus, introduce a new option to -machine called dt_compatible, which when
set changes the /compat
The MAS registers on BookE are all 32 bit wide, except for MAS2, which
can hold up to 64 bit on 64 bit capable CPUs. Reflect this in the SPR
setting code, so that the guest can never write invalid values in them.
Signed-off-by: Alexander Graf
---
target-ppc/translate_init.c | 19 ++
Recent u-boot has different defines for its gzip extract buffer, but the
common ground seems to be 64MB. So let's bump it up to that, enabling me
to load my test image again ;).
Signed-off-by: Alexander Graf
---
hw/loader.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --gi
This patch adds e5500's CPU initialization to the TCG CPU initialization
code.
Signed-off-by: Alexander Graf
---
v1 -> v2:
- remove reset msr vector
- clean up ivpr_mask code
---
target-ppc/translate_init.c | 96 +-
1 files changed, 93 insertions(
On the e500 series, accessing SPR_EPR magically turns into an access at
that CPU's IACK register on the MPIC. Implement that logic to get kernels
that make use of that feature work.
Signed-off-by: Alexander Graf
---
hw/ppce500_mpc8544ds.c |1 +
target-ppc/Makefile.objs |1 +
target-ppc
Whatever we pass in to qemu_devtree_setprop to put into the device tree
will not get modified by that function, so it can easily be declared const.
Signed-off-by: Alexander Graf
---
device_tree.c |2 +-
device_tree.h |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/d
On 2012-06-21 16:49, Liu Ping Fan wrote:
> In order to break the big lock, using per-cpu_lock in kvm_cpu_exec()
> to protect the race from other cpu's access to env->apic_state & related
> field in env.
> Also, we need to protect agaist run_on_cpu().
>
> Race condition can be like this:
> 1. vcpu
Nowadays, we use qemu_mutex_lock_iothread()/qemu_mutex_unlock_iothread() to
protect the race to access the emulated dev launched by vcpu threads & iothread.
But this lock is too big. We can break it down.
These patches separate the CPUArchState's protection from the other devices, so
we
can have
introduce a lock for per-cpu to protect agaist accesing from
other vcpu thread.
Signed-off-by: Liu Ping Fan
---
cpu-defs.h |2 ++
cpus.c | 17 +
main-loop.h |3 +++
3 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/cpu-defs.h b/cpu-defs.h
index f49e9
In order to break the big lock, using per-cpu_lock in kvm_cpu_exec()
to protect the race from other cpu's access to env->apic_state & related
field in env.
Also, we need to protect agaist run_on_cpu().
Race condition can be like this:
1. vcpu-1 IPI vcpu-2
vcpu-3 IPI vcpu-2
Open window exi
On Fri, Jun 15, 2012 at 11:49:36PM -, Michael Sabino wrote:
> Qemu 1.0.1 - Doesn't have a problem
> Qemu 1.1.0 - has the problem
> Qemu master commit eb2aeacf983a2a88a2b31e8fee067c38bd10abd3 - has the problem
I was also able to reproduce with commit:
eb2aeacf983a2a88a2b31e8fee067c38bd10abd3
On 2012-06-21 16:49, Liu Ping Fan wrote:
> Nowadays, we use qemu_mutex_lock_iothread()/qemu_mutex_unlock_iothread() to
> protect the race to access the emulated dev launched by vcpu threads &
> iothread.
>
> But this lock is too big. We can break it down.
> These patches separate the CPUArchState
On Thu, 2012-06-21 at 12:56 +0200, Jan Kiszka wrote:
> On 2012-06-21 12:50, Alexey Kardashevskiy wrote:
> > On 21/06/12 20:38, Jan Kiszka wrote:
> >> On 2012-06-21 12:28, Alexey Kardashevskiy wrote:
> >>> On 21/06/12 17:39, Jan Kiszka wrote:
> On 2012-06-21 09:18, Alexey Kardashevskiy wrote:
>
On Thu, 2012-06-21 at 16:04 +0200, Andreas Färber wrote:
> Am 21.06.2012 15:10, schrieb Alexey Kardashevskiy:
> > On 21/06/12 22:19, Andreas Färber wrote:
> >> Am 21.06.2012 13:21, schrieb Alexey Kardashevskiy:
> >>> On 21/06/12 20:36, Andreas Färber wrote:
> Am 21.06.2012 05:22, schrieb Alexe
On 06/21/2012 08:33 AM, Alexander Graf wrote:
> The MAS registers on BookE are all 32 bit wide, except for MAS2, which
> can hold up to 64 bit on 64 bit capable CPUs. Reflect this in the SPR
> setting code, so that the guest can never write invalid values in them.
>
> Signed-off-by: Alexander Graf
Anthony,
please pull Anthony Perard's Xen PCI Passthrough series from:
git://xenbits.xen.org/people/sstabellini/qemu-dm.git xen-pt
All the generic patches have been acked by Michael, the Xen patches have
been reviewed by Konrad and me.
Allen Kay (2):
Introduce Xen PCI Passthrough, qdevic
Anthony,
please pull a couple of small Xen compile fixes to compile against
xen-unstable:
git://xenbits.xen.org/people/sstabellini/qemu-dm.git compile-xs
Anthony PERARD (2):
xen: Reorganize includes of Xen headers.
xenstore: Use
configure|2 +-
hw/xen_backend.c |6
I confirm it works.
just compiled from commit c52acf60b6c12ff5eb58eb6ac568c159ae0c8737.
Windows XP SP3 installation iso boot and start installation process.
I tested both i368-softmmu and x86_64-softmmu targets.
thanks
Luigi
--
You received this bug notification because you are a member of qemu
On 21.06.2012, at 18:04, Scott Wood wrote:
> On 06/21/2012 08:33 AM, Alexander Graf wrote:
>> The MAS registers on BookE are all 32 bit wide, except for MAS2, which
>> can hold up to 64 bit on 64 bit capable CPUs. Reflect this in the SPR
>> setting code, so that the guest can never write invalid
On Wed, Jun 20, 2012 at 1:56 AM, Guan Xuetao wrote:
> On Mon, 2012-06-18 at 20:02 +, Blue Swirl wrote:
> [snip]
>> > diff --git a/hw/puv3.h b/hw/puv3.h
>> > new file mode 100644
>> > index 000..bcfc978
>> > --- /dev/null
>> > +++ b/hw/puv3.h
>> > @@ -0,0 +1,49 @@
>> > +/*
>> > + * Misc PKU
On Wed, Jun 20, 2012 at 2:10 AM, Guan Xuetao wrote:
> On Mon, 2012-06-18 at 19:59 +, Blue Swirl wrote:
> [snip]
>> > +
>> > +#define PUV3_DMA_CH_NR (6)
>> > +#define PUV3_DMA_CH_MASK (0xff)
>> > +#define PUV3_DMA_CH(offset) ((offset) >> 8)
>> > +
>> > +typedef struct {
>> >
On Wed, Jun 20, 2012 at 7:10 AM, Jia Liu wrote:
> Hi Blue,
>
> On Tue, Jun 19, 2012 at 3:11 AM, Blue Swirl wrote:
>> On Mon, Jun 18, 2012 at 1:02 AM, Jia Liu wrote:
>>> This is the OpenCores OpenRISC 1200 support for QEMU.
>>> Full implementation of the system-model and linux-user-model support.
On 21 June 2012 18:24, Blue Swirl wrote:
> On Wed, Jun 20, 2012 at 7:10 AM, Jia Liu wrote:
>> ERROR: need consistent spacing around '*' (ctx:WxV)
>> #99: FILE: target-openrisc/int_helper.c:53:
>> +target_ulong HELPER(mul32)(CPUOpenRISCState *env,
>>
>> It is really weird. And, I don't know how to
On Wed, Jun 20, 2012 at 7:14 AM, Jia Liu wrote:
> Hi Blue,
>
> On Tue, Jun 19, 2012 at 2:28 AM, Blue Swirl wrote:
>> On Mon, Jun 18, 2012 at 1:02 AM, Jia Liu wrote:
>>> Add OpenRISC target stubs and basic cpu support.
>>>
>>> Signed-off-by: Jia Liu
>>> ---
>>> arch_init.c
On Wed, Jun 20, 2012 at 1:40 AM, Guan Xuetao wrote:
> On Mon, 2012-06-18 at 19:51 +, Blue Swirl wrote:
>> On Mon, Jun 18, 2012 at 9:24 AM, Guan Xuetao wrote:
>> > Coprocessor 0 is system control coprocessor, and we need get/set its
>> > contents.
>> > Also, all cache/tlb ops shoule be implem
On Wed, Jun 20, 2012 at 8:21 AM, Markus Armbruster wrote:
> Blue Swirl writes:
>
>> On Tue, Jun 19, 2012 at 7:45 AM, Markus Armbruster wrote:
>>> Blue Swirl writes:
>>>
On Mon, Jun 18, 2012 at 9:10 AM, Markus Armbruster
wrote:
> Commit 5bbdbb46 moved it to block.c because "other
Hi,
I just noticed libvirt tries to use the -numa option in a way that qemu
never understood: if a node is configured to have a non-contiguous set
of CPUs, it tries to generate a command-line option that looks like:
"-numa node,nodeid=...,cpus=0,2,4,mem=..."
^
But
On Wed, Jun 20, 2012 at 8:11 PM, Alexander Graf wrote:
> Some machines have MSR bits they reset with as enabled. Don't hardcode the
> logic, but let the individual core implementations save their own reset
> mask into an env variable.
>
> Signed-off-by: Alexander Graf
> ---
> target-ppc/cpu.h
On 20 June 2012 21:11, Alexander Graf wrote:
> + env->reset_msr = (1ULL < MSR_SF);
I assume you mean "<<" rather than "<" here and below...
-- PMM
Blue Swirl writes:
> On Wed, Jun 20, 2012 at 8:21 AM, Markus Armbruster wrote:
>> Blue Swirl writes:
>>
>>> On Tue, Jun 19, 2012 at 7:45 AM, Markus Armbruster
>>> wrote:
Blue Swirl writes:
> On Mon, Jun 18, 2012 at 9:10 AM, Markus Armbruster
> wrote:
>> Commit 5bbdbb4
Hi,
I suggest a small change of the QEMU related mailing lists
(see https://lists.nongnu.org/mailman/listinfo/):
Replace Qemu-devel by QEMU-devel, Qemu-trivial by QEMU-trivial,
and so on.
This matches the official project name which is QEMU (not Qemu).
As far as I know, there is no convention w
On 21.06.2012, at 20:09, Blue Swirl wrote:
> On Wed, Jun 20, 2012 at 8:11 PM, Alexander Graf wrote:
>> Some machines have MSR bits they reset with as enabled. Don't hardcode the
>> logic, but let the individual core implementations save their own reset
>> mask into an env variable.
>>
>> Sign
On 21 June 2012 19:37, Stefan Weil wrote:
> I suggest a small change of the QEMU related mailing lists
> (see https://lists.nongnu.org/mailman/listinfo/):
>
> Replace Qemu-devel by QEMU-devel, Qemu-trivial by QEMU-trivial,
> and so on.
>
> This matches the official project name which is QEMU (not
Orit Wasserman wrote:
> On 05/22/2012 09:32 PM, Juan Quintela wrote:
>> cheking each 64 pages is a random magic number as good as any other.
> s/cheking/checking
Done.
>> +*/
>> +if ((i & 63) == 0) {
>> +uint64_t t1 = (qemu_get_clock_ns(rt_clock) - bwidth) / 100;
On Thu, Jun 21, 2012 at 8:37 PM, Stefan Weil wrote:
> Replace Qemu-devel by QEMU-devel, Qemu-trivial by QEMU-trivial,
> and so on.
I suggest to remove Qemu-devel, email clients can handle filtering.
--
Sebastien Douche
Twitter: @sdouche / G+: +sdouche
Commit dcff25f2cd8c11a9368cc2369aeb0319c32d9e26 removed too many *.d
files. The directories fpu/ and tcg/ still don't use the recursive
subdir rules.
Signed-off-by: Stefan Weil
---
Makefile.target |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile.target b/Makefile.t
This series actually does not do much conversion.
These should be safe, so I'd like to apply them soon.
Further AREG0 conversions need more work.
Blue Swirl (17):
x86: prepare op_helper.c for splitting
x86: avoid AREG0 for exceptions
x86: split off exception handlers
x86: avoid an extern
Move exception handlers from op_helper.c to excp_helper.c.
Signed-off-by: Blue Swirl
---
target-i386/Makefile.objs |1 +
target-i386/cpu.h | 10 +++-
target-i386/excp_helper.c | 132 +
target-i386/op_helper.c | 113 ---
Move SMM helpers to smm_helper.c.
Signed-off-by: Blue Swirl
---
target-i386/Makefile.objs |2 +
target-i386/op_helper.c | 285 -
target-i386/smm_helper.c | 307 +
3 files changed, 309 insertions(+), 285
These still fail the test but I'll send them for review and to
complement the first series.
Blue Swirl (9):
x86: avoid AREG0 for FPU helpers
x86: avoid AREG0 for condition code helpers
x86: avoid AREG0 for integer helpers
x86: avoid AREG0 for SVM helpers
x86: avoid AREG0 for SMM helpers
Add an explicit CPUX86State parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl
---
target-i386/Makefile.objs |1 -
target-i386/cc_helper.c | 199 +--
target-i386/cc_helper_template.h| 36 +++---
target-i386/helper.h
Add an explicit CPUX86State parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl
---
target-i386/Makefile.objs |1 -
target-i386/helper.h |2 +-
target-i386/smm_helper.c | 14 --
target-i386/translate.c |2 +-
4 files changed, 6 insertions(+), 13 del
Add an explicit CPUX86State parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl
---
target-i386/Makefile.objs |1 -
target-i386/helper.h | 22 +++---
target-i386/svm_helper.c | 181 ++---
target-i386/translate.c | 21 +++---
4
Move various functions to misc_helper.c.
Signed-off-by: Blue Swirl
---
target-i386/Makefile.objs |3 +-
target-i386/misc_helper.c | 603 +
target-i386/op_helper.c | 578 ---
3 files changed, 605 insertion
Move integer and bit field helpers to int_helper.c.
Signed-off-by: Blue Swirl
---
target-i386/Makefile.objs |3 +-
target-i386/int_helper.c | 500 +
target-i386/op_helper.c | 478 ---
3 files changed, 50
Add an explicit CPUX86State parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl
---
target-i386/Makefile.objs |1 -
target-i386/helper.h | 40
target-i386/misc_helper.c | 73 ++---
target-i386/translate.c
Switch to wrapped versions of memory access functions.
Signed-off-by: Blue Swirl
---
target-i386/cpu.h| 10 ++
target-i386/mem_helper.c | 10 ++
target-i386/seg_helper.c | 209 +++---
3 files changed, 126 insertions(+), 103 deletions(-)
diff
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