On 6/3/2025 3:41 PM, Xiaoyao Li wrote:
On 3/29/2025 4:30 AM, Tom Lendacky wrote:
A page state change is typically followed by an access of the page(s) and
results in another VMEXIT in order to map the page into the nested page
table. Depending on the size of page state change request, this can
On 3/29/2025 4:30 AM, Tom Lendacky wrote:
A page state change is typically followed by an access of the page(s) and
results in another VMEXIT in order to map the page into the nested page
table. Depending on the size of page state change request, this can
generate a number of additional VMEXITs.
Change sha348 to sha384.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/tdx.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/i386/kvm/tdx.h b/target/i386/kvm/tdx.h
index 04b5afe199f9..8dd66e90149b 100644
--- a/target/i386/kvm/tdx.h
+++ b/target/i386/kvm/tdx.h
Patch 1 and patch 3 are the left review feedback of TDX QEMU v9 series.
Patch 2 is caught during preparing patch 3.
Xiaoyao Li (3):
i386/cpu: Rename enable_cpuid_0x1f to force_cpuid_0x1f
i386/tdx: Fix the typo of the comment of struct TdxGuest
i386/tdx: Clarify the error message of
The name of "enable_cpuid_0x1f" isn't right to its behavior because the
leaf 0x1f can be enabled even when "enable_cpuid_0x1f" is false.
Rename it to "force_cpuid_0x1f" to better reflect its behavior.
Suggested-by: Igor Mammedov
Signed-off-by: Xiaoyao
The error message is misleading - we successfully decoded the data,
the decoded data was simply with the wrong length.
Change the error message to show it is an length check failure with both
the received and expected values.
Suggested-by: Daniel P. Berrangé
Signed-off-by: Xiaoyao Li
On 6/3/2025 1:31 AM, Cédric Le Goater wrote:
Use PRI formats where required and fix pointer cast.
Maybe we can make 32-bit build exclusive with CONFIG_TDX? since TDX is
not supported on 32-bit host.
Cc: Xiaoyao Li
Signed-off-by: Cédric Le Goater
---
target/i386/kvm/tdx.c | 26
Hello Markus,
On 6/2/2025 5:32 AM, Markus Armbruster wrote:
Annie Li writes:
Following hmp/qmp commands are implemented for pressing virtual
sleep button,
hmp: system_sleep
qmp: { "execute": "system_sleep" }
These commands put the guest into suspend or other power sta
VirtIOMEMReplayData, which makes
it cleaner.
Reviewed-by: David Hildenbrand
Signed-off-by: Chenyi Qiang
Reviewed-by: Xiaoyao Li
MemoryRegion at present.
Suggested-by: David Hildenbrand
Reviewed-by: David Hildenbrand
Signed-off-by: Chenyi Qiang
Reviewed-by: Xiaoyao Li
Kardashevskiy
Reviewed-by: Alexey Kardashevskiy
Reviewed-by: David Hildenbrand
Reviewed-by: Zhao Liu
Signed-off-by: Chenyi Qiang
Reviewed-by: Xiaoyao Li
On 29/05/2025 21:48, Jonathan Cameron via wrote:
> This has been wrong from day 1. For now we only have
> two entries (component and device registers).
Wow, I finally understood this.
>
> The wrong size could lead to arbitrary data off the stack being presented
> in PCIe config space.
>
> S
On 5/29/2025 12:13 AM, Paolo Bonzini wrote:
On 5/26/25 05:47, Xiaoyao Li wrote:
On 1/3/2025 4:48 PM, Xin Li (Intel) wrote:
@@ -1133,6 +1134,25 @@ FeatureWordInfo
feature_word_info[FEATURE_WORDS] = {
},
.tcg_features = TCG_7_1_EAX_FEATURES,
},
+ [FEAT_7_1_ECX
On 5/29/2025 3:13 PM, Paolo Bonzini wrote:
On 5/26/25 05:47, Xiaoyao Li wrote:
On 1/3/2025 4:48 PM, Xin Li (Intel) wrote:
The immediate form of MSR access instructions will use this new CPU
feature word.
Signed-off-by: Xin Li (Intel)
---
target/i386/cpu.c | 23
On 5/25/2025 8:47 PM, Xiaoyao Li wrote:
On 1/3/2025 4:48 PM, Xin Li (Intel) wrote:
@@ -1133,6 +1134,25 @@ FeatureWordInfo
feature_word_info[FEATURE_WORDS] = {
},
.tcg_features = TCG_7_1_EAX_FEATURES,
},
+ [FEAT_7_1_ECX] = {
+ .type = CPUID_FEATURE_WORD
The fixed hardware sleep button isn't appropriate for hardware
reduced platform. This patch implements the control method sleep
button in a separate source file so that the button can be added
for various platforms.
Co-developed-by: Miguel Luis
Signed-off-by: Annie Li
---
hw
'*_*' format, it is intended to do
so to align to existing 'system_*' commands.
Signed-off-by: Annie Li
---
hmp-commands.hx| 14 ++
hw/core/machine-hmp-cmds.c | 5 +
hw/core/machine-qmp-cmds.c | 11 +++
include/monitor/hmp.h
The function qemu_wakeup_suspend_enabled combines the suspend
and wakeup together. However, the microvm doesn't support
wakeup yet. Suspend is enabled here, but wakeup doesn't
actually work for microvm now.
Signed-off-by: Annie Li
---
hw/i386/microvm.c | 1 +
1 file changed, 1
Once the microvm guest requests to go to sleep state and
sets the GED register with S3 type, QEMU needs to continue
suspending the system.
Signed-off-by: Annie Li
---
hw/acpi/generic_event_device.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/acpi/generic_event_device.c b/hw/acpi
stem State
+{
+0x03,
+Zero,
+Zero,
+Zero
+})
+}
+
+Scope (\)
+{
Name (_S5, Package (0x04) // _S5_: S5 System State
{
0x05,
Zero,
Zero,
Zero
})
}
}
Signed-off
The sleep GED event is enabled for microvm. Also, the system
suspend is enabled when the GED register is set for sleep.
Signed-off-by: Annie Li
---
hw/i386/microvm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c
index d0a236c74f
From: Miguel Luis
Add support for ACPI GED sleep event on the ACPI device
interface so that HW-reduced systems can enable guests
to sleep.
Signed-off-by: Miguel Luis
Signed-off-by: Annie Li
---
hw/acpi/generic_event_device.c | 9 +
include/hw/acpi/generic_event_device.h | 1
Add the support of ACPI Control Method Sleep Button and System
S3 Sleeping State for microvm.
Signed-off-by: Annie Li
---
hw/i386/acpi-microvm.c | 13 -
include/hw/acpi/generic_event_device.h | 1 +
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/hw
List changed files in tests/qtest/bios-tables-test-allowed-diff.h
Signed-off-by: Annie Li
---
tests/qtest/bios-tables-test-allowed-diff.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index
The GPE event is triggered to notify x86 guest to sleep
itself. The function acpi_send_sleep_event will also
trigger GED events on HW-reduced systems where ACPI GED
sleep event is supported.
Signed-off-by: Annie Li
---
hw/acpi/core.c | 12
include/hw/acpi
0x0CD8, // Range Minimum
0x0CD8, // Range Maximum
0x01, // Alignment
0x0C, // Length
)
})
OperationRegion (PRST, SystemIO, 0x0CD8, 0
Add Control Method Sleep button and its GPE event handler for
x86 platform. The GPE event handler notifies OSPM when the
Sleep button event is triggered.
Signed-off-by: Annie Li
---
hw/i386/acpi-build.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a
List changed files in tests/qtest/bios-tables-test-allowed-diff.h
Signed-off-by: Annie Li
---
tests/qtest/bios-tables-test-allowed-diff.h | 42 +
1 file changed, 42 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test
FC V3
---
Annie Li (12):
acpi: Implement control method sleep button
test/acpi: allow DSDT table changes for x86 platform
acpi: Support Control Method sleep button for x86
tests/qtest/bios-table-tests: Update ACPI table binaries for x86
acpi: Send the GPE event of sleep for x86
test/acpi:
From: Li Chen
The virt machines always instantiate a PL011/16550 at UART0 and
describe it in ACPI (DSDT device node plus optional SPCR table). When
the command line contains “-serial none” there is no backend attached to
that UART, yet the guest still discovers it via ACPI and may try to use
it
Hi Thomos,
On Wed, 28 May 2025 17:52:50 +0800 Thomas Huth wrote
---
> On 28/05/2025 11.45, Li Chen wrote:
> > Hi,
> >
> > My emails to the qemu-devel, qemu-riscv, and qemu-arm mailing lists
> > regarding the
> > "[PATCH v4 0/4] acpi: Ad
From: Li Chen
Add ACPI SPCR table test case for RISC-V when SPCR was off.
Signed-off-by: Li Chen
Reviewed-by: Sunil V L
---
Notes:
Changes since v3: Add Reviewed-by from Sunil V L
tests/qtest/bios-tables-test.c | 22 ++
1 file changed, 22 insertions(+)
diff --git
From: Li Chen
The ACPI SPCR (Serial Port Console Redirection) table allows firmware
to specify a preferred serial console device to the operating system.
On ARM64 systems, Linux by default respects this table: even if the
kernel command line does not include a hardware serial console (e.g
From: Li Chen
Add ACPI SPCR table test case for ARM when SPCR was off.
Signed-off-by: Li Chen
---
tests/qtest/bios-tables-test.c | 20
1 file changed, 20 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 0a333ec435
From: Li Chen
(REPOST because the previous post failed to send to
qemu-devel/qemu-riscv/qemu-arm,
see
https://lore.kernel.org/qemu-devel/1971648603b.dce1f5d22901195.6702025346547333607@linux.beauty/T/#u)
This series introduces a new machine option, spcr=on|off, allowing users
to disable the
This series failed to send to qemu-devel/qemu-arm/qemu-riscv. I have requested
assistance via this thread:
https://lore.kernel.org/qemu-devel/1971648603b.dce1f5d22901195.6702025346547333607@linux.beauty/T/#u
On Wed, 28 May 2025 16:09:36 +0800 Li Chen wrote ---
> From: Li C
te: 28 May 2025 08:11:19 GMT
Diagnostic-Code: Message headers fail syntax check
Remote-MTA: dns; eggs.gnu.org
(... qemu-riscv/qemu-arm ...)
```
And below is the email header:
```
Received: by mx.zohomail.com with SMTPS id 1748419823397138.51964085412385;
Wed, 28 May 2025 01:10:23 -0700 (PDT
Hi Philippe,
On Mon, 26 May 2025 18:07:16 +0800 Philippe Mathieu-Daudé
wrote ---
> Hi Li,
>
> On 15/5/25 14:41, Li Chen wrote:
> > From: Li Chen
> >
> > The ACPI SPCR (Serial Port Console Redirection) table allows firmware
> > to specify a p
On 5/28/2025 4:11 PM, Thomas Huth wrote:
On 28/05/2025 05.01, Xiaoyao Li wrote:
On 5/12/2025 4:39 PM, Philippe Mathieu-Daudé wrote:
(series reviewed)
Since v3:
- Fixed 2 issues noticed by Thomas (floppy fallback, e1000)
Since v2:
- Removed qtest in test-x86-cpuid-compat.c
Since v1:
- Fixed
copy=1.39 GiB
> Page Types: normal=367713, zero=41195
>Page Rates (pps): transfer=40900, dirty=4
>Others: dirty_syncs=2, postcopy_req=57503
>
> Cc: Zhijian Li (Fujitsu)
> Suggested-by: Dr. David Alan Gilbert
> Signed-off-by: Peter Xu
Thanks for
On 5/28/2025 11:48 AM, Zhao Liu wrote:
On Wed, May 28, 2025 at 11:22:57AM +0800, Xiaoyao Li wrote:
Date: Wed, 28 May 2025 11:22:57 +0800
From: Xiaoyao Li
Subject: Re: [PATCH] Revert "i386/cpu: Set up CPUID_HT in
x86_cpu_expand_features() instead of cpu_x86_cpuid()"
On 5/28/202
On 5/28/2025 11:25 AM, Zhao Liu wrote:
Hi Elisey,
Thank you for your patch! I'm sorry I previously noticed #2894 [*] but
missed your report.
Recently there's a fix (commit 5979f50fa9fd ("i386/tcg: Make CPUID_HT
and CPUID_EXT3_CMP_LEG supported")). Does that fix address this bug?
[*]: https://l
On 5/12/2025 4:39 PM, Philippe Mathieu-Daudé wrote:
(series reviewed)
Since v3:
- Fixed 2 issues noticed by Thomas (floppy fallback, e1000)
Since v2:
- Removed qtest in test-x86-cpuid-compat.c
Since v1:
- Fixed issues noticed by Thomas
The versioned 'pc' and 'q35' machines up to 2.12 been mar
Li
---
hw/net/vmxnet3.c | 15 +--
1 file changed, 1 insertion(+), 14 deletions(-)
diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c
index d080fe9b38a..7c0ca56b7c0 100644
--- a/hw/net/vmxnet3.c
+++ b/hw/net/vmxnet3.c
@@ -2238,6 +2238,7 @@ static void vmxnet3_instance_init(Object *obj
ned-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
---
hw/net/vmxnet3.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c
index 3cf5d71f478..d080fe9b38a 100644
--
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
---
hw/net/vmxnet3.c | 20 ++--
1 file changed, 6 insertions(+), 14 deletions(-)
diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c
index 83d942af179..3cf5d71f
On 5/12/2025 4:39 PM, Philippe Mathieu-Daudé wrote:
Simplify replacing pvscsi_realize() by pvscsi_instance_init(),
removing the need for device_class_set_parent_realize().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
now
unused PVSCSIState::compat_flags field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Thomas Huth
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
---
hw/scsi/vmw_pvscsi.c | 30 +-
1 file changed, 1 insertion(+), 29
FIGURATION.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Thomas Huth
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
---
hw/scsi/vmw_pvscsi.c | 26 +++---
1 file changed, 7 insertions(+), 19 deletions(-)
diff --git a/hw/scsi/vmw_pvscsi.c
()
- fw_cfg_reset_order_override()
- fw_cfg_order[]
- rom_set_order_override()
- rom_reset_order_override()
Simplify CLI and pc_vga_init() / pc_nic_init().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
e220d8 for similar
VIRTIO_PCI_FLAG_* enum removal).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Thomas Huth
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
---
include/hw/virtio/virtio-pci.h | 4
hw/virtio/virtio-pci.c | 5 +
2 fil
-by: Thomas Huth
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
On 5/12/2025 4:39 PM, Philippe Mathieu-Daudé wrote:
The X86CPU::check_cpuid boolean was only set in the
pc_compat_2_4[] array, via the 'check=off' property.
We removed all machines using that array, lets remove
that CPU property and simplify x86_cpu_realizefn().
No.
We cannot do this. Because
now be removed.
Remove the now unused empty pc_compat_2_5[] array.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
On 5/12/2025 4:39 PM, Philippe Mathieu-Daudé wrote:
The hw_compat_2_5[] array was only used by the pc-q35-2.5 and
pc-i440fx-2.5 machines, which got removed. Remove it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
On 5/12/2025 4:39 PM, Philippe Mathieu-Daudé wrote:
The hw_compat_2_4[] array was only used by the pc-q35-2.4 and
pc-i440fx-2.4 machines, which got removed. Remove it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
On 5/12/2025 4:39 PM, Philippe Mathieu-Daudé wrote:
The pc_compat_2_4[] array was only used by the pc-q35-2.4
and pc-i440fx-2.4 machines, which got removed. Remove it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
now be removed.
Remove the qtest in test-x86-cpuid-compat.c file.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Thomas Huth
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
---
hw/i386/pc_piix.c | 13 -
hw
Reviewed-by: Thomas Huth
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
---
include/hw/i386/pc.h | 1 -
hw/i386/pc.c | 13 +
2 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 9563674e2da..f4a874b17fc 100644
On 5/27/2025 12:27 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
On 5/27/2025 12:12 AM, Paolo Bonzini wrote:
On 5/8/25 16:59, Xiaoyao Li wrote:
This is the v9 series of TDX QEMU enabling. The series is also available
at github:
https://github.com/intel-staging/qemu-tdx/tree/tdx-qemu
On 5/27/2025 12:12 AM, Paolo Bonzini wrote:
On 5/8/25 16:59, Xiaoyao Li wrote:
This is the v9 series of TDX QEMU enabling. The series is also available
at github:
https://github.com/intel-staging/qemu-tdx/tree/tdx-qemu-upstream-v9
Note, this series has a dependency on
https://lore.kernel.org
On 1/3/2025 4:48 PM, Xin Li (Intel) wrote:
The immediate form of MSR access instructions will use this new CPU
feature word.
Signed-off-by: Xin Li (Intel)
---
target/i386/cpu.c | 23 ++-
target/i386/cpu.h | 1 +
2 files changed, 23 insertions(+), 1 deletion(-)
diff
On 1/3/2025 4:48 PM, Xin Li (Intel) wrote:
WRMSRNS doesn't become a required feature for FERD, and Linux has
removed the dependency, as such remove it from Qemu.
Signed-off-by: Xin Li (Intel)
Reviewed-by: Xiaoyao Li
---
target/i386/cpu.c | 4
1 file changed, 4 deletions(-)
On 22/05/2025 21:16, Peter Xu wrote:
> I followed up with Dave's idea, but then added all entries into it, below.
>
>Status: postcopy-active
>Time (ms): total=40504, setup=14, down=145
>RAM info:
> Throughput (Mbps): 6102.65
> Sizes (KiB):pagesize=4, total=16777992
On 4/15/2025 8:25 PM, Xin Li wrote:
On 1/3/2025 12:48 AM, Xin Li (Intel) wrote:
The immediate form of MSR access instructions are primarily motivated by
performance, not code size: by having the MSR number in an immediate, it
is available *much* earlier in the pipeline, which allows the
On 21/05/2025 22:03, Peter Xu wrote:
> On Wed, May 21, 2025 at 08:43:37AM +, Zhijian Li (Fujitsu) wrote:
> [...]
>>> After this change, sample output (default, no "-a" specified):
>>>
>>> Status: postcopy-active
>>> Time (m
On 22/05/2025 05:04, Dr. David Alan Gilbert wrote:
> * Peter Xu (pet...@redhat.com) wrote:
>> On Wed, May 21, 2025 at 08:43:37AM +, Zhijian Li (Fujitsu) wrote:
>> [...]
>>>> After this change, sample output (default, no "-a" specified):
>>>>
&
On 15/05/2025 04:01, Peter Xu wrote:
> A new parameter "-a" is added to "info migrate" to dump all info, while
> when not specified it only dumps the important ones. When at it, reorg
> everything to make it easier to read for human.
>
> The general rule is:
>
>- Put important things at th
On 13/05/2025 19:14, Jonathan Cameron via wrote:
>
> +hwaddr cxl_fmws_set_memmap(hwaddr base, hwaddr max_addr)
> +{
> +GSList *cfmws_list, *iter;
> +
> +struct cfmw_update_state cfmwss = {
> +.base = base,
> +.maxaddr = max_addr,
> +.update_mmio = false,
> +
ron
Reviewed-by: Li Zhijian
> ---
> include/hw/cxl/cxl.h | 1 +
> hw/cxl/cxl-host.c| 9 ++---
> 2 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h
> index 75e47b6864..b2bcce7ed6 100644
> --- a/incl
On 13/05/2025 19:14, Jonathan Cameron via wrote:
> Previously these somewhat device like structures were tracked using a list
> in the CXLState in each machine. This is proving restrictive in a few
> cases where we need to iterate through these without being aware of the
> machine type. Just mak
From: Li Chen
The virt machines always instantiate a PL011/16550 at UART0 and
describe it in ACPI (DSDT device node plus optional SPCR table). When
the command line contains “-serial none” there is no backend attached to
that UART, yet the guest still discovers it via ACPI and may try to use
it
From: Li Chen
Add ACPI SPCR table test case for RISC-V when SPCR was off.
Signed-off-by: Li Chen
---
tests/qtest/bios-tables-test.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index d2a1aa7fb3
From: Li Chen
Add ACPI SPCR table test case for ARM when SPCR was off.
Signed-off-by: Li Chen
---
tests/qtest/bios-tables-test.c | 20
1 file changed, 20 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 0a333ec435
From: Li Chen
The ACPI SPCR (Serial Port Console Redirection) table allows firmware
to specify a preferred serial console device to the operating system.
On ARM64 systems, Linux by default respects this table: even if the
kernel command line does not include a hardware serial console (e.g
thieu-Daudé.
- Add Reviewed-by from Gavin Shan for the first patch and
fix style issue.
Changes since v1:
- Add bios-tables-test for RISC-V and ARM as suggested by
- Add Acked-by from Michael S. Tsirkin for the first patch
- Add Reviewed-by from Bibo Mao for the first patch
Li Chen (4):
acpi
-Mailer: Claws Mail 4.3.1 (GTK 3.24.43; x86_64-redhat-linux-gnu)
On Wed, 23 Apr 2025 19:46:58 +0800
Zhao Liu wrote:
From: Xiaoyao Li
Currently, QEMU exposes CPUID 0x1f to guest only when necessary, i.e.,
when topology level that cannot be enumerated by leaf 0xB, e.g., die or
module level, are
ed-by: Zhao Liu
Signed-off-by: Philippe Mathieu-Daudé
with the usage in hw/loongarch/fw_cfg.c fixed,
Reviewed-by: Xiaoyao Li
---
include/hw/nvram/fw_cfg.h | 6 +++---
hw/arm/virt.c | 2 +-
hw/nvram/fw_cfg.c | 6 +++---
hw/riscv/virt.c | 4 ++--
4 files changed
e
that fw_cfg_data_mem_ops.valid.max_access_size is not changed by other code.
It's even better to put this in a seperate patch.
For the pure rename part:
Reviewed-by: Xiaoyao Li
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, ms->smp.cpus);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, HPPA_MAX_CPUS);
fw_cfg
: Xiaoyao Li
---
hw/nvram/fw_cfg.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
index 10f8f8db86f..4067324fb09 100644
--- a/hw/nvram/fw_cfg.c
+++ b/hw/nvram/fw_cfg.c
@@ -1053,9 +1053,9 @@ FWCfgState
On 5/8/2025 9:35 PM, Philippe Mathieu-Daudé wrote:
fw_cfg_init_mem_wide() is prefered to initialize fw_cfg
with DMA support. Without DMA, use fw_cfg_init_mem_nodma().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Xiaoyao Li
---
hw/mips/loongson3_virt.c | 2 +-
1 file changed, 1
On 5/14/2025 1:17 AM, Philippe Mathieu-Daudé wrote:
As each target declares the same prototypes, we can
use a single header, removing the TARGET_XXX uses.
Signed-off-by: Philippe Mathieu-Daudé
...
diff --git a/hw/arm/xen-pvh.c b/hw/arm/xen-pvh.c
index 4b26bcff7a5..1a9eeb01c8e 100644
--- a/hw/
bits of TCG since multiple
vcpus are supported by TCG.
Fixes: c6bd2dd63420 ("i386/cpu: Set up CPUID_HT in x86_cpu_expand_features()
instead of cpu_x86_cpuid()")
Fixes: 99a637a86f55 ("i386/cpu: Set and track CPUID_EXT3_CMP_LEG in
env->features[FEAT_8000_0001_ECX]")
Report
VF, it should have the same warning of CPUID.01H:EDX.ht [bit 28].
This series tries to fix them.
Xiaoyao Li (2):
i386/tcg: Make CPUID_HT and CPUID_EXT3_CMP_LEG supported
i386/hvf: Make CPUID_HT supported
target/i386/cpu.c | 8 +---
target/i386/hvf/x86_cpuid.c | 2 +-
2 fil
It will trigger the warning like
qemu-system-x86_64: warning: host doesn't support requested feature:
CPUID.01H:EDX.ht [bit 28]
Add CPUID_HT to HVF supported CPUID bits to fix it.
Signed-off-by: Xiaoyao Li
---
Note, the issue is totally by my analysis (which should be the same as
the TC
Recently, we removed ipv6 restriction[0] from RDMA migration, add a
test for it.
[0]
https://lore.kernel.org/qemu-devel/20250326095224.9918-1-jinpu.w...@ionos.com/
Cc: Jack Wang
Cc: Michael R. Galaxy
Cc: Peter Xu
Cc: Yu Zhang
Reviewed-by: Jack Wang
Signed-off-by: Li Zhijian
---
V4
On 12/05/2025 21:56, Peter Xu wrote:
> On Mon, May 12, 2025 at 02:01:35PM +0800, Li Zhijian wrote:
>> Recently, we removed ipv6 restriction[0] from RDMA migration, add a
>> test for it.
>>
>> [0]
>> https://lore.kernel.org/qemu-devel/20250326095224.9918-1-jin
On 5/12/2025 5:31 PM, Paolo Bonzini wrote:
This brings in the userspace TDX API.
Signed-off-by: Paolo Bonzini
Reviewed-by: Xiaoyao Li
---
linux-headers/asm-x86/kvm.h | 71 +
linux-headers/linux/kvm.h | 1 +
2 files changed, 72 insertions(+)
diff
On 5/12/2025 6:54 PM, Markus Armbruster wrote:
Daniel P. Berrangé writes:
On Mon, May 12, 2025 at 09:46:30AM +0100, Peter Maydell wrote:
On Fri, 9 May 2025 at 11:04, Thomas Huth wrote:
Thanks for your clarifications, Zhao! But I think this shows again the
problem that we have hit a couple of
Recently, we removed ipv6 restriction[0] from RDMA migration, add a
test for it.
[0]
https://lore.kernel.org/qemu-devel/20250326095224.9918-1-jinpu.w...@ionos.com/
Cc: Jack Wang
Cc: Michael R. Galaxy
Cc: Peter Xu
Cc: Yu Zhang
Reviewed-by: Jack Wang
Signed-off-by: Li Zhijian
---
V3
On 09/05/2025 23:32, Peter Xu wrote:
> Does this mean I'll need to setup twice, one for each v?
>
> Even if so, I did this:
>
> ===8<===
> $ sudo ../scripts/rdma-migration-helper.sh setup
> Setup new rdma/rxe wlp0s20f3_rxe for wlp0s20f3 with 192.168.68.123
> $ sudo IP_FAMILY=ipv6 ../scripts/rdm
On 5/8/2025 11:55 PM, Daniel P. Berrangé wrote:
On Thu, May 08, 2025 at 10:59:19AM -0400, Xiaoyao Li wrote:
From: Isaku Yamahata
Three sha384 hash values, mrconfigid, mrowner and mrownerconfig, of a TD
can be provided for TDX attestation. Detailed meaning of them can be
found:
https
On 5/8/2025 9:35 PM, Philippe Mathieu-Daudé wrote:
The CPUX86State::enable_cpuid_0xb boolean was only disabled
for the pc-q35-2.6 and pc-i440fx-2.6 machines, which got
removed. Being now always %true, we can remove it and simplify
cpu_x86_cpuid().
Signed-off-by: Philippe Mathieu-Daudé
---
tar
an error state waiting migration to abort!
qemu-system-x86_64: failed to save SaveStateEntry with id(name): 2(ram): -1
qemu-system-x86_64: Channel error: Operation not permitted
Reported-by: Peter Xu
Signed-off-by: Li Zhijian
---
tests/qtest/migration/precopy-tests.c | 34
Recently, we removed ipv6 restriction[0] from RDMA migration, add a
test for it.
[0]
https://lore.kernel.org/qemu-devel/20250326095224.9918-1-jinpu.w...@ionos.com/
Cc: Jack Wang
Cc: Michael R. Galaxy
Cc: Peter Xu
Cc: Yu Zhang
Reviewed-by: Jack Wang
Signed-off-by: Li Zhijian
---
V2
licitly to ensure KVM provide correct
emulated APIC timer for TD guest.
Signed-off-by: Xiaoyao Li
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Zhao Liu
---
Changes in v6:
- new patch;
---
target/i386/kvm/tdx.c | 13 +
target/i386/kvm/tdx.h | 3 +++
2 files changed, 16 insertions(+)
For TDX guest, the phys_bits is not configurable and can only be
host/native value.
Validate phys_bits inside tdx_check_features().
Signed-off-by: Xiaoyao Li
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Zhao Liu
---
Changes in v9:
- return -EINVAL instead of exit(1); (Zhao Liu)
---
target
configure
this bit.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
Acked-by: Markus Armbruster
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Zhao Liu
---
Changes in v4:
- collect Acked-by from Markus
Changes in v3:
- update the comment of property @sept-ve-disable to make it more
For TDs, only MSR_IA32_UCODE_REV in kvm_init_msrs() can be configured
by VMM, while the features enumerated/controlled by other MSRs except
MSR_IA32_UCODE_REV in kvm_init_msrs() are not under control of VMM.
Only configure MSR_IA32_UCODE_REV for TDs.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd
that QEMU may change the CPUID
configuration when creating vCPUs, i.e. punts on refactoring QEMU to
provide a stable CPUID config prior to kvm_arch_init().
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
Acked-by: Markus Armbruster
Reviewed-by: Zhao Liu
---
Changes in v9:
- use error_append
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