On 5/29/2025 3:13 PM, Paolo Bonzini wrote:
On 5/26/25 05:47, Xiaoyao Li wrote:
On 1/3/2025 4:48 PM, Xin Li (Intel) wrote:
The immediate form of MSR access instructions will use this new CPU
feature word.

Signed-off-by: Xin Li (Intel) <x...@zytor.com>
---
  target/i386/cpu.c | 23 ++++++++++++++++++++++-
  target/i386/cpu.h |  1 +
  2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 8a1223acb3..2fb05879c3 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -894,6 +894,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,   #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \
            CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD)
+#define TCG_7_1_ECX_FEATURES 0
  #define TCG_7_1_EDX_FEATURES 0
  #define TCG_7_2_EDX_FEATURES 0
  #define TCG_APM_FEATURES 0
@@ -1133,6 +1134,25 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
          },
          .tcg_features = TCG_7_1_EAX_FEATURES,
      },
+    [FEAT_7_1_ECX] = {
+        .type = CPUID_FEATURE_WORD,
+        .feat_names = {
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,

This looks silly, and the size of feat_names[] was changed from 32 to 64. Just explicitly assign the first 32 entries with NULL doesn't make any sense after the size change.

64 is just for MSR features.  This is a bit silly, I agree, but it is consistent with existing feature words and ultimately it becomes more compact after just 9 features.  So I'm queuing Xin's patches as they are.

Yes. It makes sense for this reason, especially that this leaf is general feature enumeration leaf and destined to be filled up in the future.

Thanks for the review though!  It's always appreciated even if we disagree.

My pleasure.


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