The immediate form of MSR access instructions will use this new CPU
feature word.
Signed-off-by: Xin Li (Intel) <x...@zytor.com>
---
target/i386/cpu.c | 23 ++++++++++++++++++++++-
target/i386/cpu.h | 1 +
2 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 8a1223acb3..2fb05879c3 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -894,6 +894,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t
vendor1,
#define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM |
CPUID_7_1_EAX_FSRS | \
CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD)
+#define TCG_7_1_ECX_FEATURES 0
#define TCG_7_1_EDX_FEATURES 0
#define TCG_7_2_EDX_FEATURES 0
#define TCG_APM_FEATURES 0
@@ -1133,6 +1134,25 @@ FeatureWordInfo
feature_word_info[FEATURE_WORDS] = {
},
.tcg_features = TCG_7_1_EAX_FEATURES,
},
+ [FEAT_7_1_ECX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,