Reviewed-by: Niek Linnenbank
On Tue, Mar 18, 2025 at 7:14 AM Thomas Huth wrote:
> From: Thomas Huth
>
> We don't use the term "integration tests" for these kind of tests
> anymore, it's "functional tests" nowadays.
>
> Suggested-by: Niek Linnenb
Reviewed-by: Niek Linnenbank
On Tue, Mar 18, 2025 at 6:54 AM Thomas Huth wrote:
> From: Thomas Huth
>
> To avoid problems with the meson installation from the host
> system, we should always use the meson from our venv instead.
> Thus use this in the documentation, too.
>
&
Pi tests to the
functional framework")
Reviewed-by: Thomas Huth
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Niek Linnenbank
---
tests/functional/test_arm_orangepi.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/functional/test_arm_orangepi.py
Hi Thomas,
On Mon, Mar 17, 2025 at 7:50 AM Thomas Huth wrote:
> Hi!
>
> On 16/03/2025 21.21, Niek Linnenbank wrote:
> > Hi Thomas,
> >
> > On Tue, Mar 11, 2025 at 5:08 PM Thomas Huth > <mailto:th...@redhat.com>> wrote:
> >
> > The tests
The test class in this file contains all functional test cases
for testing the Orange Pi PC board. It should be given a name
matching the Qemu machine it covers.
This commit sets the test class name to 'OrangePiMachine'.
Signed-off-by: Niek Linnenbank
---
tests/functional/test_arm_o
-test
>
> ethtool can test register accesses, interrupts, etc. It is automated as an
> -Avocado test and can be ran with the following command:
> +functional test and can be ran with the following command:
>
> .. code:: shell
>
> - make check-avocado AVOCADO_TESTS=tests/avocado/netdev-ethtool.py
> + meson test --suite thorough func-x86_64-netdev_ethtool
>
> References
> ==
> --
> 2.48.1
>
>
--
Niek Linnenbank
orangepi_initrd
ok 4 test_arm_orangepi.BananaPiMachine.test_arm_orangepi_sd
ok 5 test_arm_orangepi.BananaPiMachine.test_arm_orangepi_uboot_netbsd9
1..5
Can you confirm the URL is working again properly on CI also?
Regards
Niek
On Thu, Mar 13, 2025 at 10:22 PM Niek Linnenbank
wrote:
> Hello Stefan,
ady provided a nice patch series to skip the test in
> case
> > of such incomplete downloads:
> >
> >
> https://lore.kernel.org/qemu-devel/20250312130002.945508-1-npig...@gmail.com/
> >
> > I'll try to assemble a pull request with these patches today.
>
> Thank you!
>
> Stefan
>
--
Niek Linnenbank
be it's better to stick with http for now.
>
Yes, I also just noted that the orangepi.org website is not responding.
However earlier this week, I was able to load the new URL above to the
official website.
Perhaps it is only temporary down, but we can only be sure once it comes
back up.
The NetBSD image URL is OK, ive also verified that the hash is the same.
So for me:
Reviewed-by: Niek Linnenbank
Regards,
Niek
--
Niek Linnenbank
out ehci driver
> can manage all devices via ohci, with usb 2.0+ devices being downgraded
> to 1.1 compatibility mode then).
>
> > If the real hardware only instantiates four USB ports (or, in other
> words,
> > if it utilizes EHCI companion functionality), would it make sense to
> > reflect that in qemu ?
>
> Yes.
>
> take care,
> Gerd
>
>
--
Niek Linnenbank
On Tue, Apr 30, 2024 at 4:12 PM Peter Maydell
wrote:
> On Mon, 29 Apr 2024 at 21:40, Niek Linnenbank
> wrote:
> >
> > Hi Peter, Strahinja,
> >
> > I can confirm that the orangepi-pc and cubieboard based tests are
> working OK using the newer kernel 6.6.16:
>
/avocado/boot_linux_console.py
...
RESULTS: PASS 7 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 |
CANCEL 1
JOB TIME : 177.65 s
So for this patch:
Reviewed-by: Niek Linnenbank
Tested-by: Niek Linnenbank
About the BootLinuxConsole.test_arm_orangepi_bionic_20_08 test, I'd be
Hi Peter, Qianfan,
On Mon, Jun 5, 2023 at 5:31 PM Peter Maydell
wrote:
> On Thu, 1 Jun 2023 at 19:48, Niek Linnenbank
> wrote:
> >
> > Hi Qianfan,
> >
> > Thanks for sending the v5. From my side, I have no further comments on
> the content.
> > So please
Hi Qianfan,
Thanks for sending the v5. From my side, I have no further comments on the
content.
So please feel free to add the following to each of the patches 01-11 in
the series:
Reviewed-by: Niek Linnenbank
As a reminder and explained here on this page, you'll need to make sure
these
-ccu.c
> create mode 100644 hw/misc/allwinner-r40-dramc.c
> create mode 100644 hw/misc/allwinner-sramc.c
> delete mode 100644 hw/misc/axp209.c
> create mode 100644 hw/misc/axp2xx.c
> create mode 100644 include/hw/arm/allwinner-r40.h
> create mode 100644 include/hw/misc/allwinner-r40-ccu.h
> create mode 100644 include/hw/misc/allwinner-r40-dramc.h
> create mode 100644 include/hw/misc/allwinner-sramc.h
>
> --
> 2.25.1
>
>
--
Niek Linnenbank
On Wed, May 10, 2023 at 12:31 PM wrote:
> From: qianfan Zhao
>
> Add documents for Banana Pi M2U
>
> Signed-off-by: qianfan Zhao
>
Reviewed-by: Niek Linnenbank
> ---
> docs/system/arm/bananapi_m2u.rst | 138 +++
> 1 file changed, 138 i
wed-by: Niek Linnenbank
Tested-by: Niek Linnenbank
Regards,
Niek
>
> Signed-off-by: qianfan Zhao
> ---
> tests/avocado/boot_linux_console.py | 176
> 1 file changed, 176 insertions(+)
>
> diff --git a/tests/avocado/boot_linux_console.py
> b
On Wed, May 10, 2023 at 12:30 PM wrote:
> From: qianfan Zhao
>
> Only a few important registers are added, especially the SRAM_VER
> register.
>
> Signed-off-by: qianfan Zhao
>
Reviewed-by: Niek Linnenbank
> ---
> hw/arm/Kconfig| 1
/allwinner-r40-ccu.h"
> #include "hw/misc/allwinner-r40-dramc.h"
> #include "hw/i2c/allwinner-i2c.h"
> +#include "hw/net/allwinner_emac.h"
> +#include "hw/net/allwinner-sun8i-emac.h"
> #include "target/arm/cpu.h"
> #include "sysemu/block-backend.h"
>
> @@ -36,6 +38,7 @@ enum {
> AW_R40_DEV_SRAM_A2,
> AW_R40_DEV_SRAM_A3,
> AW_R40_DEV_SRAM_A4,
> +AW_R40_DEV_EMAC,
> AW_R40_DEV_MMC0,
> AW_R40_DEV_MMC1,
> AW_R40_DEV_MMC2,
> @@ -51,6 +54,7 @@ enum {
> AW_R40_DEV_UART6,
> AW_R40_DEV_UART7,
> AW_R40_DEV_TWI0,
> +AW_R40_DEV_GMAC,
> AW_R40_DEV_GIC_DIST,
> AW_R40_DEV_GIC_CPU,
> AW_R40_DEV_GIC_HYP,
> @@ -103,6 +107,8 @@ struct AwR40State {
> AwR40ClockCtlState ccu;
> AwR40DramCtlState dramc;
> AWI2CState i2c0;
> +AwEmacState emac;
> +AwSun8iEmacState gmac;
> GICState gic;
> MemoryRegion sram_a1;
> MemoryRegion sram_a2;
> --
> 2.25.1
>
>
Regards,
Niek
--
Niek Linnenbank
; *data)
> @@ -888,6 +920,24 @@ static void
> allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data)
> sc->is_sun4i = false;
> }
>
> +static void allwinner_sdhost_sun50i_a64_class_init(ObjectClass *klass,
> +
cpus[AW_R40_NUM_CPUS];
> const hwaddr *memmap;
> AwA10PITState timer;
> AwSdHostState mmc[AW_R40_NUM_MMCS];
> AwR40ClockCtlState ccu;
> +AwR40DramCtlState dramc;
> AWI2CState i2c0;
> GICState gic;
> MemoryRegion sram_a1;
> diff --git a/include/hw/misc/allwinner-r40-dramc.h
> b/include/hw/misc/allwinner-r40-dramc.h
> new file mode 100644
> index 00..6a1a3a7893
> --- /dev/null
> +++ b/include/hw/misc/allwinner-r40-dramc.h
> @@ -0,0 +1,108 @@
> +/*
> + * Allwinner R40 SDRAM Controller emulation
> + *
> + * Copyright (C) 2023 qianfan Zhao
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef HW_MISC_ALLWINNER_R40_DRAMC_H
> +#define HW_MISC_ALLWINNER_R40_DRAMC_H
> +
> +#include "qom/object.h"
> +#include "hw/sysbus.h"
> +#include "exec/hwaddr.h"
> +
> +/**
> + * Constants
> + * @{
> + */
> +
> +/** Highest register address used by DRAMCOM module */
> +#define AW_R40_DRAMCOM_REGS_MAXADDR (0x804)
> +
> +/** Total number of known DRAMCOM registers */
> +#define AW_R40_DRAMCOM_REGS_NUM (AW_R40_DRAMCOM_REGS_MAXADDR / \
> + sizeof(uint32_t))
> +
> +/** Highest register address used by DRAMCTL module */
> +#define AW_R40_DRAMCTL_REGS_MAXADDR (0x88c)
> +
> +/** Total number of known DRAMCTL registers */
> +#define AW_R40_DRAMCTL_REGS_NUM (AW_R40_DRAMCTL_REGS_MAXADDR / \
> + sizeof(uint32_t))
> +
> +/** Highest register address used by DRAMPHY module */
> +#define AW_R40_DRAMPHY_REGS_MAXADDR (0x4)
> +
> +/** Total number of known DRAMPHY registers */
> +#define AW_R40_DRAMPHY_REGS_NUM (AW_R40_DRAMPHY_REGS_MAXADDR / \
> + sizeof(uint32_t))
> +
> +/** @} */
> +
> +/**
> + * Object model
> + * @{
> + */
> +
> +#define TYPE_AW_R40_DRAMC "allwinner-r40-dramc"
> +OBJECT_DECLARE_SIMPLE_TYPE(AwR40DramCtlState, AW_R40_DRAMC)
> +
> +/** @} */
> +
> +/**
> + * Allwinner R40 SDRAM Controller object instance state.
> + */
> +struct AwR40DramCtlState {
> +/*< private >*/
> +SysBusDevice parent_obj;
> +/*< public >*/
> +
> +/** Physical base address for start of RAM */
> +hwaddr ram_addr;
> +
> +/** Total RAM size in megabytes */
> +uint32_t ram_size;
> +
> +uint8_t set_row_bits;
> +uint8_t set_bank_bits;
> +uint8_t set_col_bits;
> +
> +/**
> + * @name Memory Regions
> + * @{
> + */
> +MemoryRegion dramcom_iomem;/**< DRAMCOM module I/O registers */
> +MemoryRegion dramctl_iomem;/**< DRAMCTL module I/O registers */
> +MemoryRegion dramphy_iomem;/**< DRAMPHY module I/O registers */
> +MemoryRegion dram_high;/**< The high 1G dram for dualrank
> detect */
> +MemoryRegion detect_cells; /**< DRAM memory cells for auto detect
> */
> +
> +/** @} */
> +
> +/**
> + * @name Hardware Registers
> + * @{
> + */
> +
> +uint32_t dramcom[AW_R40_DRAMCOM_REGS_NUM]; /**< DRAMCOM registers */
> +uint32_t dramctl[AW_R40_DRAMCTL_REGS_NUM]; /**< DRAMCTL registers */
> +uint32_t dramphy[AW_R40_DRAMPHY_REGS_NUM] ;/**< DRAMPHY registers */
> +
> +/** @} */
> +
> +};
> +
> +#endif /* HW_MISC_ALLWINNER_R40_DRAMC_H */
> --
> 2.25.1
>
>
Looks good to me.
Reviewed-by: Niek Linnenbank
--
Niek Linnenbank
+static const TypeInfo axp209_info = {
> +.name = TYPE_AXP209_PMU,
> +.parent = TYPE_AXP2XX,
> +.class_init = axp209_class_init
> +};
> +
> +static void axp221_class_init(ObjectClass *oc, void *data)
> +{
> +AXP2xxClass *sc = AXP2XX_CLASS(oc);
> +
> +sc->reset_enter = axp221_reset_enter;
> +}
> +
> +static const TypeInfo axp221_info = {
> +.name = TYPE_AXP221_PMU,
> +.parent = TYPE_AXP2XX,
> +.class_init = axp221_class_init,
> +};
> +
> +static void axp2xx_register_devices(void)
> +{
> +type_register_static(&axp2xx_info);
> +type_register_static(&axp209_info);
> +type_register_static(&axp221_info);
> +}
> +
> +type_init(axp2xx_register_devices);
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index 96e35f1cdb..1db034 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -45,7 +45,7 @@ softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true:
> files('allwinner-h3-dramc.c
> softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true:
> files('allwinner-h3-sysctrl.c'))
> softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true:
> files('allwinner-sid.c'))
> softmmu_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true:
> files('allwinner-r40-ccu.c'))
> -softmmu_ss.add(when: 'CONFIG_AXP209_PMU', if_true: files('axp209.c'))
> +softmmu_ss.add(when: 'CONFIG_AXP2XX_PMU', if_true: files('axp2xx.c'))
> softmmu_ss.add(when: 'CONFIG_REALVIEW', if_true: files('arm_sysctl.c'))
> softmmu_ss.add(when: 'CONFIG_NSERIES', if_true: files('cbus.c'))
> softmmu_ss.add(when: 'CONFIG_ECCMEMCTL', if_true: files('eccmemctl.c'))
> diff --git a/hw/misc/trace-events b/hw/misc/trace-events
> index c47876a902..24cdec83fe 100644
> --- a/hw/misc/trace-events
> +++ b/hw/misc/trace-events
> @@ -23,10 +23,10 @@ allwinner_sid_write(uint64_t offset, uint64_t data,
> unsigned size) "offset 0x%"
> avr_power_read(uint8_t value) "power_reduc read value:%u"
> avr_power_write(uint8_t value) "power_reduc write value:%u"
>
> -# axp209.c
> -axp209_rx(uint8_t reg, uint8_t data) "Read reg 0x%" PRIx8 " : 0x%" PRIx8
> -axp209_select(uint8_t reg) "Accessing reg 0x%" PRIx8
> -axp209_tx(uint8_t reg, uint8_t data) "Write reg 0x%" PRIx8 " : 0x%" PRIx8
> +# axp2xx
> +axp2xx_rx(uint8_t reg, uint8_t data) "Read reg 0x%" PRIx8 " : 0x%" PRIx8
> +axp2xx_select(uint8_t reg) "Accessing reg 0x%" PRIx8
> +axp2xx_tx(uint8_t reg, uint8_t data) "Write reg 0x%" PRIx8 " : 0x%" PRIx8
>
> # eccmemctl.c
> ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
> --
> 2.25.1
>
>
--
Niek Linnenbank
ta rate
> up to 400kbit/s.
>
> Signed-off-by: qianfan Zhao
>
Reviewed-by: Niek Linnenbank
> ---
> hw/arm/allwinner-r40.c | 11 ++-
> include/hw/arm/allwinner-r40.h | 3 +++
> 2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/hw/arm/all
_UART3 = 4,
>
Since you put the addition of UART1-7 in this patch, probably it makes
sense to have adding the lines 'AW_R40_GIC_SPI_UART1/2/3' also part of this
patch.
With the two above remarks resolved, the patch looks good to me.
Reviewed-by: Niek Linnenbank
Regards,
#x27;omap2.c'))
> arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c'))
> arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true:
> files('allwinner-a10.c', 'cubieboard.c'))
> arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c',
> 'orangepi.c'))
> +arm_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true:
> files('allwinner-r40.c', 'bananapi_m2u.c'))
> arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c'))
> arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true:
> files('stm32f100_soc.c'))
> arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true:
> files('stm32f205_soc.c'))
> diff --git a/include/hw/arm/allwinner-r40.h
> b/include/hw/arm/allwinner-r40.h
> new file mode 100644
> index 00..348bf25d6b
> --- /dev/null
> +++ b/include/hw/arm/allwinner-r40.h
> @@ -0,0 +1,110 @@
> +/*
> + * Allwinner R40/A40i/T3 System on Chip emulation
> + *
> + * Copyright (C) 2023 qianfan Zhao
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef HW_ARM_ALLWINNER_R40_H
> +#define HW_ARM_ALLWINNER_R40_H
> +
> +#include "qom/object.h"
> +#include "hw/arm/boot.h"
> +#include "hw/timer/allwinner-a10-pit.h"
> +#include "hw/intc/arm_gic.h"
> +#include "hw/sd/allwinner-sdhost.h"
> +#include "target/arm/cpu.h"
> +#include "sysemu/block-backend.h"
> +
> +enum {
> +AW_R40_DEV_SRAM_A1,
> +AW_R40_DEV_SRAM_A2,
> +AW_R40_DEV_SRAM_A3,
> +AW_R40_DEV_SRAM_A4,
> +AW_R40_DEV_MMC0,
> +AW_R40_DEV_MMC1,
> +AW_R40_DEV_MMC2,
> +AW_R40_DEV_MMC3,
> +AW_R40_DEV_CCU,
> +AW_R40_DEV_PIT,
> +AW_R40_DEV_UART0,
> +AW_R40_DEV_GIC_DIST,
> +AW_R40_DEV_GIC_CPU,
> +AW_R40_DEV_GIC_HYP,
> +AW_R40_DEV_GIC_VCPU,
> +AW_R40_DEV_SDRAM
> +};
> +
> +#define AW_R40_NUM_CPUS (4)
> +
> +/**
> + * Allwinner R40 object model
> + * @{
> + */
> +
> +/** Object type for the Allwinner R40 SoC */
> +#define TYPE_AW_R40 "allwinner-r40"
> +
> +/** Convert input object to Allwinner R40 state object */
> +OBJECT_DECLARE_SIMPLE_TYPE(AwR40State, AW_R40)
> +
> +/** @} */
> +
> +/**
> + * Allwinner R40 object
> + *
> + * This struct contains the state of all the devices
> + * which are currently emulated by the R40 SoC code.
> + */
> +#define AW_R40_NUM_MMCS 4
> +
> +struct AwR40State {
> +/*< private >*/
> +DeviceState parent_obj;
> +/*< public >*/
> +
> +ARMCPU cpus[AW_R40_NUM_CPUS];
> +const hwaddr *memmap;
> +AwA10PITState timer;
> +AwSdHostState mmc[AW_R40_NUM_MMCS];
> +GICState gic;
> +MemoryRegion sram_a1;
> +MemoryRegion sram_a2;
> +MemoryRegion sram_a3;
> +MemoryRegion sram_a4;
> +};
> +
> +/**
> + * Emulate Boot ROM firmware setup functionality.
> + *
> + * A real Allwinner R40 SoC contains a Boot ROM
> + * which is the first code that runs right after
> + * the SoC is powered on. The Boot ROM is responsible
> + * for loading user code (e.g. a bootloader) from any
> + * of the supported external devices and writing the
> + * downloaded code to internal SRAM. After loading the SoC
> + * begins executing the code written to SRAM.
> + *
> + * This function emulates the Boot ROM by copying 32 KiB
> + * of data from the given block device and writes it to
> + * the start of the first internal SRAM memory.
> + *
> + * @s: Allwinner R40 state object pointer
> + * @blk: Block backend device object pointer
> + * @unit: the mmc control's unit
> + */
> +bool allwinner_r40_bootrom_setup(AwR40State *s, BlockBackend *blk, int
> unit);
> +
> +#endif /* HW_ARM_ALLWINNER_R40_H */
> --
> 2.25.1
>
>
--
Niek Linnenbank
it which emulates
> a simple read/write register interface.
>
> Signed-off-by: qianfan Zhao
>
Reviewed-by: Niek Linnenbank
> ---
> hw/arm/allwinner-r40.c | 8 +-
> hw/misc/allwinner-r40-ccu.c | 209
> hw/misc/meson.bu
t; differ in applicable temperatures range (industrial and military).
>
> Signed-off-by: qianfan Zhao
>
Reviewed-by: Niek Linnenbank
> ---
> hw/arm/Kconfig | 10 +
> hw/arm/allwinner-r40.c | 418 +
> hw/arm/banana
e *s, AwSdHostState *mmc, int unit,
> + bool load_bootroom, bool *bootroom_loaded)
> +{
> +DriveInfo *di = drive_get(IF_SD, 0, unit);
> +BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
> +BusState *bus;
> +DeviceState *carddev;
:
Tested-by: Niek Linnenbank
On Tue, Mar 28, 2023 at 7:49 AM wrote:
> From: qianfan Zhao
>
> Add test case for booting from initrd and sd card.
>
> Signed-off-by: qianfan Zhao
> ---
> tests/avocado/boot_linux_console.py | 176
> 1 file
W_SDHOST "-sun50i-a64-emmc"
> +
> /** @} */
>
> /**
> @@ -110,6 +116,7 @@ struct AwSdHostState {
> uint32_t startbit_detect; /**< eMMC DDR Start Bit Detection Control
> */
> uint32_t response_crc; /**< Response CRC */
> uint32_t data_crc[8]; /**< Data CRC */
> +uint32_t sample_delay; /**< Sample delay control */
> uint32_t status_crc;/**< Status CRC */
>
> /** @} */
> @@ -132,6 +139,8 @@ struct AwSdHostClass {
> size_t max_desc_size;
> bool is_sun4i;
>
> +/** does the IP block support autocalibration? */
> +bool can_calibrate;
> };
>
> #endif /* HW_SD_ALLWINNER_SDHOST_H */
> --
> 2.25.1
>
>
In this patch, I don't see any update to the new allwinner-r40.c file.
If you make the required changes to allwinner-r40.c in this patch, you can
also avoid having patch 08.
Regards,
Niek
--
Niek Linnenbank
On Tue, Mar 28, 2023 at 7:48 AM wrote:
> From: qianfan Zhao
>
> Add documents for Banana Pi M2U
>
> Signed-off-by: qianfan Zhao
>
Reviewed-by: Niek Linnenbank
> ---
> docs/system/arm/bananapi_m2u.rst | 138 +++
> 1 file changed, 138 i
s->mmc[i],
> -TYPE_AW_SDHOST_SUN5I);
> +TYPE_AW_SDHOST_SUN50I_A64);
> }
>
> object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I);
> --
> 2.25.1
>
>
--
Niek Linnenbank
it which emulates
> a simple read/write register interface.
>
> Signed-off-by: qianfan Zhao
>
Reviewed-by: Niek Linnenbank
> ---
> hw/arm/allwinner-r40.c | 8 +-
> hw/misc/allwinner-r40-ccu.c | 209
> hw/misc/meson.bu
STRONGARM', if_true: files('strongarm.c'))
> arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true:
> files('allwinner-a10.c', 'cubieboard.c'))
> arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c',
> 'orangepi.c'))
> +arm_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true:
> files('allwinner-r40.c', 'bananapi_m2u.c'))
> arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c'))
> arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true:
> files('stm32f100_soc.c'))
> arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true:
> files('stm32f205_soc.c'))
> diff --git a/include/hw/arm/allwinner-r40.h
> b/include/hw/arm/allwinner-r40.h
> new file mode 100644
> index 00..348bf25d6b
> --- /dev/null
> +++ b/include/hw/arm/allwinner-r40.h
> @@ -0,0 +1,110 @@
> +/*
> + * Allwinner R40/A40i/T3 System on Chip emulation
> + *
> + * Copyright (C) 2023 qianfan Zhao
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef HW_ARM_ALLWINNER_R40_H
> +#define HW_ARM_ALLWINNER_R40_H
> +
> +#include "qom/object.h"
> +#include "hw/arm/boot.h"
> +#include "hw/timer/allwinner-a10-pit.h"
> +#include "hw/intc/arm_gic.h"
> +#include "hw/sd/allwinner-sdhost.h"
> +#include "target/arm/cpu.h"
> +#include "sysemu/block-backend.h"
> +
> +enum {
> +AW_R40_DEV_SRAM_A1,
> +AW_R40_DEV_SRAM_A2,
> +AW_R40_DEV_SRAM_A3,
> +AW_R40_DEV_SRAM_A4,
> +AW_R40_DEV_MMC0,
> +AW_R40_DEV_MMC1,
> +AW_R40_DEV_MMC2,
> +AW_R40_DEV_MMC3,
> +AW_R40_DEV_CCU,
> +AW_R40_DEV_PIT,
> +AW_R40_DEV_UART0,
> +AW_R40_DEV_GIC_DIST,
> +AW_R40_DEV_GIC_CPU,
> +AW_R40_DEV_GIC_HYP,
> +AW_R40_DEV_GIC_VCPU,
> +AW_R40_DEV_SDRAM
> +};
> +
> +#define AW_R40_NUM_CPUS (4)
> +
> +/**
> + * Allwinner R40 object model
> + * @{
> + */
> +
> +/** Object type for the Allwinner R40 SoC */
> +#define TYPE_AW_R40 "allwinner-r40"
> +
> +/** Convert input object to Allwinner R40 state object */
> +OBJECT_DECLARE_SIMPLE_TYPE(AwR40State, AW_R40)
> +
> +/** @} */
> +
> +/**
> + * Allwinner R40 object
> + *
> + * This struct contains the state of all the devices
> + * which are currently emulated by the R40 SoC code.
> + */
> +#define AW_R40_NUM_MMCS 4
> +
> +struct AwR40State {
> +/*< private >*/
> +DeviceState parent_obj;
> +/*< public >*/
> +
> +ARMCPU cpus[AW_R40_NUM_CPUS];
> +const hwaddr *memmap;
> +AwA10PITState timer;
> +AwSdHostState mmc[AW_R40_NUM_MMCS];
> +GICState gic;
> +MemoryRegion sram_a1;
> +MemoryRegion sram_a2;
> +MemoryRegion sram_a3;
> +MemoryRegion sram_a4;
> +};
> +
> +/**
> + * Emulate Boot ROM firmware setup functionality.
> + *
> + * A real Allwinner R40 SoC contains a Boot ROM
> + * which is the first code that runs right after
> + * the SoC is powered on. The Boot ROM is responsible
> + * for loading user code (e.g. a bootloader) from any
> + * of the supported external devices and writing the
> + * downloaded code to internal SRAM. After loading the SoC
> + * begins executing the code written to SRAM.
> + *
> + * This function emulates the Boot ROM by copying 32 KiB
> + * of data from the given block device and writes it to
> + * the start of the first internal SRAM memory.
> + *
> + * @s: Allwinner R40 state object pointer
> + * @blk: Block backend device object pointer
> + * @unit: the mmc control's unit
> + */
> +bool allwinner_r40_bootrom_setup(AwR40State *s, BlockBackend *blk, int
> unit);
> +
> +#endif /* HW_ARM_ALLWINNER_R40_H */
> --
> 2.25.1
>
>
With the above resolved/answered:
Reviewed-by: Niek Linnenbank
--
Niek Linnenbank
w/watchdog/allwinner-wdt.c
> new file mode 100644
> index 00..45a4a36ba7
> --- /dev/null
> +++ b/hw/watchdog/allwinner-wdt.c
> @@ -0,0 +1,416 @@
> +/*
> + * Allwinner Watchdog emulation
> + *
> + * Copyright (C) 2023 Strahinja Jankovic
> + *
> + * This file is
On Sat, Mar 11, 2023 at 3:42 PM Strahinja Jankovic <
strahinjapjanko...@gmail.com> wrote:
> This patch adds WDT to Allwinner-H3 and Orangepi-PC.
> WDT is added as an overlay to the Timer module memory area.
>
> Signed-off-by: Strahinja Jankovic
>
Reviewed-by: Niek Linnen
sheet.pdf", except for a very brief
summary in chapter 9.1 in the Timer Controller. But I did find that linux
is using this same base address and registers with the shared driver code
in drivers/watchdog/sunxi_wdt.c.
Looks good to me.
Reviewed-by: Niek Linnenbank
atchdog/allwinner-wdt.c
> new file mode 100644
> index 00..cf16ec7a56
> --- /dev/null
> +++ b/hw/watchdog/allwinner-wdt.c
> @@ -0,0 +1,428 @@
> +/*
> + * Allwinner Watchdog emulation
> + *
> + * Copyright (C) 2023 Strahinja Jankovic
> + *
> + * This file is de
Mar 14 19:56:37 UTC 2023
\console: Starting root file system check:
PASS (22.45 s)
RESULTS: PASS 8 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 |
CANCEL 0
JOB TIME : 189.23 s
Reviewed-by: Niek Linnenbank
Tested-by: Niek Linnenbank
On Sat, Mar 11, 2023 at 3:42 PM Strahinja Jankovic
ry
to find some time for a more detailed review of your patches.
Kind regards,
Niek Linnenbank
On Thu, Mar 2, 2023 at 12:41 PM wrote:
> From: qianfan Zhao
>
> v1: 2023-03-02
>
> The first three patches try fix allwinner i2c driver and I already send
> them
> as a sta
RUPT 0 |
CANCEL 0
JOB TIME : 36.82 s
So for me:
Reviewed-by: Niek Linnenbank
Tested-by: Niek Linnenbank
> ---
> tests/avocado/boot_linux_console.py | 47 +
> 1 file changed, 47 insertions(+)
>
> diff --git a/tests/avocado/boot_linux_console.py
>
this
> is
> first part enabling the TWI/I2C bus operation.
>
> Since both Allwinner A10 and H3 use the same module, it is added for
> both boards.
>
> Docs are also updated for Cubieboard and Orangepi-PC board to indicate
> I2C availability.
>
> Signed-off-by: St
Hi Strahinja,
On Thu, Dec 8, 2022 at 8:24 PM Strahinja Jankovic <
strahinjapjanko...@gmail.com> wrote:
> Hi Niek,
>
> On Wed, Dec 7, 2022 at 9:25 PM Niek Linnenbank
> wrote:
> >
> > Hello Strahinja,
> >
> > Thanks for contribution these patc
quot;allwinner-a10.bootrom", buffer, rom_size,
> + rom_size, AW_A10_SRAM_A_BASE,
> + NULL, NULL, NULL, NULL, false);
> +}
>
Its probably fine for now to do it in the same way here for the A10 indeed.
Perhaps in the future, we can try
to share some ov
hese registers and initializes reset values from user's
> guide.
>
> Signed-off-by: Strahinja Jankovic
>
Looks fine to me:
Reviewed-by: Niek Linnenbank
Regards,
Niek
> ---
> hw/arm/Kconfig | 1 +
> hw/arm/allwinner-a10.c | 7 +
> hw
WINNER_A10_CCM
> bool
>
> +config ALLWINNER_A10_DRAMC
> +bool
> +
> source macio/Kconfig
> diff --git a/hw/misc/allwinner-a10-dramc.c b/hw/misc/allwinner-a10-dramc.c
> new file mode 100644
> index 00..e118b0c2fd
> --- /dev/null
> +++ b/hw/misc/allwinner-a10-dramc.c
mplied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
> + * for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> +#ifndef ALLWINNER_I2C_H
> +#define ALLWINNER_I2C_H
> +
> +#include "hw/sysbus.h"
> +#include "qom/object.h"
> +
> +#define TYPE_AW_I2C "allwinner.i2c"
> +OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C)
> +
> +#define AW_I2C_MEM_SIZE 0x24
> +
> +/* Allwinner I2C memory map */
> +#define TWI_ADDR_REG0x00 /* slave address register */
> +#define TWI_XADDR_REG 0x04 /* extended slave address register
> */
> +#define TWI_DATA_REG0x08 /* data register */
> +#define TWI_CNTR_REG0x0c /* control register */
> +#define TWI_STAT_REG0x10 /* status register */
> +#define TWI_CCR_REG 0x14 /* clock control register */
> +#define TWI_SRST_REG0x18 /* software reset register */
> +#define TWI_EFR_REG 0x1c /* enhance feature register */
> +#define TWI_LCR_REG 0x20 /* line control register */
> +
>
If no other modules except for the new driver need these defines, it may be
a good idea to move them to the .c file instead.
Doing so helps avoiding accidental or unintentional use of the defines.
Same for the other flags below.
> +/* Used only in slave mode, do not set */
> +#define TWI_ADDR_RESET 0
> +#define TWI_XADDR_RESET 0
> +
> +/* Data register */
> +#define TWI_DATA_MASK 0xFF
> +#define TWI_DATA_RESET 0
> +
> +/* Control register */
> +#define TWI_CNTR_INT_EN (1 << 7)
> +#define TWI_CNTR_BUS_EN (1 << 6)
> +#define TWI_CNTR_M_STA (1 << 5)
> +#define TWI_CNTR_M_STP (1 << 4)
> +#define TWI_CNTR_INT_FLAG (1 << 3)
> +#define TWI_CNTR_A_ACK (1 << 2)
> +#define TWI_CNTR_MASK 0xFC
> +#define TWI_CNTR_RESET 0
> +
> +/* Status register */
> +#define TWI_STAT_MASK 0xF8
> +#define TWI_STAT_RESET 0xF8
> +
> +/* Clock register */
> +#define TWI_CCR_CLK_M_MASK 0x78
> +#define TWI_CCR_CLK_N_MASK 0x07
> +#define TWI_CCR_MASK0x7F
> +#define TWI_CCR_RESET 0
> +
> +/* Soft reset */
> +#define TWI_SRST_MASK 0x01
> +#define TWI_SRST_RESET 0
> +
> +/* Enhance feature */
> +#define TWI_EFR_MASK0x03
> +#define TWI_EFR_RESET 0
> +
> +/* Line control */
> +#define TWI_LCR_SCL_STATE (1 << 5)
> +#define TWI_LCR_SDA_STATE (1 << 4)
> +#define TWI_LCR_SCL_CTL (1 << 3)
> +#define TWI_LCR_SCL_CTL_EN (1 << 2)
> +#define TWI_LCR_SDA_CTL (1 << 1)
> +#define TWI_LCR_SDA_CTL_EN (1 << 0)
> +#define TWI_LCR_MASK0x3F
> +#define TWI_LCR_RESET 0x3A
> +
> +struct AWI2CState {
> +/*< private >*/
> +SysBusDevice parent_obj;
> +
> +/*< public >*/
> +MemoryRegion iomem;
> +I2CBus *bus;
> +qemu_irq irq;
> +
> +uint8_t addr;
> +uint8_t xaddr;
> +uint8_t data;
> +uint8_t cntr;
> +uint8_t stat;
> +uint8_t ccr;
> +uint8_t srst;
> +uint8_t efr;
> +uint8_t lcr;
> +};
> +
> +#endif /* ALLWINNER_I2C_H */
> --
> 2.30.2
>
>
Regards,
Niek
--
Niek Linnenbank
ft: 0
console: sy8106a: probe of 0-0065 failed with error -110
The SY8106a appears to be an peripheral attached to the I2C bus on the
orangepi-pc, and we don't emulate the SY8106a yet, so that's an error to be
expected:
https://linux-sunxi.org/SY8106A
So for the series:
Tested-by: Niek Li
at 9:03 PM Niek Linnenbank
wrote:
> Hi Paolo,
>
> Thanks for queing this patch. I did not yet see it appear in master. Do
> you know when we can expect to see it?
>
> Regards,
> Niek
>
> On Tue, Feb 1, 2022 at 11:51 AM Paolo Bonzini wrote:
>
>
in memory_region_del_subregion()
> > triggering the next time we call memory_region_readd_subregion().
> >
> > Fix it by using memory_region_add_subregion_common() for readding the
> > region.
> >
> > Reported-by: Niek Linnenbank
> > Fixes: 5ead62185d23 (&
Hi Philippe,
On Mon, Jan 31, 2022 at 12:29 AM Philippe Mathieu-Daudé
wrote:
> Hi Niek!
>
> (+Mark FYI)
>
> On 30/1/22 23:50, Niek Linnenbank wrote:
> > Hi David,
> >
> > While I realize my response is quite late, I wanted to report this error
> > I foun
Hi David,
On Mon, Jan 31, 2022 at 9:11 AM David Hildenbrand wrote:
> On 30.01.22 23:50, Niek Linnenbank wrote:
> > Hi David,
>
> Hi Niek,
>
> thanks for the report.
>
> >
> > While I realize my response is quite late, I wanted to report this error
>
without the assertion.
Would you be able to help out how we can best resolve this? Ofcourse, if
there is anything needed to be changed on the allwinner-h3-dramc.c file, I
would be happy to prepare a patch for that.
Kind regards,
Niek Linnenbank
On Tue, Nov 2, 2021 at 5:46 PM David Hildenbrand wr
with this
information.
However, with commit 5ead62185d reverted, all tested passed fine:
ARMBIAN_ARTIFACTS_CACHED=yes AVOCADO_ALLOW_LARGE_STORAGE=yes avocado
--show=app,console run -t machine:orangepi-pc
tests/avocado/boot_linux_console.py
...
PASS (16.48 s)
RESULTS : PASS 5 | ERROR 0 | FAIL 0 |
Hi Willian,
For the Orange Pi PC documentation:
Reviewed-by: Niek Linnenbank
Op wo 3 nov. 2021 22:14 schreef Willian Rampazzo :
> In the discussion about renaming the `tests/acceptance` [1], the
> conclusion was that the folders inside `tests` are related to the
> framework running
erride the provided DTB for this in
fdt_add_psci_node() in hw/arm/boot.c and the Linux kernel then uses that to
decide between HVC and SMC.
So looks fine to me:
Reviewed-by: Niek Linnenbank
Tested-by: Niek Linnenbank
Regards,
Niek
On Mon, Sep 20, 2021 at 10:39 PM Alexander Graf wrote:
> The
inflate it
>
Only a few typos here:
download -> downloads
inflate -> inflates
Otherwise, looks fine:
Reviewed-by: Niek Linnenbank
+# to 1036 MiB, but 1/ the underlying filesystem is 1552 MiB,
> +# 2/ U-Boot loads TFTP filenames from the last sector below
&
d by the NetBSD
> installer:
> > +# https://wiki.netbsd.org/ports/evbarm/raspberry_pi/#index7h2
> > +# "A 2 GB card is the smallest workable size that the
> installation
> > +# image will fit on."
>
> Do you agree with this comment and t
for test_arm_orangepi_uboot_netbsd9:
Reviewed-by: Niek Linnenbank
Op za 3 jul. 2021 10:44 schreef Philippe Mathieu-Daudé :
> On Sat, Jul 3, 2021 at 10:41 AM Philippe Mathieu-Daudé
> wrote:
> >
> > CC'ing NetBSD maintainers.
> >
> > On 6/23/21 8:
5.10.16 for the acceptance
tests of the orangepi-pc and cubieboard machines.
Signed-off-by: Niek Linnenbank
Reviewed-by: Willian Rampazzo
---
tests/acceptance/boot_linux_console.py | 40 +-
tests/acceptance/replay_kernel.py | 8 +++---
2 files changed, 24 insertions
-sunxi_5.75_armhf.deb
(0.53 s)
This commits removes the ARMBIAN_ARTIFACTS_CACHED pre-condition such that
the acceptance tests for the orangepi-pc and cubieboard machines can run.
Signed-off-by: Niek Linnenbank
Reviewed-by: Willian Rampazzo
---
tests/acceptance/boot_linux_console.py | 12
tests
the transmit queue using the TX_CUR_DESC register in the same way as hardware.
Signed-off-by: Niek Linnenbank
Reviewed-by: Philippe Mathieu-Daudé
---
hw/net/allwinner-sun8i-emac.c | 58 +++
1 file changed, 32 insertions(+), 26 deletions(-)
diff --git a/hw/net
.
Signed-off-by: Niek Linnenbank
Reviewed-by: Willian Rampazzo
---
tests/acceptance/boot_linux_console.py | 72 --
1 file changed, 23 insertions(+), 49 deletions(-)
diff --git a/tests/acceptance/boot_linux_console.py
b/tests/acceptance/boot_linux_console.py
index
Update the download URL of the Armbian 20.08 Bionic image for
test_arm_orangepi_bionic_20_08 of the orangepi-pc machine.
The archive.armbian.com URL contains more images and should keep stable
for a longer period of time than dl.armbian.com.
Signed-off-by: Niek Linnenbank
Reviewed-by: Philippe
tested and should be ready to pull in.
ChangeLog:
v4:
- added Reviewed-By/Tested-By tags
v3:
- fixed the acceptance tests by using up-to-date armbian.com URLs
v2:
- added Reviewed-By tags
- changed URL for artifacts to github.com/nieklinnenbank/QemuArtifacts
Kind regards,
Niek
Niek
Hi Philippe, Willian,
On Mon, Mar 8, 2021 at 8:52 AM Philippe Mathieu-Daudé
wrote:
> On 3/5/21 4:16 PM, Willian Rampazzo wrote:
> > On Thu, Mar 4, 2021 at 5:44 PM Niek Linnenbank
> wrote:
> >>
> >> The image for Armbian 19.11.3 bionic has been removed from the
Hi Philippe, Willian,
Thanks for reviewing!
On Mon, Mar 8, 2021 at 8:50 AM Philippe Mathieu-Daudé
wrote:
> On 3/5/21 4:04 PM, Willian Rampazzo wrote:
> > On Thu, Mar 4, 2021 at 5:45 PM Niek Linnenbank
> wrote:
> >>
> >> The linux kernel 4.20.7 binary f
-sunxi_5.75_armhf.deb
(0.53 s)
This commits removes the ARMBIAN_ARTIFACTS_CACHED pre-condition such that
the acceptance tests for the orangepi-pc and cubieboard machines can run.
Signed-off-by: Niek Linnenbank
---
tests/acceptance/boot_linux_console.py | 12
tests/acceptance/replay_kernel.py
5.10.16 for the acceptance
tests of the orangepi-pc and cubieboard machines.
Signed-off-by: Niek Linnenbank
---
tests/acceptance/boot_linux_console.py | 40 +-
tests/acceptance/replay_kernel.py | 8 +++---
2 files changed, 24 insertions(+), 24 deletions(-)
diff
.
Signed-off-by: Niek Linnenbank
---
tests/acceptance/boot_linux_console.py | 72 --
1 file changed, 23 insertions(+), 49 deletions(-)
diff --git a/tests/acceptance/boot_linux_console.py
b/tests/acceptance/boot_linux_console.py
index eb01286799..9fadea9958 100644
--- a
Update the download URL of the Armbian 20.08 Bionic image for
test_arm_orangepi_bionic_20_08 of the orangepi-pc machine.
The archive.armbian.com URL contains more images and should keep stable
for a longer period of time than dl.armbian.com.
Signed-off-by: Niek Linnenbank
---
tests/acceptance
the transmit queue using the TX_CUR_DESC register in the same way as hardware.
Signed-off-by: Niek Linnenbank
Reviewed-by: Philippe Mathieu-Daudé
---
hw/net/allwinner-sun8i-emac.c | 58 +++
1 file changed, 32 insertions(+), 26 deletions(-)
diff --git a/hw/net
tests by using up-to-date armbian.com URLs
v2:
- added Reviewed-By tags
- changed URL for artifacts to github.com/nieklinnenbank/QemuArtifacts
Kind regards,
Niek
Niek Linnenbank (5):
hw/net/allwinner-sun8i-emac: traverse transmit queue using TX_CUR_DESC
register value
tests/acceptance
Hi Philippe, Thomas, Daniel,
Thank you all. Then I'll just prepare a new version of the patch that uses
currently working archive.armbian.com links.
Kind regards,
Niek
On Thu, Feb 25, 2021 at 10:46 AM Daniel P. Berrangé
wrote:
> On Wed, Feb 24, 2021 at 09:02:51PM +0100, Niek Linnenba
Hi Philippe, Cleber,
On Wed, Feb 24, 2021 at 8:14 PM Cleber Rosa wrote:
> On Wed, Feb 24, 2021 at 10:12:10AM +0100, Philippe Mathieu-Daudé wrote:
> > Hi Niek,
> >
> > On 2/23/21 11:53 PM, Niek Linnenbank wrote:
> > > Currently the automated acceptance tests for the
the transmit queue using the TX_CUR_DESC register in the same way as hardware.
Signed-off-by: Niek Linnenbank
Reviewed-by: Philippe Mathieu-Daudé
---
hw/net/allwinner-sun8i-emac.c | 58 +++
1 file changed, 32 insertions(+), 26 deletions(-)
diff --git a/hw/net
ts to github.com/nieklinnenbank/QemuArtifacts
Kind regards,
Niek
Niek Linnenbank (2):
tests/acceptance: replace unstable apt.armbian.com URLs for
orangepi-pc, cubieboard
hw/net/allwinner-sun8i-emac: traverse transmit queue using TX_CUR_DESC
register value
hw/net/allwinner-sun8i-e
uncertain whether more will be
removed.
This commit moves the artifacts previously stored on apt.armbian.com to github
and retrieves them using the path: '//'.
Signed-off-by: Niek Linnenbank
Reviewed-by: Willian Rampazzo
Reviewed-by: Cleber Rosa
Tested-by: Cleber Rosa
---
tests/
On Fri, Feb 19, 2021 at 7:24 PM Philippe Mathieu-Daudé
wrote:
> Hi Niek,
>
> On 2/17/21 9:57 PM, Niek Linnenbank wrote:
> > Hi Daniel, Philippe,
> >
> > Op di 16 feb. 2021 10:49 schreef Daniel P. Berrangé > <mailto:berra...@redhat.com>>:
> >
>
Hi Daniel, Philippe,
Op di 16 feb. 2021 10:49 schreef Daniel P. Berrangé :
> On Fri, Feb 12, 2021 at 03:10:00PM +0100, Philippe Mathieu-Daudé wrote:
> > Hi Niek and QEMU community,
> >
> > On 2/11/21 11:00 PM, Niek Linnenbank wrote:
> > > The following a
Op vr 12 feb. 2021 15:10 schreef Philippe Mathieu-Daudé :
> Hi Niek and QEMU community,
>
> On 2/11/21 11:00 PM, Niek Linnenbank wrote:
> > The following are maintenance patches for the Allwinner H3. The first
> patch
> > is a proposal to relocate the binary artifacts
facts or a more generic qemu location.
The second patch is a fix for the EMAC that is used by the Allwinner H3 /
Orange Pi PC machine.
Kind regards,
Niek
Niek Linnenbank (2):
tests/acceptance: replace unstable apt.armbian.com URLs for
orangepi-pc, cubieboard
hw/net/allwinner-sun8i-emac
uncertain whether more will be
removed.
This commit moves the artifacts previously stored on apt.armbian.com to a
different
domain that is maintainted by me and retrieves them using the path:
'/pub/qemu//'.
Signed-off-by: Niek Linnenbank
---
tests/acceptance/boot_linux_conso
the transmit queue using the TX_CUR_DESC register in the same way as hardware.
Signed-off-by: Niek Linnenbank
---
hw/net/allwinner-sun8i-emac.c | 58 +++
1 file changed, 32 insertions(+), 26 deletions(-)
diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net
For Orange Pi PC:
Reviewed-by: Niek Linnenbank
Op zo 31 jan. 2021 19:45 schreef Philippe Mathieu-Daudé :
> Most of ARM machines display their CPU when QEMU list the available
> machines (-M help). Some machines do not. Fix to unify the help
> output.
>
> Signed-off-by: Philipp
Hi Philippe, Thomas,
Op vr 27 nov. 2020 18:57 schreef Philippe Mathieu-Daudé :
> On 11/27/20 6:47 PM, Thomas Huth wrote:
> > On 27/11/2020 18.41, Philippe Mathieu-Daudé wrote:
> >> We lately realized that the Avocado framework was not designed
> >> to be regularly run on CI environments. Therefor
Op vr 20 nov. 2020 16:46 schreef Philippe Mathieu-Daudé :
> Fixes: 0553ef42571 ("docs: add Orange Pi PC document")
> Signed-off-by: Philippe Mathieu-Daudé
>
Reviewed-by: Niek Linnenbank
---
> Cc: Niek Linnenbank
> ---
> MAINTAINERS | 2 +-
> 1 file chan
@@ static void sd_function_switch(SDState *sd, uint32_t
> arg)
> > sd->data[12] = 0x80;/* Supported group 1 functions */
> > sd->data[13] = 0x03;
> >
> > +memset(&sd->data[14], 0, 3);
> > for (i = 0; i < 6; i ++) {
> > new_func = (arg >> (i * 4)) & 0x0f;
> > if (mode && new_func != 0x0f)
> >
>
> Thanks, series applied to sd-next tree.
>
>
--
Niek Linnenbank
Hi Philippe,
I've tested the patch by Bin on the 2G & Sd blocksize issue, see my
response there.
https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg07318.html
So probably we do not need the patch I send here.
Regards,
Niek
On Mon, Oct 26, 2020 at 12:48 AM Niek Linnenba
these tests it looks to me that the change is working as expected. I'm
not an expert on SD internals
so perhaps Philippe would like to give more detailed review comments on the
code itself.
So for the Orange Pi PC machine & acceptance tests:
Tested-by: Niek Linnenbank
Regards,
Niek
Hello Philippe,
On Sun, Oct 25, 2020 at 1:11 PM Philippe Mathieu-Daudé
wrote:
> On 10/25/20 2:31 AM, Philippe Mathieu-Daudé wrote:
> > Hi Niek,
> >
> > On 10/24/20 11:52 PM, Niek Linnenbank wrote:
> >> The acceptance tests for the Orange Pi PC need to expand the
Hi Bin,
On Sun, Oct 25, 2020 at 3:17 AM Bin Meng wrote:
> Hi Niek,
>
> On Sun, Oct 25, 2020 at 5:01 AM Niek Linnenbank
> wrote:
> >
> > Hi Philippe,
> >
> > I have ran this series with the new Armbian 20.08 test and noticed this
> failure:
> >
>
2.0977679] vfs_mountroot: can't open root device
console: [ 2.0977679] cannot mount root, error = 6
INTERRUPTED: Test interrupted by SIGTERM\nRunner error occurred: Timeout
reached.
Signed-off-by: Niek Linnenbank
Based-on: ("[RFC PATCH 0/4] tests/acceptance: Test U-Boot/Linux f
Hi Philippe,
On Fri, Oct 23, 2020 at 11:34 AM Philippe Mathieu-Daudé
wrote:
> On 10/23/20 11:23 AM, Philippe Mathieu-Daudé wrote:
> > On 10/23/20 4:02 AM, Bin Meng wrote:
> >> Hi Niek,
> >>
> >> On Thu, Oct 22, 2020 at 11:20 PM Niek Linnenbank
>
Tested-by: Niek Linnenbank
Reviewed-by: Niek Linnenbank
On Fri, Oct 23, 2020 at 3:18 PM Philippe Mathieu-Daudé
wrote:
> This reverts commit b638627c723a8d0d2bb73489bc6bf9ff09b8d53a.
>
> Currently booting U-Boot on the Orange Pi PC we get:
>
> console: U-Boot SPL 2020.04-armbi
As a temporary solution this should be fine, until we have decided on which
reliable storage location to use.
Reviewed-by: Niek Linnenbank
On Fri, Oct 23, 2020 at 3:18 PM Philippe Mathieu-Daudé
wrote:
> Unfortunately the Armbian 19.11.3 image has been removed from the
> dl.armbian.co
h_asset(image_url, asset_hash=image_hash,
> + algorithm='sha256')
> +image_path = archive.extract(image_path_xz, self.workdir)
> +image_pow2ceil_expand(image_path)
> +
> +self.do_test_arm_orangepi_uboot_armbian(image_path)
> +
> @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage
> limited')
> def test_arm_orangepi_uboot_netbsd9(self):
> """
> --
> 2.26.2
>
>
--
Niek Linnenbank
Hi Bin, Philippe,
If im correct the acceptance tests for orange pi need to be run with a flag
ARMBIAN_ARTIFACTS_CACHED set that explicitly allows them to be run using
the armbian mirror. So if you pass that flag on the same command that
Philippe gave, the rests should run.
I have a follow up ques
Acked-by: Niek Linnenbank
Op zo 4 okt. 2020 20:25 schreef Philippe Mathieu-Daudé :
> These individual contributors have a number of contributions,
> add them to the 'individual' group map.
>
> Cc: Ahmed Karaman
> Cc: Aleksandar Markovic
> Cc: Alistair Francis
DECLARE_TYPE().
>
> Rename all the constants to AW_H3_DEV_*, to avoid conflicts.
>
> Reviewed-by: Daniel P. Berrangé
>
Reviewed-by: Niek Linnenbank
> Signed-off-by: Eduardo Habkost
> ---
> Changes v1 -> v2:
> * Added more details to commit message
>
> ---
> Cc:
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