Yes, that's fine by me.
--Mark Langsdorf
Calxeda, Inc.
From: Andreas Färber [afaer...@suse.de]
Sent: Thursday, June 07, 2012 8:45 AM
To: Mark Langsdorf
Cc: qemu-devel@nongnu.org; peter.mayd...@linaro.org; Rob Herring; Paolo Bonzini
Subject: Re:
On 03/12/2012 11:47 AM, Andreas Färber wrote:
> Am 12.03.2012 17:33, schrieb Mark Langsdorf:
>> Allow load_image_targphys to load files on systems with more than 2G of
>> emulated memory by changing the max_sz parameter from an int to an
>> uint64_t.
>>
>> Sign
Odd that I wasn't actually cc'd by the mailer on this.
Do you want me to pull together a patch to make it a QOM property now,
or is there some other dependency I should wait on? It may take me a
week or so to get time to pull it together and test it.
--Mark Langsdorf
Calxeda, Inc.
On
Please include a change log below the commit line so we know
what you changed. Thank you.
More comments below.
--Mark Langsdorf
Calxeda, Inc.
On 03/14/2012 06:58 AM, Alexey Starikovskiy wrote:
> Sufficient to boot Linux kernel on vexpress-a15
>
> Missing:
> * Extends the DBGDRAR an
From: Joshua Housh
Make sure a BusInfo exists before trying to dereference it.
Signed-off-by: Joshua Housh
Signed-off-by: Mark Langsdorf
---
hw/qdev.c |9 ++---
1 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/qdev.c b/hw/qdev.c
index ee21d90..6c3d02f 100644
--- a/hw
From: Joshua Housh
There are no users of i2c_slave.
Signed-off-by: Joshua Housh
Signed-off-by: Mark Langsdorf
---
qemu-common.h |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/qemu-common.h b/qemu-common.h
index b0fdf5c..c9e96a8 100644
--- a/qemu-common.h
+++ b/qemu
On 03/13/2012 06:19 AM, Alexey Starikovskiy wrote:
The entire patch repeatedly fails scripts/checkpatch. More comments
below.
--Mark Langsdorf
Calxeda, Inc.
> Minimal ARM LPAE support. Sufficient to boot Linux kernel on vexpress-a15
>
> Signed-off-by: Alexey Starikovskiy
> ---
&g
be updated to use uint64_t. (The
> arm_boot device tree code needs updating too, to check whether
> the dtb is using 32 bit or 64 bit cell sizes for its RAM size).
> I'm happy to put together a patch to do this at some point if
> Mark doesn't already have one lined up.
I don't have one lined up for that.
--Mark Langsdorf
Calxeda, Inc.
Allow load_image_targphys to load files on systems with more than 2G of
emulated memory by changing the max_sz parameter from an int to an
uint64_t.
Signed-off-by: Mark Langsdorf
---
Changes from v2
changed max_sz from target_phys_addr_t to uint64_t
Changes from v1
changed max_sz
ed DRAM?
I've fired off 3 versions of a patch that answers that question, some
of which I've liked more than others. I'm willing to do a reasonable
amount of refactoring the general QEMU image loading code, but I don't
want to do that until I have a sense that the maintainers agree on the
general solution and that I'm working toward their understand.
Thanks for thinking this over.
--Mark Langsdorf
Calxeda, Inc.
On 03/09/2012 10:13 AM, Peter Maydell wrote:
> On 9 March 2012 15:57, Mark Langsdorf wrote:
>> Since the ram_size field of arm_boot_info is only an int, don't set
>> that field to more than INT_MAX. Signed vs unsigned comparison
>> overruns are possible otherwis
Since the ram_size field of arm_boot_info is only an int, don't set
that field to more than INT_MAX. Signed vs unsigned comparison
overruns are possible otherwise.
Signed-off-by: Mark Langsdorf
---
hw/highbank.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git
On 03/09/2012 08:17 AM, Markus Armbruster wrote:
> Mark Langsdorf writes:
>
>> On 03/09/2012 03:25 AM, Markus Armbruster wrote:
>>> get_image_size() returns int. How does widening size and max_sz here
>>> improve things?
>>
>> If max_sz is greater th
Allow load_image_targphys to load files on systems with more than 2G of
emulated memory by changing the max_sz parameter from an int to an
unsigned long.
Signed-off-by: Mark Langsdorf
---
The other loaders in hw/loader.h did not look they had a similar issue.
Changes from v1
changed
On 03/09/2012 07:21 AM, Alexander Graf wrote:
>
> On 09.03.2012, at 14:15, Mark Langsdorf wrote:
>
>> On 03/09/2012 03:25 AM, Markus Armbruster wrote:
>>> Mark Langsdorf writes:
>>>
>>>> Allow load_image_targphys to load files on systems with more th
On 03/09/2012 03:25 AM, Markus Armbruster wrote:
> Mark Langsdorf writes:
>
>> Allow load_image_targphys to load files on systems with more than 2G of
>> emulated memory by changing the max_sz parameter from an int to an
>> unsigned long.
>>
>> Signed-o
On 03/08/2012 11:56 AM, Eric Blake wrote:
> On 03/08/2012 09:59 AM, Mark Langsdorf wrote:
>> Allow load_image_targphys to load files on systems with more than 2G of
>> emulated memory by changing the max_sz parameter from an int to an
>> unsigned long.
>
> unsigned lo
Allow load_image_targphys to load files on systems with more than 2G of
emulated memory by changing the max_sz parameter from an int to an
unsigned long.
Signed-off-by: Mark Langsdorf
---
hw/loader.c |4 ++--
hw/loader.h |3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff
Signed-off-by: Mark Langsdorf
---
Changes from v1
Put entry in alphabetical order
Added maintainership of hw/xgmac
MAINTAINERS |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 173e893..74ee059 100644
--- a/MAINTAINERS
Signed-off-by: Mark Langsdorf
---
MAINTAINERS |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 173e893..bdc254f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -237,6 +237,11 @@ M: Peter Maydell
S: Maintained
F: hw/versatilepb.c
This patch series adds support for the Calxeda Highbank SoC.
Makefile.target |2 +
hw/arm-misc.h | 17 ++
hw/arm_boot.c | 65 ++--
hw/highbank.c | 330
hw/ide/ahci.c | 44 ++
hw/xgmac.c | 421 +++
Create two functions, write_secondary_boot() and secondary_cpu_reset_hook(),
to allow platforms more control of how secondary CPUs are brought up. The
new functions default to NULL and aren't called unless they are populated
so there are no changes to existing platform models.
Signed-off-by:
Long term, the config_base_register will be a QDM parameter. In the
meantime, models that use it need to be able to preserve it across
cpu_reset() calls.
Signed-off-by: Mark Langsdorf
---
Changes from v13
Make save/restore unconditional
Changes from v1-v12
Skipped
target-arm
From: Rob Herring
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v13
Removed no_vga parameter
Really reverted board_id to -1
Changes from v12
Reverted board_id to -1. Added comments clarifying why
From: Peter Maydell
Support passing a board ID value to the kernel in r1
that is more than 16 bits wide. This is needed to pass
the '-1 == invalid' value for boards which only support
device tree booting.
Signed-off-by: Peter Maydell
Tested-by: Mark Langsdorf
---
Changes from v13
From: Rob Herring
This adds very basic support for the xgmac ethernet core. Missing things
include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring
Signed-off-by: Mark
From: Rob Herring
Add support for ahci on sysbus.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Andreas Färber
---
Changes from v10-v13
None
Changes from v9
Changed typedef struct names to CamelCase
Changes from v7, v8
None
Changes from v5, v6
From: Rob Herring
Add support for ahci on sysbus.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Andreas Färber
---
Changes from v10-v12
None
Changes from v9
Changed typedef struct names to CamelCase
Changes from v7, v8
None
Changes from v5, v6
Create two functions, write_secondary_boot() and secondary_cpu_reset_hook(),
to allow platforms more control of how secondary CPUs are brought up. The
new functions default to NULL and aren't called unless they are populated
so there are no changes to existing platform models.
Signed-off-by:
From: Peter Maydell
Support passing a board ID value to the kernel in r1
that is more than 16 bits wide. This is needed to pass
the '-1 == invalid' value for boards which only support
device tree booting.
Signed-off-by: Peter Maydell
Tested-by: Mark Langsdorf
---
Changes f
From: Rob Herring
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v12
Reverted board_id to -1. Added comments clarifying why this is legal.
Changes from v11
Provided a meaningful board ID
Added com
From: Rob Herring
This adds very basic support for the xgmac ethernet core. Missing things
include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring
Signed-off-by: Mark
Long term, the config_base_register will be a QDM parameter. In the
meantime, models that use it need to be able to preserve it across
cpu_reset() calls.
Signed-off-by: Mark Langsdorf
---
Changes from v1-v12
Skipped
target-arm/helper.c |7 +++
1 files changed, 7 insertions
This patch series adds support for the Calxeda Highbank SoC.
Makefile.target |2 +
hw/arm-misc.h | 17 ++
hw/arm_boot.c | 65 ++--
hw/highbank.c | 331
hw/ide/ahci.c | 44 ++
hw/xgmac.c | 421 +++
On 01/20/2012 10:58 AM, Peter Maydell wrote:
> On 20 January 2012 16:57, Mark Langsdorf wrote:
>> On 01/20/2012 10:27 AM, Peter Maydell wrote:
>>> It's still not clear to me from this conversation if the right
>>> answer is "0", "-1" or "a
+ SCU_CONFIG (0xfee4) as the value of smpboot[0]. It seems to be
bypassing the a9mpcore.c code entirely. I'm not sure what's happening
there.
--Mark Langsdorf
Calxeda, Inc.
On 01/20/2012 10:27 AM, Peter Maydell wrote:
> On 20 January 2012 16:25, Mark Langsdorf wrote:
>> On 01/20/2012 07:48 AM, Rob Herring wrote:
>>> On 01/20/2012 02:47 AM, Peter Maydell wrote:
>>>> On 19 January 2012 23:17, Rob Herring wrote:
>>>>>
On 01/20/2012 07:48 AM, Rob Herring wrote:
> On 01/20/2012 02:47 AM, Peter Maydell wrote:
>> On 19 January 2012 23:17, Rob Herring wrote:
>>> On 01/19/2012 03:44 PM, Peter Maydell wrote:
>>>> On 19 January 2012 21:31, Mark Langsdorf
>>>> wrote:
>&
From: Rob Herring
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v11
Provided a meaningful board ID
Added comments on the way the device tree memory values interact with
qemu command line arguments for m
From: Rob Herring
This adds very basic support for the xgmac ethernet core. Missing things
include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring
Signed-off-by: Mark
This patch series adds support for the Calxeda Highbank SoC.
Makefile.target |2 +
hw/arm-misc.h | 17 +++
hw/arm_boot.c | 54 ++--
hw/highbank.c | 327 ++
hw/ide/ahci.c | 44 ++
hw/xgmac.c | 421
Create two functions, write_secondary_boot() and secondary_cpu_reset_hook(),
to allow platforms more control of how secondary CPUs are brought up. The
new functions default to NULL and aren't called unless they are populated
so there are no changes to existing platform models.
Signed-off-by:
From: Rob Herring
Add support for ahci on sysbus.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Andreas Färber
---
Changes from v10
None
Changes from v9
Changed typedef struct names to CamelCase
Changes from v7, v8
None
Changes from v5, v6
On 01/19/2012 01:59 PM, Peter Maydell wrote:
> On 19 January 2012 19:58, Mark Langsdorf wrote:
>> On 01/19/2012 01:44 PM, Peter Maydell wrote:
>>> I have a kernel now that seems to boot but then
>>> barfs with:
>>> Freeing init memory: 124K
>>> Kerne
On 01/19/2012 01:44 PM, Peter Maydell wrote:
> On 19 January 2012 19:35, Mark Langsdorf wrote:
>> On 01/19/2012 01:32 PM, Peter Maydell wrote:
>>> On 19 January 2012 19:25, Mark Langsdorf wrote:
>>>> On 01/19/2012 01:15 PM, Peter Maydell wrote:
>>>>
On 01/19/2012 01:32 PM, Peter Maydell wrote:
> On 19 January 2012 19:25, Mark Langsdorf wrote:
>> On 01/19/2012 01:15 PM, Peter Maydell wrote:
>>> On 19 January 2012 15:43, Mark Langsdorf wrote:
>>>> +highbank_binfo.board_id = -1; /* provided by deviceTree
On 01/19/2012 01:15 PM, Peter Maydell wrote:
> On 19 January 2012 15:43, Mark Langsdorf wrote:
>> +highbank_binfo.board_id = -1; /* provided by deviceTree */
>
> This doesn't work, because arm_boot.c does:
> bootloader[1] |= info->board_id & 0xff;
&g
Create two functions, write_secondary_boot() and secondary_cpu_reset_hook(),
to allow platforms more control of how secondary CPUs are brought up. The
new functions default to NULL and aren't called unless they are populated
so there are no changes to existing platform models.
Signed-off-by:
appropriately.
Set the maximum theoretical number of GIC interrupts to 1020 and
update the save/restore code to only use the appropriate number for
each SoC.
Signed-off-by: Mark Langsdorf
Reviewed-by: Andreas Färber
Reviewed-by: Peter Maydell
---
Changes from v9, v10
None
Changes from v8
From: Rob Herring
Add support for ahci on sysbus.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Andreas Färber
---
Changes from v10
None
Changes from v9
Changed typedef struct names to CamelCase
Changes from v7, v8
None
Changes from v5, v6
The current comment says that the arm_timers are restricted to between
32 KHz and 1 MHz, but sp804 TRM does not specify those limits.
Signed-off-by: Mark Langsdorf
Reviewed-by: Andreas Färber
---
Changes from v7-v10
None
Changes from v2-v6
Skipped
Changes from v1
From: Rob Herring
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v10
Added secondary core boot functions
Changes from v9
Made typedef struct names in CamelCase
Changes from v7, v8
None
Changes fr
From: Rob Herring
This adds very basic support for the xgmac ethernet core. Missing things
include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring
Signed-off-by: Mark
This patch series adds support for the Calxeda Highbank SoC.
On 01/18/2012 01:26 PM, Peter Maydell wrote:
> On 18 January 2012 19:06, Mark Langsdorf wrote:
>> On 01/18/2012 08:53 AM, Peter Maydell wrote:
>>> On 18 January 2012 14:35, Mark Langsdorf wrote:
>>>> I can set the smp_loader code so that I can boot 2 cpus
>>&g
On 01/18/2012 08:53 AM, Peter Maydell wrote:
> On 18 January 2012 14:35, Mark Langsdorf wrote:
>> I can set the smp_loader code so that I can boot 2 cpus
>> and verify their existence in /proc/cpuinfo, but I can't
>> get 3 cpus to boot at all, no matter how I hack the
Create two functions, write_secondary_boot() and secondary_cpu_reset_hook(),
to allow platforms more control of how secondary CPUs are brought up. The
new functions default to NULL and aren't called unless they are populated
so there are no changes to existing platform models.
Signed-off-by:
On 01/18/2012 08:53 AM, Peter Maydell wrote:
> On 18 January 2012 14:35, Mark Langsdorf wrote:
>> Is there a good example of how to write secondary smp boot
>> code other than arm_boot.c? Should I just expect to pull
>> most of arm_boot.c into highbank and adjust from ther
On 01/17/2012 09:13 AM, Peter Maydell wrote:
> On 17 January 2012 13:50, Mark Langsdorf wrote:
>> +highbank_binfo.ram_size = ram_size;
>> +highbank_binfo.kernel_filename = kernel_filename;
>> +highbank_binfo.kernel_cmdline = kernel_cmdline;
>> +hig
From: Rob Herring
Add support for ahci on sysbus.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Andreas Färber
---
Changes from v9
Changed typedef struct names to CamelCase
Changes from v7, v8
None
Changes from v5, v6
Skipped
Changes from v4
appropriately.
Set the maximum theoretical number of GIC interrupts to 1020 and
update the save/restore code to only use the appropriate number for
each SoC.
Signed-off-by: Mark Langsdorf
Reviewed-by: Andreas Färber
Reviewed-by: Peter Maydell
---
Changes from v9
None
Changes from v8
From: Rob Herring
This adds very basic support for the xgmac ethernet core. Missing things
include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring
Signed-off-by: Mark
From: Rob Herring
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Peter Maydell
---
Changes from v9
Made typedef struct names in CamelCase
Changes from v7, v8
None
Changes from v3, v4, v5, v6
Sk
The current comment says that the arm_timers are restricted to between
32 KHz and 1 MHz, but sp804 TRM does not specify those limits.
Signed-off-by: Mark Langsdorf
Reviewed-by: Andreas Färber
---
Changes from v7, v8, v9
None
Changes from v2, v3, v4, v5, v6
Skipped
Changes from
This patch series adds support for the Calxeda Highbank SoC.
From: Rob Herring
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Peter Maydell
---
Changes from v1, v2, v3, v4, v5, v6
Skipped
target-arm/cpu.h |3 ++-
target-arm/helper.c |9 +
target-arm/machine.c |2 ++
3 files changed, 13
This patch series adds support for the Calxeda Highbank SoC.
It depends on my previous patch series "various ARM fixes for
Calxeda Highbank" and "ahci: convert ahci_reset to use AHCIState".
Some of the patches are carried voer from "Various ARM fixes
for Calxeda Highbank" and were reviewed but not
This patch series adds support for the Calxeda Highbank SoC.
It depends on my previous patch series "various ARM fixes for
Calxeda Highbank" and "ahci: convert ahci_reset to use AHCIState".
Some of the patches are carried voer from "Various ARM fixes
for Calxeda Highbank" and were reviewed but not
The current comment says that the arm_timers are restricted to between
32 KHz and 1 MHz, but sp804 TRM does not specify those limits.
Signed-off-by: Mark Langsdorf
---
Changes from v1
Clarified the commit message
hw/arm_timer.c |3 ---
1 files changed, 0 insertions(+), 3 deletions
This adds very basic support for the xgmac ethernet core. Missing things
include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed
From: Rob Herring
Add support for ahci on sysbus.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Andreas Färber
---
Changes from v5, v6
Skipped
Changes from v4
replaced all references to Plat|plat_ with sysbus_
made the number of ports into a
From: Rob Herring
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Peter Maydell
---
Changes from v7, v8
None
Changes from v1, v2, v3, v4, v5, v6
Skipped
target-arm/cpu.h |3 ++-
target-arm/helper.c |9 +
target-arm/machine.c |2
From: Rob Herring
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v3, v4, v5, v6
Skipped
Changes from v2
Created a reset function for highbank_regs
Handled creation of regs i/o memory region
This adds very basic support for XG-mac ethernet core from Synopsis and
others. Missing things include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring
Signed-off-by: Mark
The current comment says that the arm_timers are restricted to between
32 KHz and 1 MHz, but sp804 TRM does not specify those limits.
Signed-off-by: Mark Langsdorf
Reviewed-by: Andreas Färber
---
Changes from v2, v3, v4, v5, v6
Skipped
Changes from v1
Clarified the commit
This adds very basic support for XG-mac ethernet core from Synopsis and
others. Missing things include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring
Signed-off-by: Mark
appropriately.
Set the maximum theoretical number of GIC interrupts to 1020 and
update the save/restore code to only use the appropriate number for
each SoC.
Signed-off-by: Mark Langsdorf
---
Changes from v6
Removed trailing whitespace
armv7m_nvic uses num_irq properly
Some
From: Rob Herring
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
target-arm/cpu.h |3 ++-
target-arm/helper.c |9 +
target-arm/machine.c |2 ++
3 files changed, 13 insertions(+), 1 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index
appropriately.
Set the maximum theoretical number of GIC interrupts to 1020 and
update the save/restore code to only use the appropriate number for
each SoC.
Signed-off-by: Mark Langsdorf
Reviewed-by: Andreas Färber
---
Changes from v8
Removed comments about armv7m_nvic's external IRQ
From: Rob Herring
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Peter Maydell
---
Changes from v7, v8
None
Changes from v3, v4, v5, v6
Skipped
Changes from v2
Created a reset function for highbank
From: Rob Herring
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v1
Restructed the loading of sysram.bin and made it more clearly optional
Made the regs structure into a proper qdev/sysbus o
This patch series adds support for the Calxeda Highbank SoC.
It depends on my previous patch series "various ARM fixes for
Calxeda Highbank" and "ahci: convert ahci_reset to use AHCIState".
Some of the patches are carried over from "Various ARM fixes
for Calxeda Highbank" and were reviewed but not
From: Rob Herring
Add support for ahci on sysbus.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Andreas Färber
---
Changes from v7, v8
None
Changes from v5, v6
Skipped
Changes from v4
replaced all references to Plat|plat_ with sysbus_
The current comment says that the arm_timers are restricted to between
32 KHz and 1 MHz, but sp804 TRM does not specify those limits.
Signed-off-by: Mark Langsdorf
Reviewed-by: Andreas Färber
---
Changes from v7, v8
None
Changes from v2, v3, v4, v5, v6
Skipped
Changes from v1
From: Rob Herring
Add support for ahci on sysbus.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v4
replaced all references to Plat|plat_ with sysbus_
made the number of ports into a qdev property
added dummy migration support
Changes from v3
appropriately.
Set the maximum theoretically number of GIC interrupts to 1020 and
update the save/restore code to only use the appropriate number for
each SoC.
Signed-off-by: Mark Langsdorf
---
Changes from v5
Clarify the commit message
Rename GIC_NIRQ to GIC_MAXIRQ and change usage
appropriately.
Set the maximum theoretically number of GIC interrupts to 1020 and
update the save/restore code to only use the appropriate number for
each SoC.
Signed-off-by: Mark Langsdorf
---
Changes from v7
Removed unnecessary vmstate_register
Changes from v6
Removed trailing
This patch series adds support for the Calxeda Highbank SoC.
It depends on my previous patch series "various ARM fixes for
Calxeda Highbank" and "ahci: convert ahci_reset to use AHCIState".
Some of the patches are carried voer from "Various ARM fixes
for Calxeda Highbank" and were reviewed but not
From: Rob Herring
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v7
None
Changes from v3, v4, v5, v6
Skipped
Changes from v2
Created a reset function for highbank_regs
Handled creation of
The current comment says that the arm_timers are restricted to between
32 KHz and 1 MHz, but sp804 TRM does not specify those limits.
Signed-off-by: Mark Langsdorf
Reviewed-by: Andreas Färber
---
Changes from v7
None
Changes from v2, v3, v4, v5, v6
Skipped
Changes from v1
This adds very basic support for XG-mac ethernet core from Synopsis and
others. Missing things include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring
Signed-off-by: Mark
From: Rob Herring
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Peter Maydell
---
Changes from v7
None
Changes from v1, v2, v3, v4, v5, v6
Skipped
target-arm/cpu.h |3 ++-
target-arm/helper.c |9 +
target-arm/machine.c |2
From: Rob Herring
Add support for ahci on sysbus.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Andreas Färber
---
Changes from v7
None
Changes from v5, v6
Skipped
Changes from v4
replaced all references to Plat|plat_ with sysbus_
made
appropriately.
Set the maximum theoretically number of GIC interrupts to 1020 and
update the save/restore code to only use the appropriate number for
each SoC.
Signed-off-by: Mark Langsdorf
---
Changes from v5
Clarify the commit message
Rename GIC_NIRQ to GIC_MAXIRQ and change usage
This adds very basic support for XG-mac ethernet core from Synopsis and
others. Missing things include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring
Signed-off-by: Mark
From: Rob Herring
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
target-arm/cpu.h |3 ++-
target-arm/helper.c |9 +
target-arm/machine.c |2 ++
3 files changed, 13 insertions(+), 1 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index
From: Rob Herring
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v1
Restructed the loading of sysram.bin and made it more clearly optional
Made the regs structure into a proper qdev/sysbus o
Signed-off-by: Mark Langsdorf
---
hw/arm_timer.c |3 ---
1 files changed, 0 insertions(+), 3 deletions(-)
diff --git a/hw/arm_timer.c b/hw/arm_timer.c
index 60e1c63..15d493f 100644
--- a/hw/arm_timer.c
+++ b/hw/arm_timer.c
@@ -272,11 +272,8 @@ static int sp804_init(SysBusDevice *dev
From: Rob Herring
Add support for ahci on sysbus.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v3
Renamed plat-ahci to sysbus-ahci
Changes from v1, v2
Corrected indentation of PlatAHCIState members
Made plat_ahci_info into a single
This patch series adds support for the Calxeda Highbank SoC.
It depends on my previous patch series "various ARM fixes for
Calxeda Highbank" and "ahci: convert ahci_reset to use AHCIState".
Some of the patches are carried voer from "Various ARM fixes
for Calxeda Highbank" and were reviewed but not
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