On 01/18/2012 01:26 PM, Peter Maydell wrote: > On 18 January 2012 19:06, Mark Langsdorf <mark.langsd...@calxeda.com> wrote: >> On 01/18/2012 08:53 AM, Peter Maydell wrote: >>> On 18 January 2012 14:35, Mark Langsdorf <mark.langsd...@calxeda.com> wrote: >>>> I can set the smp_loader code so that I can boot 2 cpus >>>> and verify their existence in /proc/cpuinfo, but I can't >>>> get 3 cpus to boot at all, no matter how I hack the existing >>>> arm_boot code. >>> >>> Right, multiple secondary cores requires multiple addresses >>> to be polled which we don't support in arm_boot.c at the moment. >> >> How would multiple polling supposed to work? > > You need several separate bits of code, to put each secondary > core in a different loop polling a different address. > (If you have access to your own bootloader sources you should > be able to see how it does it :-))
I wasn't sure if polling was done on the QEMU side. I can pull code from the bootloader. >> I've tried changing >> http://lxr.linux.no/#linux+v3.2.1/arch/arm/mach-highbank/highbank.c#L71 >> to point to a fixed address (0x50), and the boot loader still fails >> if there are 2 or more secondary CPUs. > > Yeah, that's insufficient, because the highbank kernel doesn't > >> I've figured out that do_cpu_reset() is only called once, even >> though that seems a bit strange to me. > > It should be called once per core -- we register it with > qemu_register_reset() for each core at the bottom of arm_load_kernel(). > The reason it isn't in your case is a bug in highbank.c -- you should > be passing first_cpu as the first parameter to arm_load_kernel(). As it turns out, the highbank simulation will boot all 4 cores if I make the change to pass first_cpu and change the Linux code to use 0x40 for all 4 CPUs. Which is gratifying if a little surprising. With that straightened out, I can go work on translating the polling code to opcodes. Thanks for the pointers. --Mark Langsdorf Calxeda, Inc.
