[PATCH v2 4/4] Add a config option for ePMP.

Add a config option to enable experimental support for ePMP. This is disabled by default and can be enabled with 'x-epmp=true'. Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin --- target/riscv/cpu.c | 9 + target/riscv/cpu.h | 3 ++

[PATCH v2 1/4] Define ePMP mseccfg

Currently using 0x390 and 0x391 for x-epmp (experimental). This may change in the future spec. Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin --- target/riscv/cpu_bits.h | 3 +++ target/riscv/gdbstub.c | 2 ++ 2 files changed, 5 insertions(+) diff

[PATCH v2 2/4] Implementation of enhanced PMP(ePMP) support

The ePMP can be found in: https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8/edit#heading=h.9wsr1lnxtwe2 Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin --- target/riscv/pmp.c| 134

[PATCH v2 0/4] riscv: Add enhanced PMP support

v1 -> v2 : * regenerate this patch based on the latest upstream Hou Weiying (4): Define ePMP mseccfg Implementation of enhanced PMP(ePMP) support Add ePMP CSR accesses Add a config option for ePMP. target/riscv/cpu.c| 9 ++ target/riscv/cpu.h| 3 + target/ri

[PATCH v2 3/4] Add ePMP CSR accesses

Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin --- target/riscv/csr.c | 18 ++ target/riscv/pmp.c | 40 2 files changed, 58 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index

[PATCH] riscv: Fix bug in setting pmpcfg CSR for RISCV64

it as a bug. We are looking for constant (e.g., define a new constant named RISCV_WORD_SIZE) in QEMU to help others understand code better, but none was found. A possible good explanation of this literal is it is the minimum word length on riscv is 4 bytes (32 bit). Signed-off-by: Hongzheng-Li Signed

[PATCH] riscv: Fix bug in setting pmpcfg CSR for RISCV64

it as a bug. We are looking for constant (e.g., define a new constant named RISCV_WORD_SIZE) in QEMU to help others understand code better, but none was found. A possible good explanation of this literal is it is the minimum word length on riscv is 4 bytes (32 bit). Signed-off-by: Hongzheng-Li Signed

[PATCH 1/4] Define ePMP mseccfg

Currently using 0x390 and 0x391 for x-epmp (experimental). This may change in the future spec. Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin --- target/riscv/cpu_bits.h | 3 +++ target/riscv/gdbstub.c | 2 ++ 2 files changed, 5 insertions(+) diff

[PATCH 1/4] Define ePMP mseccfg

Currently using 0x390 and 0x391 for x-epmp (experimental). This may change in the future spec. Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin --- target/riscv/cpu_bits.h | 3 +++ target/riscv/gdbstub.c | 2 ++ 2 files changed, 5 insertions(+) diff

[PATCH 3/4] Add ePMP CSR accesses

Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin --- target/riscv/csr.c | 18 ++ target/riscv/pmp.c | 40 2 files changed, 58 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index

[PATCH 2/4] Implementation of enhanced PMP(ePMP) support

The ePMP can be found in: https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8/edit#heading=h.9wsr1lnxtwe2 Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin --- target/riscv/pmp.c| 134

[PATCH 4/4] Add a config option for ePMP.

Add a config option to enable experimental support for ePMP. This is disabled by default and can be enabled with 'x-epmp=true'. Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin --- target/riscv/cpu.c | 9 + target/riscv/cpu.h | 3 ++

[PATCH 0/4] riscv: Add enhanced PMP support

The ePMP can be found in: https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8/edit#heading=h.9wsr1lnxtwe2 Hou Weiying (4): Define ePMP mseccfg Implementation of enhanced PMP(ePMP) support Add ePMP CSR accesses Add a config option for ePMP. target/riscv/cpu.c

[PATCH 0/4] riscv: Add enhanced PMP support

The ePMP can be found in: https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8/edit#heading=h.9wsr1lnxtwe2 Hou Weiying (4): Define ePMP mseccfg Implementation of enhanced PMP(ePMP) support Add ePMP CSR accesses Add a config option for ePMP. target/riscv/cpu.c

[PATCH 3/4] Add ePMP CSR accesses

Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin --- target/riscv/csr.c | 18 ++ target/riscv/pmp.c | 40 2 files changed, 58 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index

[PATCH 2/4] Implementation of enhanced PMP(ePMP) support

The ePMP can be found in: https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8/edit#heading=h.9wsr1lnxtwe2 Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin --- target/riscv/pmp.c| 134

[PATCH 4/4] Add a config option for ePMP.

Add a config option to enable experimental support for ePMP. This is disabled by default and can be enabled with 'x-epmp=true'. Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin --- target/riscv/cpu.c | 9 + target/riscv/cpu.h | 3 ++