Currently using 0x390 and 0x391 for x-epmp (experimental). This may change in
the future spec.
Signed-off-by: Hongzheng-Li <ethan.lee....@gmail.com>
Signed-off-by: Hou Weiying <weiying_...@outlook.com>
Signed-off-by: Myriad-Dreamin <camiy...@gmail.com>
---
target/riscv/cpu_bits.h | 3 +++
target/riscv/gdbstub.c | 2 ++
2 files changed, 5 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7f64ee1174..9a8a6be534 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -214,6 +214,9 @@
#define CSR_MTINST 0x34a
#define CSR_MTVAL2 0x34b
+/* Enhanced PMP */
+#define CSR_MSECCFG 0x390
+#define CSR_MSECCFGH 0x391
/* Physical Memory Protection */
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index eba12a86f2..de5551604a 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -132,6 +132,8 @@ static int csr_register_map[] = {
CSR_MIP,
CSR_MTINST,
CSR_MTVAL2,
+ CSR_MSECCFG,
+ CSR_MSECCFGH,
CSR_PMPCFG0,
CSR_PMPCFG1,
CSR_PMPCFG2,
--
2.20.1
