Signed-off-by: Hongzheng-Li <ethan.lee....@gmail.com>
Signed-off-by: Hou Weiying <weiying_...@outlook.com>
Signed-off-by: Myriad-Dreamin <camiy...@gmail.com>
---
target/riscv/csr.c | 18 ++++++++++++++++++
target/riscv/pmp.c | 40 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 11d184cd16..e2395e3a51 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -112,6 +112,11 @@ static int hmode(CPURISCVState *env, int csrno)
return -1;
}
+static int epmp(CPURISCVState *env, int csrno)
+{
+ return -!(env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP));
+}
+
static int pmp(CPURISCVState *env, int csrno)
{
return -!riscv_feature(env, RISCV_FEATURE_PMP);
@@ -1160,6 +1165,18 @@ static int write_pmpaddr(CPURISCVState *env, int csrno,
target_ulong val)
return 0;
}
+static int read_mseccfg(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = mseccfg_csr_read(env);
+ return 0;
+}
+
+static int write_mseccfg(CPURISCVState *env, int csrno, target_ulong val)
+{
+ mseccfg_csr_write(env, val);
+ return 0;
+}
+
#endif
/*
@@ -1368,6 +1385,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTINST] = { hmode, read_mtinst, write_mtinst
},
/* Physical Memory Protection */
+ [CSR_MSECCFG] = { epmp, read_mseccfg, write_mseccfg
},
[CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 8df389cecd..0eabaf690c 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -490,3 +490,43 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t
addr_index)
return val;
}
+
+
+/*
+ * Handle a write to a mseccfg CSR
+ */
+void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
+{
+ int i;
+
+ if (!MSECCFG_RLB_ISSET(env)) {
+ for (i = 0; i < MAX_RISCV_PMPS; i++) {
+ if (pmp_is_locked(env, i)) {
+ /*
+ * Now that mseccfg.rlb is zero
+ * the value of mseccfg.rlb should be locked.
+ */
+ val &= ~MSECCFG_RLB;
+ break;
+ }
+ }
+ }
+
+ /*
+ * sticky bit
+ */
+ val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
+
+ env->mseccfg = val;
+ trace_mseccfg_csr_write(env->mhartid, val);
+}
+
+
+/*
+ * Handle a read from a mseccfg CSR
+ */
+target_ulong mseccfg_csr_read(CPURISCVState *env)
+{
+ trace_mseccfg_csr_read(env->mhartid, env->mseccfg);
+ return env->mseccfg;
+}
--
2.20.1
