his way only implemented devices are exposed to the
> guest and the user does not need to provide a DTB.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> docs/system/arm/xlnx-versal-virt.rst | 49
> hw/arm/xlnx
On Wed, Jul 16, 2025 at 11:54:26AM +0200, Luc Michel wrote:
> Remove now unused clock nodes. They have been replaced by the ones
> created in the SoC. Remove the unused cfg.secure VersalVirt field.
> Remove unecessary include directives.
>
> Signed-off-by: Luc Michel
Reviewe
On Wed, Jul 16, 2025 at 11:54:30AM +0200, Luc Michel wrote:
> Add a test for the amd-versal2-virt machine using the same command line,
> kernel, initrd than the ones used for amd-versal-virt.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
>
On Wed, Jul 16, 2025 at 11:54:28AM +0200, Luc Michel wrote:
> Add a note in the DTB section explaining how to dump the generated DTB
> using the dumpdtb machine option.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> docs/system/arm/xlnx-v
viewed-by: Francisco Iglesias
>
> Signed-off-by: Luc Michel
> ---
> hw/arm/xlnx-versal-virt.c | 74 +++
> 1 file changed, 52 insertions(+), 22 deletions(-)
>
> diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
> inde
On Wed, Jul 16, 2025 at 11:54:27AM +0200, Luc Michel wrote:
> Update the list of supported devices in the Versal SoCs.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> docs/system/arm/xlnx-versal-virt.rst | 7 +--
> 1 file changed, 5 insertio
ompatibility.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> docs/system/arm/xlnx-versal-virt.rst | 26 +++---
> hw/arm/xlnx-versal-virt.c| 11 +++
> 2 files changed, 22 insertions(+), 15 deletions(-)
>
> diff
and versal2 in term of architecture allow to reuse the
> VersalMap structure to almost fully describe the implemented parts of
> versal2.
>
> The versal2 eFuse device differs quite a lot from the versal one and is
> left as future work.
>
> Signed-off-by: Luc Michel
/globally/
Otherwise:
Reviewed-by: Francisco Iglesias
> preparation for versal2.
>
> Signed-off-by: Luc Michel
> ---
> hw/arm/xlnx-versal.c | 15 +--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/hw/arm/xlnx-versal.c b/hw/arm/
e. Those two devices are currently not implemented so IRQs
> targeting those will be left unconnected. This is in preparation for
> versal2.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> hw/arm/xlnx-versal.c | 41 +
On Wed, Jul 16, 2025 at 11:54:19AM +0200, Luc Michel wrote:
> Add the versal2 version of the CRL device. For the implemented part, it
> is similar to the versal version but drives reset line of more devices.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
&g
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-versal.h | 204 ---
> hw/arm/xlnx-versal.c | 28 ++---
> 2 files changed, 7 insertions(+), 225 deletions(-)
>
> diff --git a/include/h
On Wed, Jul 16, 2025 at 11:54:17AM +0200, Luc Michel wrote:
> Use the bsa.h header for ARM timer and maintainance IRQ indices instead
> of redefining our owns.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-versal.h | 6 ---
to connect. The component
> parts of the device names are chosen to match the properties on the CRL.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> hw/arm/xlnx-versal.c | 31 ++-
> 1 file changed, 30 insertions(+), 1 deletion
;
> return 0;
> }
>
> -static void crl_reset_dev(XlnxVersalCRL *s, DeviceState *dev,
> - bool rst_old, bool rst_new)
> +static DeviceState **versal_decode_periph_rst(XlnxVersalCRLBase *s,
> + hwaddr addr,
On Wed, Jul 16, 2025 at 11:54:14AM +0200, Luc Michel wrote:
> Split the TYPE_XLNX_VERSAL_CRL type into base and concrete classes. This
> is in preparation for the versal2 version of the CRL.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> include/h
On Wed, Jul 16, 2025 at 11:54:12AM +0200, Luc Michel wrote:
> Add the versal_get_num_cpu accessor to the Versal SoC to retrieve the
> number of CPUs in the SoC. Use it in the xlnx-versal-virt machine.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> i
dtb callback.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-versal.h | 7 +---
> hw/arm/xlnx-versal-virt.c| 79 +---
> hw/arm/xlnx-versal.c | 73 ++---
> 3 fil
On Wed, Jul 16, 2025 at 11:54:10AM +0200, Luc Michel wrote:
> Refactor the OCM creation using the VersalMap structure.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-versal.h | 4
> hw/arm/xlnx-versal.c | 20 +++
On Wed, Jul 16, 2025 at 11:54:09AM +0200, Luc Michel wrote:
> Refactor the RPU cluster creation using the VersalMap structure. This
> effectively instantiate the RPU GICv2 which was not instantiated before.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
&g
On Wed, Jul 16, 2025 at 11:54:13AM +0200, Luc Michel wrote:
> Drop unused include directives from xlnx-versal-crl.c
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> hw/misc/xlnx-versal-crl.c | 5 +
> 1 file changed, 1 insertion(+), 4 deletions(-)
&g
On Wed, Jul 16, 2025 at 11:54:08AM +0200, Luc Michel wrote:
> Add support for GICv2 instantiation in the Versal SoC. This is in
> preparation for the RPU refactoring.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> hw/arm/
he
> IRQ to all the GICs.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-versal.h | 1 +
> hw/arm/xlnx-versal.c | 55 +---
> 2 files changed, 52 insertions(+), 4 deletions(-)
>
> diff --
On Wed, Jul 16, 2025 at 11:54:05AM +0200, Luc Michel wrote:
> Add the instance of the GIC ITS in the APU.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> hw/arm/xlnx-versal.c | 50
> 1 file changed, 50 inser
On Wed, Jul 16, 2025 at 11:54:04AM +0200, Luc Michel wrote:
> Add a way to configure the MP affinity value of the CPUs given their
> core and cluster IDs. For the Versal APU CPUs, the MP affinity value is
> directly given by the core ID.
>
> Signed-off-by: Luc Michel
Reviewe
aken care of by next commits.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-versal.h | 11 +-
> hw/arm/xlnx-versal-virt.c| 80 +---
> hw/arm/xlnx-versal.c | 346 ++-
> 3 file
On Wed, Jul 16, 2025 at 11:54:02AM +0200, Luc Michel wrote:
> Refactor the creation of virtio devices. Use the accessors provided by
> the Versal SoC to retrieve the reserved MMIO and IRQ space. Those are
> defined in the VersalMap structure.
>
> Signed-off-by: Luc Michel
Reviewe
On Wed, Jul 16, 2025 at 11:54:01AM +0200, Luc Michel wrote:
> Refactor the CRL device creation using the VersalMap structure. The
> connections to the RPU CPUs are temporarily removed and will be
> reintroduced with next refactoring commits.
>
> Signed-off-by: Luc Michel
Reviewe
On Wed, Jul 16, 2025 at 11:54:00AM +0200, Luc Michel wrote:
> Refactor the CFU device creation using the VersalMap structure. All
> users of the APB IRQ OR gate have now been converted. The OR gate device
> can be dropped.
>
> Signed-off-by: Luc Michel
Reviewed-by: Fra
model does not implement those IRQs anyway.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-versal.h | 2 --
> hw/arm/xlnx-versal-virt.c| 22
> hw/arm/xlnx-versal.c | 40 ++
On Wed, Jul 16, 2025 at 11:53:58AM +0200, Luc Michel wrote:
> Refactor the TRNG device creation using the VersalMap structure.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-versal.h | 2 --
> hw/arm/xlnx-ver
it.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-versal.h | 3 +--
> hw/arm/xlnx-versal-virt.c| 27 +++-
> hw/arm/xlnx-versal.c | 41 +---
> 3 files changed, 33 inse
l
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-versal.h | 5
> hw/arm/xlnx-versal.c | 48 +---
> 2 files changed, 28 insertions(+), 25 deletions(-)
>
> diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
to 22 indicate the index on the OR gate.
>
> This allows to share an IRQ among multiple devices. An OR gate is
> created to connect the devices to the actual IRQ pin.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
>
On Wed, Jul 16, 2025 at 11:53:54AM +0200, Luc Michel wrote:
> Refactor the OSPI controller creation using the VersalMap structure.
>
> Note that the connection to the PMC IOU SLCR is removed for now and will
> be re-added by next commits.
>
> Signed-off-by: Luc Michel
Revi
exist for them.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-versal.h | 5 +--
> hw/arm/xlnx-versal-virt.c| 43 ++--
> hw/arm/xlnx-versal.c | 78 +++-
> 3 files cha
On Wed, Jul 16, 2025 at 11:53:52AM +0200, Luc Michel wrote:
> Refactor the USB controller creation using the VersalMap structure.
>
> Note that the connection to the CRL is removed for now and will be
> re-added by next commits.
>
> Signed-off-by: Luc Michel
Reviewed-by:
On Wed, Jul 16, 2025 at 11:53:51AM +0200, Luc Michel wrote:
> Refactor the XRAM devices creation using the VersalMap structure.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-versal.h | 6
> hw/arm/xlnx-ver
On Wed, Jul 16, 2025 at 11:53:50AM +0200, Luc Michel wrote:
> Refactor the ADMA creation using the VersalMap structure.
>
> Note that the connection to the CRL is removed for now and will be
> re-added by next commits.
>
> Signed-off-by: Luc Michel
Reviewed-by:
On Wed, Jul 16, 2025 at 11:53:49AM +0200, Luc Michel wrote:
> Refactor the GEM ethernet controllers creation using the VersalMap
> structure.
>
> Note that the connection to the CRL is removed for now and will be
> re-added by next commits.
>
> Signed-off-by: Luc Michel
R
On Wed, Jul 16, 2025 at 11:53:48AM +0200, Luc Michel wrote:
> Refactor the SDHCI controllers creation using the VersalMap structure.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-versal.h | 5 +-
> hw/arm/xlnx-ver
ically creates the correct amount
> of CAN bus link properties based on the number of CAN controller
> advertised by the SoC.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-versal.h | 7 +--
> hw/arm/xlnx-versal-virt.c| 73 ++
t;
> Note that the connection to the CRL is removed for now and will be
> re-added by next commits.
>
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-versal.h | 2 -
> hw/arm/xlnx-versal-virt.c|
rt.c
> +++ b/hw/arm/xlnx-versal-virt.c
> @@ -1,9 +1,10 @@
> /*
> * Xilinx Versal Virtual board.
> *
> * Copyright (c) 2018 Xilinx Inc.
> + * Copyright (c) 2025, Advanced Micro Devices, Inc.
s/2025,/2025/
Otherwise:
Reviewed-by: Francisco Iglesias
> * Written by Edgar
65a2bd
> --- /dev/null
> +++ b/include/hw/arm/xlnx-versal-version.h
> @@ -0,0 +1,15 @@
> +/*
> + * AMD Versal versions
> + *
> + * Copyright (c) 2025, Advanced Micro Devices, Inc.
nitpick:
s/2025,/2025/
Otherwise:
Reviewed-by: Francisco Iglesias
> + * SPDX-License-Identifie
ission for interrupt
> registers")
> Signed-off-by: Luc Michel
Reviewed-by: Francisco Iglesias
> ---
> hw/net/cadence_gem.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index 50025d5a6f2..66
t are not
> supported by Emscripten. To avoid these issues, g_list_sort_with_data and
> g_slist_sort_with_data should be used instead, as they do not rely on
> function pointer casting.
>
> Signed-off-by: Kohei Tokunaga
Acked-by: Francisco Iglesias
> ---
> hw/net/can/xlnx-ver
On Wed, Dec 04, 2024 at 10:42:05AM -0800, Vikram Garhwal wrote:
> Previously, maintainer role was paused due to inactive email id. Commit id:
> c009d715721861984c4987bcc78b7ee183e86d75.
>
> Signed-off-by: Vikram Garhwal
Reviewed-by: Francisco Iglesias
> ---
> MAINTAINER
40c0)
> 8 - axi dma (0x41e0)
> 9 - axi dma
> 10 - gpio (0x4000)
> 11 - gpio2 (0x4001)
> 12 - gpio3 (0x4002)
>
> Signed-off-by: Sai Pavan Boddu
> Signed-off-by: Michal Simek
Reviewed-by: Francisco Iglesias
> ---
> Changes for V2:
> Make ch
t; 8 - axi dma (0x41e0)
> 9 - axi dma
> 10 - gpio (0x4000)
> 11 - gpio2 (0x4001)
> 12 - gpio3 (0x4002)
>
> Signed-off-by: Sai Pavan Boddu
> Signed-off-by: Michal Simek
Reviewed-by: Francisco Iglesias
> ---
> Changes for V2:
> Make changes to supp
native english speaking but I think "from the FIFO" sounds better to me!
> could cause an assertion failure:
> ../util/fifo8.c:67: fifo8_pop: Assertion `fifo->num > 0
>
> Signed-off-by: Shiva sagar Myana
With above changes:
Reviewed-by: Francisco Iglesias
On Thu, Aug 29, 2024 at 05:31:17PM +0530, Shiva sagar Myana wrote:
> Add the SFDP table for the Micron Xccela mt35xu01g flash.
>
> Signed-off-by: Shiva sagar Myana
Reviewed-by: Francisco Iglesias
> ---
> V1->V2: Change subject and commit message
>
> hw/block/m25p
Vikram's email is bouncing, pause his maintainership until a new email is
provided.
Signed-off-by: Francisco Iglesias
---
MAINTAINERS | 2 --
1 file changed, 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0c1bc69828..ad957ca5e8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1
amd.com one on the Xilinx Versal
OSPI maintaintership section. In the third I volunteer to replace Vikram as
maintainer for the CAN bus subsystem.
Best regards,
Francisco
Francisco Iglesias (3):
MAINTAINERS: Remove Vikram Garhwal as maintainer
MAINTAINERS: Update Xilinx Versal OSPI mai
Signed-off-by: Francisco Iglesias
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b03952f43e..a320ce759c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2701,6 +2701,7 @@ F: include/hw/rx/
CAN bus subsystem and hardware
M: Pavel Pisa
+M
Update my xilinx.com email address to my amd.com address.
Signed-off-by: Francisco Iglesias
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index ad957ca5e8..b03952f43e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1055,7 +1055,7
-off-by: Doug Brown
Reviewed-by: Francisco Iglesias
Thanks a lot for the fixes and sorry for the delayed review!
Best regards,
Francisco
> ---
> hw/net/can/xlnx-versal-canfd.c | 36 +++---
> 1 file changed, 3 insertions(+), 33 deletions(-)
>
> dif
Hi Peter,
On Fri, Sep 06, 2024 at 03:36:10PM +0100, Peter Maydell wrote:
> On Tue, 27 Aug 2024 at 04:51, Doug Brown wrote:
> >
> > This series fixes several problems I ran into while trying to simulate
> > the AMD/Xilinx Versal CANFD controller in the xlnx-versal-virt machine
> > using Xilinx's v
with a DLC of 0-8, which was broken previously.
>
> Signed-off-by: Doug Brown
Reviewed-by: Francisco Iglesias
> ---
> hw/net/can/xlnx-versal-canfd.c | 67 ++
> 1 file changed, 4 insertions(+), 63 deletions(-)
>
> diff --git a/hw/net/can/xlnx-v
On Fri, Aug 16, 2024 at 09:35:05AM -0700, Doug Brown wrote:
> There was no case for handling received CAN FD frames with a DLC of 0-8.
> This was already handled properly with TX. Add similar code for RX.
>
> Signed-off-by: Doug Brown
Reviewed-by: Francisco Iglesias
> ---
>
both the TX and RX code to put the data in the correct order.
>
> Signed-off-by: Doug Brown
Reviewed-by: Francisco Iglesias
> ---
> hw/net/can/xlnx-versal-canfd.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/hw/net/can/xlnx-vers
_frame for all of its ID registers. Correct this problem for
> both RX and TX, including RX filtering.
>
> Signed-off-by: Doug Brown
Reviewed-by: Francisco Iglesias
> ---
> hw/net/can/xlnx-versal-canfd.c | 53 --
> 1 file changed, 50 insertions
55f225b0bfe1 in object_new qom/object.c:797:12
> #9 0x55f226309e0d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11
>
> Signed-off-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
> include/hw/nvram/xlnx-versal-efuse.h | 1 +
> hw/nvram/xlnx-versal-efuse-ct
df1 in object_new qom/object.c:797:12
> #9 0x558432427c1d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11
>
> Signed-off-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
> include/hw/misc/xlnx-versal-trng.h | 1 +
> hw/misc/xlnx-versal-trng.c | 6 +++---
> 2 files c
87aa11 in object_new qom/object.c:797:12
> #9 0x56415507883d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11
>
> Signed-off-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
> include/hw/nvram/xlnx-bbram.h | 1 +
> hw/nvram/xlnx-bbram.c | 13 ++---
> 2 files cha
533c01 in object_new qom/object.c:797:12
> #9 0x55f402d31a2d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11
>
> Signed-off-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
> include/hw/nvram/xlnx-zynqmp-efuse.h | 1 +
> hw/nvram/xlnx-zynqmp-efuse.c |
55f225b0bfe1 in object_new qom/object.c:797:12
> #9 0x55f226309e0d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11
>
> Signed-off-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
> include/hw/nvram/xlnx-versal-efuse.h | 1 +
> hw/nvram/xlnx-versal-efuse-ct
gt; #9 0x55ec8d65c81d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11
>
> Signed-off-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
> hw/misc/xlnx-versal-cfu.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/hw/misc/xlnx-versal-cfu.c
; bit 0 when applying it, resulting in the IRQ never being delivered.
>
> Signed-off-by: Doug Brown
Reviewed-by: Francisco Iglesias
> ---
> hw/net/can/xlnx-versal-canfd.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/net/can/xlnx-versal-canfd.c
Brown
Reviewed-by: Francisco Iglesias
> ---
> hw/net/can/xlnx-versal-canfd.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/net/can/xlnx-versal-canfd.c b/hw/net/can/xlnx-versal-canfd.c
> index ad0c4da3c8..8968672b84 100644
> --- a/hw/net/can/xl
mc = MACHINE_CLASS(oc);
> +ObjectProperty *prop;
> mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
> mc->init = zynq_init;
> mc->max_cpus = ZYNQ_MAX_CPUS;
> @@ -379,6 +404,12 @@ static void zynq_machine_class_init(ObjectCla
On Thu, Jun 20, 2024 at 04:11:39PM +0530, Sai Pavan Boddu wrote:
> Added the supported device list and an example command.
>
> Signed-off-by: Sai Pavan Boddu
Reviewed-by: Francisco Iglesias
> Reviewed-by: Edgar E. Iglesias
> ---
> MAINTAINERS | 1 +
>
On Thu, Jun 20, 2024 at 04:11:37PM +0530, Sai Pavan Boddu wrote:
> boot-mode property sets user values into BOOT_MODE register, on hardware
> these are derived from board switches.
>
> Signed-off-by: Sai Pavan Boddu
Reviewed-by: Francisco Iglesias
> Reviewed-by: Edgar E. Iglesi
the tx queue"
Reviewed-by: Francisco Iglesias
BR,
F
> ---
> hw/net/can/xlnx-versal-canfd.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/hw/net/can/xlnx-versal-canfd.c b/hw/net/can/xlnx-versal-canfd.c
> index 47a14cfe63..5f083c21e9 100644
>
On 2024-02-16 12:03, Philippe Mathieu-Daudé wrote:
When the QOM parent is available, prefer object_initialize_child()
over object_initialize(), since it create the parent relationship.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
---
hw/net/can/xlnx-versal
On [2023 Dec 05] Tue 15:22:25, Sai Pavan Boddu wrote:
> Add Micro 2Gb OSPI flash part with sfdp data.
>
> Signed-off-by: Sai Pavan Boddu
Reviewed-by: Francisco Iglesias
> ---
> hw/block/m25p80_sfdp.h | 1 +
> hw/block/m25p80.c | 3 +++
> hw/blo
On [2023 Dec 05] Tue 15:22:26, Sai Pavan Boddu wrote:
> This property allows users to change flash model on command line as
> below.
>
>ex: "-M xlnx-versal-virt,ospi-flash=mt35xu02gbba"
>
> Signed-off-by: Sai Pavan Boddu
Reviewed-by: Francisco Iglesias
> -
> the memory region.
>
> Signed-off-by: Sai Pavan Boddu
Reviewed-by: Francisco Iglesias
Tested-by: Francisco Iglesias
> ---
> hw/ssi/xlnx-versal-ospi.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/ssi/xlnx-versal-ospi.c b/hw/ssi/xlnx-versal-ospi.c
>
SIZE register, so remove the LOG_GUEST_ERROR in that case.
While at it remove the comment marking the SIZE register as write-only.
See:
https://docs.xilinx.com/r/en-US/ug1087-zynq-ultrascale-registers/CSUDMA_SRC_SIZE-CSUDMA-Register
Signed-off-by: Frederic Konrad
Reviewed-by: Francisco Iglesias
On 2023-11-24 15:35, Frederic Konrad wrote:
It seems that the url changed a bit, and it triggers an error. Fix the URLs so
the documentation can be reached again.
Signed-off-by: Frederic Konrad
Reviewed-by: Francisco Iglesias
---
hw/dma/xlnx_csu_dma.c | 2
bytes for zynqmp-qspips) thus it is possible to write
out of s->regs[addr] in xilinx_spips_write for spips and qspips.
This fixes that wrong behavior.
Reviewed-by: Luc Michel
Signed-off-by: Frederic Konrad
Reviewed-by: Francisco Iglesias
---
hw/ssi/xilinx_spips.c
tps://gitlab.com/qemu-project/qemu/-/issues/1427
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
> ---
> hw/net/can/xlnx-zynqmp-can.c | 17 +
> 1 file changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/hw/net/can/xlnx-zynqmp-can.c b
g Liu
> Fixes: 98e5d7a2b7 ("hw/net/can: Introduce Xilinx ZynqMP CAN controller")
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1425
> Signed-off-by: Philippe Mathieu-Daudé
> Francisco Iglesias
-above line
+below line
Reviewed-by: Francisco Iglesias
> ---
&
Hi Philippe,
On 2023-11-16 16:44, Philippe Mathieu-Daudé wrote:
Hi Francisco,
On 16/11/23 15:17, Francisco Iglesias wrote:
Hi Philippe, good catch!
Well this was fuzzed by Qiang Liu.
On 2023-11-15 16:17, Philippe Mathieu-Daudé wrote:
Per
https://docs.xilinx.com/r/en-US/ug1085-zynq
bove minor modification:
Reviewed-by: Francisco Iglesias
Best regards,
Francisco
+bool is_txhpb = fifo == &s->txhpb_fifo;
+
+assert(used > 0);
+used %= CAN_FRAME_SIZE;
+
+/*
+ * Frame Message Format
+ *
+ * Each frame includes four words (16 bytes). Software mus
x-FOO", like commit e178113ff64 did.
Reported-by: Thomas Huth
Signed-off-by: Markus Armbruster
Reviewed-by: Francisco Iglesias
---
docs/system/arm/xlnx-versal-virt.rst | 2 +-
include/hw/misc/xlnx-versal-cframe-reg.h | 2 +-
include/hw/misc/xlnx-versal-cfu.h| 6 +++---
incl
On 2023-11-13 14:43, Markus Armbruster wrote:
Fixes: b65b4b7ae3c8 (xlnx-bbram: hw/nvram: Use dot in device type name)
Signed-off-by: Markus Armbruster
Reviewed-by: Francisco Iglesias
---
docs/system/arm/xlnx-versal-virt.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
On [2023 Oct 02] Mon 22:21:39, Tong Ho wrote:
> This replaces the comma (,) to dot (.) in the device type name
> so the name can be used with the 'driver=' command line option.
>
> Signed-off-by: Tong Ho
Reviewed-by: Francisco Iglesias
> ---
> include/hw/nvram/x
On [2023 Oct 03] Tue 22:57:13, Tong Ho wrote:
> This change implements the ResettableClass interface for the device.
>
> Signed-off-by: Tong Ho
Reviewed-by: Francisco Iglesias
> ---
> hw/nvram/xlnx-zynqmp-efuse.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(
On [2023 Oct 03] Tue 22:53:39, Tong Ho wrote:
> This change implements the ResettableClass interface for the device.
>
> Signed-off-by: Tong Ho
Reviewed-by: Francisco Iglesias
> ---
> hw/nvram/xlnx-versal-efuse-ctrl.c | 8 +---
> 1 file changed, 5 insertions(+), 3 dele
s not intended for use cases when
> cryptograpically strong TRNG is needed.
>
> Signed-off-by: Tong Ho
Reviewed-by: Francisco Iglesias
> ---
> hw/arm/Kconfig | 1 +
> hw/arm/xlnx-versal.c | 16
> include/hw/arm/xlnx-versal.h | 5
On [2023 Oct 04] Wed 07:27:46, Tong Ho wrote:
> Signed-off-by: Tong Ho
Reviewed-by: Francisco Iglesias
> ---
> tests/qtest/meson.build | 2 +-
> tests/qtest/xlnx-versal-trng-test.c | 490
> 2 files changed, 491 insertions(+), 1 deleti
trng_generate(true);
> +n = trng_collect(prng, cnt);
> +g_assert_cmpuint(n, ==, cnt);
> +
> +/* #2: zero string should match personalization disabled */
> +trng_load(R_TRNG_PER_STRNG_0, NULL);
> +trng_reseed(prng_seed);
> +
> +trng_generate(tr
On [2023 Sep 05] Tue 16:56:51, Philippe Mathieu-Daudé wrote:
> Simplify gicv3_class_name() logic. No functional change intended.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
> ---
> hw/intc/arm_gicv3_common.c | 9 -
> 1 file changed,
Connect the Configuration Frame Unit (CFU_APB, CFU_FDRO and CFU_SFR) to
the Versal machine.
Signed-off-by: Francisco Iglesias
Acked-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal.c | 42
include/hw/arm/xlnx-versal.h | 16
Introduce a model of Xilinx Versal's Configuration Frame Unit's Single
Frame Read port (CFU_SFR).
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/misc/xlnx-versal-cfu.c | 87 +++
include/hw/misc/xlnx-versal-cfu.h | 15 +
Introduce a model of the software programming interface (CFU_APB) of
Xilinx Versal's Configuration Frame Unit.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
MAINTAINERS | 2 +
hw/misc/meson.build | 1 +
hw/misc/xlnx-versal-
Introduce a model of Xilinx Versal's Configuration Frame broadcast
controller (CFRAME_BCAST_REG).
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/misc/xlnx-versal-cframe-reg.c | 161 +++
include/hw/misc/xlnx-versal-cframe-reg.h | 17 +++
2
Introduce a model of Xilinx Versal's Configuration Frame controller
(CFRAME_REG).
Signed-off-by: Francisco Iglesias
---
MAINTAINERS | 2 +
hw/misc/meson.build | 1 +
hw/misc/xlnx-versal-cframe-reg.c
Connect the Configuration Frame controller (CFRAME_REG) and the
Configuration Frame broadcast controller (CFRAME_BCAST_REG) to the
Versal machine.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal.c | 113 ++-
include/hw
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