On Wed, Jul 16, 2025 at 11:53:51AM +0200, Luc Michel wrote:
> Refactor the XRAM devices creation using the VersalMap structure.
>
> Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
> ---
> include/hw/arm/xlnx-versal.h | 6 ----
> hw/arm/xlnx-versal.c | 59 +++++++++++++++++++++---------------
> 2 files changed, 35 insertions(+), 30 deletions(-)
>
> diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
> index 4eeea98ff34..71c3314b8b4 100644
> --- a/include/hw/arm/xlnx-versal.h
> +++ b/include/hw/arm/xlnx-versal.h
> @@ -18,11 +18,10 @@
> #include "hw/or-irq.h"
> #include "hw/intc/arm_gicv3.h"
> #include "hw/rtc/xlnx-zynqmp-rtc.h"
> #include "qom/object.h"
> #include "hw/usb/xlnx-usb-subsystem.h"
> -#include "hw/misc/xlnx-versal-xramc.h"
> #include "hw/nvram/xlnx-bbram.h"
> #include "hw/nvram/xlnx-versal-efuse.h"
> #include "hw/ssi/xlnx-versal-ospi.h"
> #include "hw/dma/xlnx_csu_dma.h"
> #include "hw/misc/xlnx-versal-crl.h"
> @@ -86,15 +85,10 @@ struct Versal {
>
> CPUClusterState cluster;
> ARMCPU cpu[XLNX_VERSAL_NR_RCPUS];
> } rpu;
>
> - struct {
> - OrIRQState irq_orgate;
> - XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
> - } xram;
> -
> XlnxVersalCRL crl;
> } lpd;
>
> /* The Platform Management Controller subsystem. */
> struct {
> diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
> index 97cd991be10..6c5eb6d3fd5 100644
> --- a/hw/arm/xlnx-versal.c
> +++ b/hw/arm/xlnx-versal.c
> @@ -29,10 +29,11 @@
> #include "hw/char/pl011.h"
> #include "hw/net/xlnx-versal-canfd.h"
> #include "hw/sd/sdhci.h"
> #include "hw/net/cadence_gem.h"
> #include "hw/dma/xlnx-zdma.h"
> +#include "hw/misc/xlnx-versal-xramc.h"
>
> #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
> #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
> #define GEM_REVISION 0x40070106
>
> @@ -69,10 +70,18 @@ typedef struct VersalMap {
> uint64_t chan_stride;
> int irq_stride;
> } zdma[2];
> size_t num_zdma;
>
> + struct VersalXramMap {
> + uint64_t mem;
> + uint64_t mem_stride;
> + uint64_t ctrl;
> + uint64_t ctrl_stride;
> + int irq;
> + size_t num;
> + } xram;
> } VersalMap;
>
> static const VersalMap VERSAL_MAP = {
> .uart[0] = { 0xff000000, 18 },
> .uart[1] = { 0xff010000, 19 },
> @@ -90,10 +99,17 @@ static const VersalMap VERSAL_MAP = {
> .gem[1] = { { 0xff0d0000, 58 }, 2, "rgmii-id", 1000 },
> .num_gem = 2,
>
> .zdma[0] = { "adma", { 0xffa80000, 60 }, 8, 0x10000, 1 },
> .num_zdma = 1,
> +
> + .xram = {
> + .num = 4,
> + .mem = 0xfe800000, .mem_stride = 1 * MiB,
> + .ctrl = 0xff8e0000, .ctrl_stride = 0x10000,
> + .irq = 79,
> + },
> };
>
> static const VersalMap *VERSION_TO_MAP[] = {
> [VERSAL_VER_VERSAL] = &VERSAL_MAP,
> };
> @@ -633,41 +649,35 @@ static void versal_create_trng(Versal *s, qemu_irq *pic)
> mr = sysbus_mmio_get_region(sbd, 0);
> memory_region_add_subregion(&s->mr_ps, MM_PMC_TRNG, mr);
> sysbus_connect_irq(sbd, 0, pic[VERSAL_TRNG_IRQ]);
> }
>
> -static void versal_create_xrams(Versal *s, qemu_irq *pic)
> +static void versal_create_xrams(Versal *s, const struct VersalXramMap *map)
> {
> - int nr_xrams = ARRAY_SIZE(s->lpd.xram.ctrl);
> - DeviceState *orgate;
> - int i;
> + SysBusDevice *sbd;
> + MemoryRegion *mr;
> + DeviceState *or;
> + size_t i;
>
> - /* XRAM IRQs get ORed into a single line. */
> - object_initialize_child(OBJECT(s), "xram-irq-orgate",
> - &s->lpd.xram.irq_orgate, TYPE_OR_IRQ);
> - orgate = DEVICE(&s->lpd.xram.irq_orgate);
> - object_property_set_int(OBJECT(orgate),
> - "num-lines", nr_xrams, &error_fatal);
> - qdev_realize(orgate, NULL, &error_fatal);
> - qdev_connect_gpio_out(orgate, 0, pic[VERSAL_XRAM_IRQ_0]);
> + or = create_or_gate(s, OBJECT(s), "xram-orgate", map->num, map->irq);
>
> - for (i = 0; i < ARRAY_SIZE(s->lpd.xram.ctrl); i++) {
> - SysBusDevice *sbd;
> - MemoryRegion *mr;
> + for (i = 0; i < map->num; i++) {
> + hwaddr ctrl, mem;
>
> - object_initialize_child(OBJECT(s), "xram[*]", &s->lpd.xram.ctrl[i],
> - TYPE_XLNX_XRAM_CTRL);
> - sbd = SYS_BUS_DEVICE(&s->lpd.xram.ctrl[i]);
> - sysbus_realize(sbd, &error_fatal);
> + sbd = SYS_BUS_DEVICE(qdev_new(TYPE_XLNX_XRAM_CTRL));
> + object_property_add_child(OBJECT(s), "xram[*]", OBJECT(sbd));
> + sysbus_realize_and_unref(sbd, &error_fatal);
> +
> + ctrl = map->ctrl + map->ctrl_stride * i;
> + mem = map->mem + map->mem_stride * i;
>
> mr = sysbus_mmio_get_region(sbd, 0);
> - memory_region_add_subregion(&s->mr_ps,
> - MM_XRAMC + i * MM_XRAMC_SIZE, mr);
> + memory_region_add_subregion(&s->mr_ps, ctrl, mr);
> mr = sysbus_mmio_get_region(sbd, 1);
> - memory_region_add_subregion(&s->mr_ps, MM_XRAM + i * MiB, mr);
> + memory_region_add_subregion(&s->mr_ps, mem, mr);
>
> - sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(orgate, i));
> + sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(or, i));
> }
> }
>
> static void versal_create_bbram(Versal *s, qemu_irq *pic)
> {
> @@ -1186,15 +1196,16 @@ static void versal_realize(DeviceState *dev, Error
> **errp)
>
> for (i = 0; i < map->num_zdma; i++) {
> versal_create_zdma(s, &map->zdma[i]);
> }
>
> + versal_create_xrams(s, &map->xram);
> +
> versal_create_usbs(s, pic);
> versal_create_pmc_apb_irq_orgate(s, pic);
> versal_create_rtc(s, pic);
> versal_create_trng(s, pic);
> - versal_create_xrams(s, pic);
> versal_create_bbram(s, pic);
> versal_create_efuse(s, pic);
> versal_create_pmc_iou_slcr(s, pic);
> versal_create_ospi(s, pic);
> versal_create_crl(s, pic);
> --
> 2.50.0
>
