On Wed, Jul 16, 2025 at 11:54:14AM +0200, Luc Michel wrote:
> Split the TYPE_XLNX_VERSAL_CRL type into base and concrete classes. This
> is in preparation for the versal2 version of the CRL.
>
> Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
> ---
> include/hw/misc/xlnx-versal-crl.h | 31 ++++++++++++++++++--
> hw/misc/xlnx-versal-crl.c | 48 +++++++++++++++++++------------
> 2 files changed, 58 insertions(+), 21 deletions(-)
>
> diff --git a/include/hw/misc/xlnx-versal-crl.h
> b/include/hw/misc/xlnx-versal-crl.h
> index dba6d3585d1..2b39d203a67 100644
> --- a/include/hw/misc/xlnx-versal-crl.h
> +++ b/include/hw/misc/xlnx-versal-crl.h
> @@ -1,21 +1,27 @@
> /*
> * QEMU model of the Clock-Reset-LPD (CRL).
> *
> * Copyright (c) 2022 Xilinx Inc.
> + * Copyright (c) 2025 Advanced Micro Devices, Inc.
> * SPDX-License-Identifier: GPL-2.0-or-later
> *
> * Written by Edgar E. Iglesias <edgar.igles...@xilinx.com>
> */
> #ifndef HW_MISC_XLNX_VERSAL_CRL_H
> #define HW_MISC_XLNX_VERSAL_CRL_H
>
> #include "hw/sysbus.h"
> #include "hw/register.h"
> #include "target/arm/cpu-qom.h"
> +#include "hw/arm/xlnx-versal-version.h"
>
> +#define TYPE_XLNX_VERSAL_CRL_BASE "xlnx-versal-crl-base"
> #define TYPE_XLNX_VERSAL_CRL "xlnx-versal-crl"
> +
> +OBJECT_DECLARE_TYPE(XlnxVersalCRLBase, XlnxVersalCRLBaseClass,
> + XLNX_VERSAL_CRL_BASE)
> OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL)
>
> REG32(ERR_CTRL, 0x0)
> FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
> REG32(IR_STATUS, 0x4)
> @@ -214,22 +220,43 @@ REG32(PSM_RST_MODE, 0x370)
>
> #define CRL_R_MAX (R_PSM_RST_MODE + 1)
>
> #define RPU_MAX_CPU 2
>
> -struct XlnxVersalCRL {
> +struct XlnxVersalCRLBase {
> SysBusDevice parent_obj;
> +
> + RegisterInfoArray *reg_array;
> + uint32_t *regs;
> +};
> +
> +struct XlnxVersalCRLBaseClass {
> + SysBusDeviceClass parent_class;
> +};
> +
> +struct XlnxVersalCRL {
> + XlnxVersalCRLBase parent_obj;
> qemu_irq irq;
>
> struct {
> ARMCPU *cpu_r5[RPU_MAX_CPU];
> DeviceState *adma[8];
> DeviceState *uart[2];
> DeviceState *gem[2];
> DeviceState *usb;
> } cfg;
>
> - RegisterInfoArray *reg_array;
> uint32_t regs[CRL_R_MAX];
> RegisterInfo regs_info[CRL_R_MAX];
> };
> +
> +static inline const char *xlnx_versal_crl_class_name(VersalVersion ver)
> +{
> + switch (ver) {
> + case VERSAL_VER_VERSAL:
> + return TYPE_XLNX_VERSAL_CRL;
> + default:
> + g_assert_not_reached();
> + }
> +}
> +
> #endif
> diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c
> index f288545967a..be89e0da40d 100644
> --- a/hw/misc/xlnx-versal-crl.c
> +++ b/hw/misc/xlnx-versal-crl.c
> @@ -296,21 +296,21 @@ static const RegisterAccessInfo crl_regs_info[] = {
> .reset = 0x1,
> .rsvd = 0xf8,
> }
> };
>
> -static void crl_reset_enter(Object *obj, ResetType type)
> +static void versal_crl_reset_enter(Object *obj, ResetType type)
> {
> XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
> unsigned int i;
>
> for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
> register_reset(&s->regs_info[i]);
> }
> }
>
> -static void crl_reset_hold(Object *obj, ResetType type)
> +static void versal_crl_reset_hold(Object *obj, ResetType type)
> {
> XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
>
> crl_update_irq(s);
> }
> @@ -323,24 +323,26 @@ static const MemoryRegionOps crl_ops = {
> .min_access_size = 4,
> .max_access_size = 4,
> },
> };
>
> -static void crl_init(Object *obj)
> +static void versal_crl_init(Object *obj)
> {
> XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
> + XlnxVersalCRLBase *xvcb = XLNX_VERSAL_CRL_BASE(obj);
> SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> int i;
>
> - s->reg_array =
> + xvcb->reg_array =
> register_init_block32(DEVICE(obj), crl_regs_info,
> ARRAY_SIZE(crl_regs_info),
> s->regs_info, s->regs,
> &crl_ops,
> XLNX_VERSAL_CRL_ERR_DEBUG,
> CRL_R_MAX * 4);
> - sysbus_init_mmio(sbd, &s->reg_array->mem);
> + xvcb->regs = s->regs;
> + sysbus_init_mmio(sbd, &xvcb->reg_array->mem);
> sysbus_init_irq(sbd, &s->irq);
>
> for (i = 0; i < ARRAY_SIZE(s->cfg.cpu_r5); ++i) {
> object_property_add_link(obj, "cpu_r5[*]", TYPE_ARM_CPU,
> (Object **)&s->cfg.cpu_r5[i],
> @@ -375,45 +377,53 @@ static void crl_init(Object *obj)
> OBJ_PROP_LINK_STRONG);
> }
>
> static void crl_finalize(Object *obj)
> {
> - XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
> + XlnxVersalCRLBase *s = XLNX_VERSAL_CRL_BASE(obj);
> register_finalize_block(s->reg_array);
> }
>
> -static const VMStateDescription vmstate_crl = {
> +static const VMStateDescription vmstate_versal_crl = {
> .name = TYPE_XLNX_VERSAL_CRL,
> .version_id = 1,
> .minimum_version_id = 1,
> .fields = (const VMStateField[]) {
> VMSTATE_UINT32_ARRAY(regs, XlnxVersalCRL, CRL_R_MAX),
> VMSTATE_END_OF_LIST(),
> }
> };
>
> -static void crl_class_init(ObjectClass *klass, const void *data)
> +static void versal_crl_class_init(ObjectClass *klass, const void *data)
> {
> - ResettableClass *rc = RESETTABLE_CLASS(klass);
> DeviceClass *dc = DEVICE_CLASS(klass);
> + ResettableClass *rc = RESETTABLE_CLASS(klass);
>
> - dc->vmsd = &vmstate_crl;
> -
> - rc->phases.enter = crl_reset_enter;
> - rc->phases.hold = crl_reset_hold;
> + dc->vmsd = &vmstate_versal_crl;
> + rc->phases.enter = versal_crl_reset_enter;
> + rc->phases.hold = versal_crl_reset_hold;
> }
>
> -static const TypeInfo crl_info = {
> - .name = TYPE_XLNX_VERSAL_CRL,
> +static const TypeInfo crl_base_info = {
> + .name = TYPE_XLNX_VERSAL_CRL_BASE,
> .parent = TYPE_SYS_BUS_DEVICE,
> - .instance_size = sizeof(XlnxVersalCRL),
> - .class_init = crl_class_init,
> - .instance_init = crl_init,
> + .instance_size = sizeof(XlnxVersalCRLBase),
> + .class_size = sizeof(XlnxVersalCRLBaseClass),
> .instance_finalize = crl_finalize,
> + .abstract = true,
> +};
> +
> +static const TypeInfo versal_crl_info = {
> + .name = TYPE_XLNX_VERSAL_CRL,
> + .parent = TYPE_XLNX_VERSAL_CRL_BASE,
> + .instance_size = sizeof(XlnxVersalCRL),
> + .instance_init = versal_crl_init,
> + .class_init = versal_crl_class_init,
> };
>
> static void crl_register_types(void)
> {
> - type_register_static(&crl_info);
> + type_register_static(&crl_base_info);
> + type_register_static(&versal_crl_info);
> }
>
> type_init(crl_register_types)
> --
> 2.50.0
>
