From: "Chao Liu"
Hi, all:
Thanks to Alistair for the review~
PATCH v4:
Rebasing this on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next
PATCH v3:
Use cpu_by_arch_id() instead of qemu_get_cpu(), when registering gpio in
sifive_plic_create().
PATCH v2:
During plic init
-cluster machines, hartid_base should be 0.
Signed-off-by: Chao Liu
Reviewed-by: Tingjian Zhang
Reviewed-by: Alistair Francis
---
hw/intc/sifive_plic.c | 4 ++--
hw/riscv/boot.c| 4 ++--
hw/riscv/microchip_pfsoc.c | 2 +-
hw/riscv/sifive_u.c| 5 +++--
hw/riscv/virt.c
11758...@linaro.org/
https://lore.kernel.org/qemu-devel/7ec1e581-3919-fdf5-499a-279cba99d...@eik.bme.hu/
https://lore.kernel.org/qemu-devel/874iy5d9v7@pond.sub.org/
PATCH v1:
https://lore.kernel.org/qemu-devel/210c69d9-803e-41a5-b40c-bc8372e58...@redhat.com/
--
Regards,
Chao
Chao Liu (1):
sys
, ram): riscv_virt_board.ram
`- 0004-0007 (prio 0, i/o): alias pcie-mmio-high
@gpex_mmio_window
```
Signed-off-by: Chao Liu
Reviewed-by: Qingze Zhao
Reviewed-by: Tingjian Zhang
---
system/memory.c | 132
1 file changed
9d9-803e-41a5-b40c-bc8372e58...@redhat.com/
--
Regards,
Chao
Chao Liu (1):
system: improve visual representation of node hierarchy in 'info
mtree' output for qemu monitor
system/memory.c | 122 +++-
1 file changed, 111 insertions(+), 11 deletions(-)
--
2.48.1
-87ff (prio 0, ram): riscv_virt_board.ram
`-- 0004-0007 (prio 0, i/o): alias pcie-mmio-high
@gpex_mmio_window
```
Signed-off-by: Chao Liu
Reviewed-by: Qingze Zhao
Reviewed-by: Tingjian Zhang
---
system/memory.c | 122
@pond.sub.org/
PATCH v1:
https://lore.kernel.org/qemu-devel/210c69d9-803e-41a5-b40c-bc8372e58...@redhat.com/
--
Regards,
Chao
Chao Liu (1):
system: improve visual representation of node hierarchy in 'info
mtree' output for qemu monitor
system/memory.c | 122 +++
(prio 0, ram): riscv_virt_board.ram
`-- 0004-0007 (prio 0, i/o): alias pcie-mmio-high
```
Signed-off-by: Chao Liu
Reviewed-by: Qingze Zhao
Reviewed-by: Tingjian Zhang
---
system/memory.c | 122 +++-
1 file changed, 111
ntation according to the review comments.
PATCH v2 (reviewed):
https://lore.kernel.org/qemu-devel/72b2d911-112e-48e3-9ba4-017a11758...@linaro.org/T/#u
PATCH v1 (reviewed):
https://lore.kernel.org/qemu-devel/210c69d9-803e-41a5-b40c-bc8372e58...@redhat.com/T/#u
--
Regards,
Chao
Chao Liu (1):
sys
(prio 0, i/o): gpex_ioport_window
│ │ │ └── 0300-0300 (prio 0, i/o): gpex_ioport
...
│ │ └── 0004-0007 (prio 0, i/o): alias ...
```
Signed-off-by: Chao Liu
Reviewed-by: Qingze Zhao
Reviewed-by: Tingjian Zhang
---
system/memory.c | 36
l/210c69d9-803e-41a5-b40c-bc8372e58...@redhat.com/T/#u
--
Regards,
Chao
Chao Liu (1):
system: optimizing info mtree printing for monitors
system/memory.c | 42 --
1 file changed, 36 insertions(+), 6 deletions(-)
--
2.48.1
(prio 0, i/o): gpex_ioport_window
│ │ │ └── 0300-0300 (prio 0, i/o): gpex_ioport
...
│ │ └── 0004-0007 (prio 0, i/o): alias ...
```
Signed-off-by: Chao Liu
Reviewed-by: Qingze Zhao
Reviewed-by: Tingjian Zhang
---
system/memory.c | 42
...
│ │ ├── 4000-7fff (prio 0, i/o): alias ...
│ │ ├── 8000-87ff (prio 0, ram): riscv_virt_board.ram
│ │ └── 0004-0007 (prio 0, i/o): alias ...
```
--
Regards,
Chao
Chao Liu (1):
system: optimizing info mtree printing for
Make the hierarchical relationship between nodes clearer by adding characters
Signed-off-by: Chao Liu
---
system/memory.c | 34 +++---
1 file changed, 27 insertions(+), 7 deletions(-)
diff --git a/system/memory.c b/system/memory.c
index 71434e7ad0..e723928068 100644
x27;s hartid for indexing via the cpu_by_arch_id()
interface.
PATCH v1 (Reviewed):
https://lore.kernel.org/qemu-riscv/416e68f4-bf12-4218-ae2d-0246cc8ea...@linaro.org/T/#u
--
Regards,
Chao
Chao Liu (1):
hw/riscv: fix PLIC hart topology configuration string when not getting
CPUState corr
-cluster machines, hartid_base should be 0.
Signed-off-by: Chao Liu
Reviewed-by: Qingze Zhao
Reviewed-by: Tingjian Zhang
---
hw/intc/sifive_plic.c | 4 ++--
hw/riscv/boot.c| 4 ++--
hw/riscv/microchip_pfsoc.c | 2 +-
hw/riscv/sifive_u.c| 5 +++--
hw/riscv/virt.c
https://lore.kernel.org/qemu-riscv/416e68f4-bf12-4218-ae2d-0246cc8ea...@linaro.org/T/#u
--
Regards,
Chao
Chao Liu (1):
hw/riscv: fix PLIC hart topology configuration string when not getting
CPUState correctly
hw/intc/sifive_plic.c | 2 +-
hw/riscv/boot.c| 4 ++--
hw/
-cluster machines, hartid_base should be 0.
Signed-off-by: Chao Liu
Reviewed-by: Qingze Zhao
Reviewed-by: Tingjian Zhang
---
hw/intc/sifive_plic.c | 2 +-
hw/riscv/boot.c| 4 ++--
hw/riscv/microchip_pfsoc.c | 2 +-
hw/riscv/sifive_u.c| 5 +++--
hw/riscv/virt.c
From: Philippe Mathieu-Daudé
Hi,
On 15/4/25 12:05, Chao Liu wrote:
> riscv_plic_hart_config_string() when getting CPUState via qemu_get_cpu()
> should be consistent with keeping sifive_plic_realize() by
> hartid_base + cpu_index.
>
> For non-numa or single-cluster machin
to
update it with the value of mhartid during riscv_hart_realize().
Signed-off-by: Chao Liu
Reviewed-by: zhaoqingze
---
hw/riscv/boot.c| 4 ++--
hw/riscv/microchip_pfsoc.c | 2 +-
hw/riscv/riscv_hart.c | 1 +
hw/riscv/sifive_u.c| 5 +++--
hw/riscv/virt.c
,
Chao
Chao Liu (1):
hw/riscv: fix PLIC hart topology configuration string when not getting
CPUState correctly
hw/riscv/boot.c| 4 ++--
hw/riscv/microchip_pfsoc.c | 2 +-
hw/riscv/riscv_hart.c | 1 +
hw/riscv/sifive_u.c| 5 +++--
hw/riscv/virt.c| 2
/cakmqykpfyxhk8panovzv3fmwxd79wzsjylwkkoagemt_b2k...@mail.gmail.com/
--
Regards,
Chao
Chao Liu (2):
target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a
parameter
target/riscv: fix handling of nop for vstart >= vl in some vector
instruction
target/riscv/vcrypto_helper.c |
made the following change:
Put VSTART_CHECK_EARLY_EXIT(env) at the beginning of the vext_vx_rm_2 function,
so that the VSTART register is checked correctly.
Fixes: df4252b2ec ("target/riscv/vector_helpers: do early exit when
vstart >= vl")
Signed-off-by: Chao Liu
Reviewed-by: Daniel Henrique
lving evl.
Fixes: df4252b2ec ("target/riscv/vector_helpers: do early exit when
vstart >= vl")
Signed-off-by: Chao Liu
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/vcrypto_helper.c | 32 +++
target/riscv/vector_helper.c| 69 -
t_b2k...@mail.gmail.com/
>
> --
> Regards,
> Chao
>
> Chao Liu (2):
> target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a
> parameter
> target/riscv: fix handling of nop for vstart >= vl in some vector
> instruction
>
> target/ri
made the following change:
Put VSTART_CHECK_EARLY_EXIT(env) at the beginning of the vext_vx_rm_2 function,
so that the VSTART register is checked correctly.
Fixes: df4252b2ec ("target/riscv/vector_helpers: do early exit when
vstart >= vl")
Signed-off-by: Chao Liu
---
target/riscv
lving evl.
Fixes: df4252b2ec ("target/riscv/vector_helpers: do early exit when
vstart >= vl")
Signed-off-by: Chao Liu
---
target/riscv/vcrypto_helper.c | 32 +++
target/riscv/vector_helper.c| 69 -
target/riscv/vector_internals.c
://lore.kernel.org/qemu-devel/cakmqykpfyxhk8panovzv3fmwxd79wzsjylwkkoagemt_b2k...@mail.gmail.com/
--
Regards,
Chao
Chao Liu (2):
target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a
parameter
target/riscv: fix handling of nop for vstart >= vl in some vector
instruct
lving evl.
Signed-off-by: Chao Liu
---
target/riscv/vcrypto_helper.c | 32 +++
target/riscv/vector_helper.c| 69 -
target/riscv/vector_internals.c | 4 +-
target/riscv/vector_internals.h | 12 +++---
4 files changed, 57 insertions(+), 60 deletions
fix:
https://lore.kernel.org/all/20240322085319.1758843-8-alistair.fran...@wdc.com/
Signed-off-by: Chao Liu
---
target/riscv/vector_helper.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index
is macro,
such as vlm.v instruction (real vl = ceil(vl / 8)).
PATCH v1:
https://lore.kernel.org/qemu-riscv/cover.1734423785.git.lc00...@tecorigin.com/
Chao Liu (2):
target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a
parameter
target/riscv: fix handling of nop for vstart
;ve made the following change:
put VSTART_CHECK_EARLY_EXIT(env) at the beginning of the vext_vx_rm_2 function,
so that the VSTART register is checked correctly.
Regards,
Chao
Chao Liu (1):
target/riscv: Fix handling of NOP for vstart >= vl in vext_vx_rm_2()
target/riscv/vector_helper.c | 4 +
fix:
https://lore.kernel.org/all/20240322085319.1758843-8-alistair.fran...@wdc.com/
Signed-off-by: Chao Liu
---
target/riscv/vector_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a85dd1d200
On 2024/12/11 23:55, Richard Henderson wrote:
On 12/11/24 09:48, Chao Liu wrote:
Signed-off-by: Chao Liu
---
target/riscv/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 284b112821..0d74ee4581 100644
--- a/target
Signed-off-by: Chao Liu
---
target/riscv/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 284b112821..0d74ee4581 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -170,7 +170,8 @@ FIELD(VTYPE, VSEW, 3, 3)
FIELD
Hi, all:
I improve compatibility with RV32 and RV64 by adjusting the FIELD definition
of vtype.vill.
PATCH v1:
https://lore.kernel.org/qemu-devel/cover.1733922709.git.lc00...@tecorigin.com/T
Chao Liu (1):
target/riscv: add VILL field for vtype register macro definition
target/riscv/cpu.h
Signed-off-by: Chao Liu
---
target/riscv/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 284b112821..fc286484b8 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -170,7 +170,8 @@ FIELD(VTYPE, VSEW, 3, 3)
FIELD
register. The bit position for vill is [63].
This change ensures that our implementation remains in line with the latest
RISC-V specifications, thereby maintaining compatibility and correctness.
Chao Liu (1):
target/riscv: add VILL field for vtype register macro definition
target/riscv/cp
Currently, the v1-patch is not yet capable of achieving the desired effect.
It still requires passing the number of variable arguments to the helper_print()
function:
static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
{
TCGv src1;
decode_save_opc(ctx, 0);
For example:
static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
{
TCGv src1;
decode_save_opc(ctx, 0);
src1 = get_address(ctx, a->rs1, 0);
gen_helper_print("src1 %x\n", src1);
...
return true;
}
When the TCG executes instruc
discuss
and come up with a friendlier and more universal solution. :)
Regards,
Chao
Chao Liu (1):
riscv: Add gen_helper_print() to debug IR
target/riscv/helper.h| 13
target/riscv/op_helper.c | 46
2 files changed, 59 insertions(+)
--
2.40.1
Signed-off-by: Chao Liu
---
target/riscv/helper.h| 13
target/riscv/op_helper.c | 46
2 files changed, 59 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 451261ce5a..667da16988 100644
--- a/target/riscv
space of the
zynq board with the following qemu command:
${QEMU_PATH}/qemu-system-aarch64 \
-M xilinx-zynq-a9 \
-display none \
-monitor stdio -s
(qemu) info mtree -f
The testing methodology previously discussed in earlier email exchanges
will not be repeated here.
Chao Liu (3
s not
consistent with the hardware specifications.
This bug was not found earlier because the ignore_memory_transaction_failures
flag was enabled, which ignored exceptions from devcfg devices
when access was disabled.
Signed-off-by: Chao Liu
---
hw/dma/xlnx-zynq-devcfg.c | 7 ++-
1 file chang
Add xilinx zynq board memory mapping is implemented in the device.
Remove a ignore_memory_transaction_failures concurrently.
See: ug585-Zynq-7000-TRM manual B.3 (Module Summary)
Signed-off-by: Chao Liu
---
hw/arm/xilinx_zynq.c | 71 +++-
1 file changed
Signed-off-by: Chao Liu
---
hw/dma/xlnx-zynq-devcfg.c | 2 +-
include/hw/dma/xlnx-zynq-devcfg.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c
index b8544d0731..e5eff9abc0 100644
--- a/hw/dma/xlnx-zynq-devcfg.c
/xilinx/support/documents/data_sheets/ds190-Zynq-7000-Overview.pdf
[2]: http://www.wiki.xilinx.com/Zynq+2016.2+Release
Chao Liu (2):
xilink_zynq: Add various missing unimplemented devices
xilink-zynq-devcfg: Fix up for memory address range size not set
correctly
hw/arm/xilinx_zynq.c | 12 +
diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c
index b8544d0731..7170353a62 100644
--- a/hw/dma/xlnx-zynq-devcfg.c
+++ b/hw/dma/xlnx-zynq-devcfg.c
@@ -372,7 +372,7 @@ static void xlnx_zynq_devcfg_init(Object *obj)
s->regs_info, s->regs,
Add xilinx zynq board memory mapping is implemented in the device.
Remove a ignore_memory_transaction_failures concurrently.
Source: Zynq-7000 SoC Data Sheet: Overview, Chapter: Memory Map
See: https://www.mouser.com/datasheet/2/903/ds190_Zynq_7000_Overview-1595492.pdf
Signed-off-by: Chao Liu
On 2024/9/27 22:20, Peter Maydell wrote:
On Fri, 27 Sept 2024 at 15:03, Chao Liu wrote:
On 2024/9/27 20:18, Peter Maydell wrote:
On Fri, 27 Sept 2024 at 09:52, Chao Liu wrote:
Even if our test set is not sufficiently comprehensive, we can create an
unimp_device for the maximum address space
On 2024/9/27 20:18, Peter Maydell wrote:
On Fri, 27 Sept 2024 at 09:52, Chao Liu wrote:
Hi, thank you for your prompt reply, it's a great encouragement to me!
Based on your review suggestions, I have improved the v1 patch.
By using create_unimplemented_device() during the initializ
Signed-off-by: Chao Liu
---
hw/dma/xlnx-zynq-devcfg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c
index b8544d0731..7170353a62 100644
--- a/hw/dma/xlnx-zynq-devcfg.c
+++ b/hw/dma/xlnx-zynq-devcfg.c
@@ -372,7 +372,7
Add PMU, CAN, GPIO, I2C, and other as unimplemented devices.
Remove a ignore_memory_transaction_failures concurrently.
This allows operating systems such as Linux to run emulations such as
xilinx_zynq-7000
Signed-off-by: Chao Liu
---
hw/arm/xilinx_zynq.c | 46
t
root@zedboard-zynq7:~#
Chao Liu (2):
xilink_zynq: Add various missing unimplemented devices
xilink-zynq-devcfg: Fix up for memory address range size not set
correctly
hw/arm/xilinx_zynq.c | 46 ++-
hw/dma/xlnx-zynq-devcfg.c | 2 +-
2 files changed
> The ignore_memory_transaction_failures is used for compatibility
> with legacy board models.
>
> I attempted to remove this property from the
> xilink_zynq board and replace it with unimplemented devices to
> handle devices that are not implemented on the board
> The ignore_memory_transaction_failures is used for compatibility
> with legacy board models.
>
> I attempted to remove this property from the
> xilink_zynq board and replace it with unimplemented devices to
> handle devices that are not implemented on the board
The ignore_memory_transaction_failures is used for compatibility
with legacy board models.
I attempted to remove this property from the
xilink_zynq board and replace it with unimplemented devices to
handle devices that are not implemented on the board.
Chao Liu (2):
xilink_zynq: Add various
Add PMU, CAN, GPIO, I2C, and other as unimplemented devices.
Remove a ignore_memory_transaction_failures concurrently.
This allows operating systems such as Linux to run emulations such as
xilinx_zynq-7000
Signed-off-by: Chao Liu
---
hw/arm/xilinx_zynq.c | 44
Signed-off-by: Chao Liu
---
hw/dma/xlnx-zynq-devcfg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c
index b8544d0731..7170353a62 100644
--- a/hw/dma/xlnx-zynq-devcfg.c
+++ b/hw/dma/xlnx-zynq-devcfg.c
@@ -372,7 +372,7
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