Hi, all: I made the following changes in version 2 of the patch:
Regarding the plic initialization phase to get CPUState by traversing qemu_get_cpu(), this is an early design flaw, a better approach would be to use riscv's hartid for indexing via the interface cpu_by_arch_id(). PATCH v1: https://lore.kernel.org/qemu-riscv/416e68f4-bf12-4218-ae2d-0246cc8ea...@linaro.org/T/#u -- Regards, Chao Chao Liu (1): hw/riscv: fix PLIC hart topology configuration string when not getting CPUState correctly hw/intc/sifive_plic.c | 2 +- hw/riscv/boot.c | 4 ++-- hw/riscv/microchip_pfsoc.c | 2 +- hw/riscv/sifive_u.c | 5 +++-- hw/riscv/virt.c | 2 +- include/hw/riscv/boot.h | 2 +- 6 files changed, 9 insertions(+), 8 deletions(-) -- 2.48.1
