Reviewed-by: Clement Mathieu--Drif
On 09/04/2025 4:36 am, Bibo Mao wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> Macro PCH_PIC_HTMSI_VEC_OFFSET and PCH_PIC_ROUTE_ENTRY_OFFSET is re
Reviewed-by: Clement Mathieu--Drif
On 09/04/2025 4:36 am, Bibo Mao wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> For some registers with width 8 bytes, its name is something like
>
On 10/04/2025 22.31, Rorie Reyes wrote:
On 3/17/25 9:41 AM, Thomas Huth wrote:
On 11/03/2025 16.16, Rorie Reyes wrote:
Handle interception of the CHSC SEI instruction for requests
indicating the guest's AP configuration has changed.
Signed-off-by: Rorie Reyes
Reviewed-by: Anthony Krowiak
Te
On Wed Apr 2, 2025 at 5:17 AM AEST, Corey Minyard wrote:
> On Wed, Apr 02, 2025 at 12:01:47AM +1000, Nicholas Piggin wrote:
>> These little things came up when looking at behaviour of IPMI with
>> the bmc-sim implementation running the ppc powernv machine, and
>> trying to clean up error messages a
On Fri, Apr 11, 2025 at 06:38:35AM +0200, Markus Armbruster wrote:
> Date: Fri, 11 Apr 2025 06:38:35 +0200
> From: Markus Armbruster
> Subject: Re: [PATCH 1/5] qapi/qom: Introduce kvm-pmu-filter object
>
> Zhao Liu writes:
>
> > Hi Markus
> >
> > On Thu, Apr 10, 2025 at 04:21:01PM +0200, Markus
On 2025/04/10 22:45, Michael S. Tsirkin wrote:
On Thu, Apr 10, 2025 at 05:26:47PM +0900, Akihiko Odaki wrote:
On 2025/04/10 17:02, Michael S. Tsirkin wrote:
On Thu, Apr 10, 2025 at 04:54:41PM +0900, Akihiko Odaki wrote:
On 2025/04/10 16:48, 'Michael S. Tsirkin' via devel wrote:
On Thu, Apr 10
Am 5. April 2025 14:00:00 UTC schrieb Guenter Roeck :
>This series is needed to support the USB interface on imx8mp-evk when
>booting the Linux kernel.
>
>According to the XHCI specification, ERSTBA should be written in Low-High
>order. The Linux kernel writes the high word first. This results i
Am 11. April 2025 03:53:27 UTC schrieb Guenter Roeck :
>On 4/8/25 14:56, Bernhard Beschow wrote:
>
> Tt turns out that sabrelite has the same problem.
Did it work with QEMU 9.2?
>>>
>>> No, the pcie interfaces on sabrelite don't instantiate for me with qemu 9.2
>>> (9.2.3,
Since v3:
https://lore.kernel.org/qemu-devel/20250117172244.406206-1-npig...@gmail.com/
- Split out the preparation patches for the ahci and virtio tests
into their own patches as suggested by Phil.
- Added an extra assertion that qpci_iounmap() must only be called
for a bar that was previousl
Assert there is no existing irq raised that would lead to a false
positive interrupt test.
e1000e has to disable interrupt throttling for this test, because
it can cause delayed superfluous interrupts which trip the assertions.
Cc: Michael S. Tsirkin
Cc: Marcel Apfelbaum
Cc: Dmitry Fleytman
Cc
The spec explicitly permits xITR register interval field to have a value
of zero to disable throttling. The e1000e model already allows for this
in the throttling logic, so remove the minimum value for the register.
The spec appears to say there is a maximum observable interrupt rate
when throttli
Add assertions to ensure a BAR is not mapped twice, and that only
previously mapped BARs are unmapped. This can help catch bugs and
fragile coding.
Cc: Michael S. Tsirkin
Cc: Marcel Apfelbaum
Reviewed-by: Akihiko Odaki
Reviewed-by: Fabiano Rosas
Signed-off-by: Nicholas Piggin
---
tests/qtest
Migration tests can create new QPCI devices for the destination
machine which may need to take on some state of the source machine
after destination is complete.
Add a migration fixup helper and call it from ahci migration tests.
This is currently a noop and will be used subsequently.
Signed-off-
ahci-test double-maps the hba bar in the pending_callback test.
Unmap it first, to keep iomaps balanced.
Cc: Michael S. Tsirkin
Cc: Marcel Apfelbaum
Cc: Akihiko Odaki
Reviewed-by: Akihiko Odaki
Reviewed-by: Fabiano Rosas
Signed-off-by: Nicholas Piggin
---
tests/qtest/libqos/ahci.h | 2 ++
Setting msix entry address and data and masking is moved into
common code helpers from virtio tests.
For now that remains the only user, but there are changes under
development to enable msix vectors for msix, e1000e, and xhci
tests, which can make use of them.
Reviewed-by: Akihiko Odaki
Signed-
Devices where the MSI-X addresses are shared with other MMIO on BAR0
can not use msi_enable because it unmaps and remaps BAR0, which
interferes with device MMIO mappings. xhci-nec is one such device we
would like to test with msix.
Use the BAR iomap tracking structure introduced in the previous ch
Unmap the virtio-pci bar in qvirtio_pci_disable_device() to keep
iomap/iounmap balanced.
Cc: Michael S. Tsirkin
Cc: Marcel Apfelbaum
Reviewed-by: Akihiko Odaki
Reviewed-by: Fabiano Rosas
Signed-off-by: Nicholas Piggin
---
tests/qtest/libqos/virtio-pci.h | 1 +
tests/qtest/libqos/virtio-pci.
ahci-test has a bunch of tests where the pci bar was not mapped. Avoid
unmapping it in these cases, to keep iomaps balanced.
Cc: Michael S. Tsirkin
Cc: Marcel Apfelbaum
Cc: Akihiko Odaki
Cc: Akihiko Odaki
Cc: Fabiano Rosas
Signed-off-by: Nicholas Piggin
---
tests/qtest/ahci-test.c | 35
Zhao Liu writes:
> Hi Markus
>
> On Thu, Apr 10, 2025 at 04:21:01PM +0200, Markus Armbruster wrote:
>> Date: Thu, 10 Apr 2025 16:21:01 +0200
>> From: Markus Armbruster
>> Subject: Re: [PATCH 1/5] qapi/qom: Introduce kvm-pmu-filter object
>>
>> Zhao Liu writes:
>>
>> > Introduce the kvm-pmu-fi
Changes since v1:
https://lore.kernel.org/qemu-devel/20250115150112.346497-1-npig...@gmail.com/
- Made changes as suggested by Odaki san in v1. Renamed some
functions and changed some comments, added a Fixes: tag.
- Bug fix in "net/e1000e|igb: Fix interrupt throttling logic"
patch to notify o
The guest value xITR logic is not required now that the write functions
store necessary data to be read back, and internal users mask and shift
fields they need as they go.
Signed-off-by: Nicholas Piggin
---
hw/net/e1000e_core.c | 31 +++
hw/net/igb_core.c| 14 +++
Interrupt throttling is broken in several ways:
- Timer expiry sends an interrupt even if there is no cause.
- (e1000e) Mitigated interrupts still auto-clear cause bits.
- Timer expiry that results in an interrupt does not re-arm the timer so
an interrupt can appear immediately after the timer ex
IGB EITR registers have counter fields which reflect the current ITR
and LLI counter values, as well as a bit to enable LLI moderation,
and a bit to write the register without modifying the counter fields.
Implement the EITR Moderation Counter (aka EITR counter), and counter
ignore bit. The EITR c
Enable interrupt throtling on one of the two queue interrupts used
in the multiple_transfers test, to improve coverage. The number of
interrupts for the e1000e test is reduced because it has a long minimum
throttling delay so without reducing iterations throttling adds about
40s to the test runtime
IGB throttling granularity is 1us, and interval field is in bits 2..14
of the EITRx registers.
Fixes: 3a977deebe6b ("Intrdocue igb device emulation")
Signed-off-by: Nicholas Piggin
---
hw/net/igb_regs.h | 3 +++
hw/net/igb_core.c | 7 ---
2 files changed, 7 insertions(+), 3 deletions(-)
dif
The e1000e and igb tests do not clear the ICR/EICR cause bits (or
set auto-clear) on seeing queue interrupts, which inhibits the
triggering of a new interrupt. The msix pending bit which is used
to test for the interrupt is also not cleared (the vector is masked).
Fix this by clearing the ICR/EICR
On 4/8/25 14:56, Bernhard Beschow wrote:
Tt turns out that sabrelite has the same problem.
Did it work with QEMU 9.2?
No, the pcie interfaces on sabrelite don't instantiate for me with qemu 9.2
(9.2.3,
more specifically). I see the pcie root port, but nothing behind it.
You need to add `
Hi Markus
On Thu, Apr 10, 2025 at 04:21:01PM +0200, Markus Armbruster wrote:
> Date: Thu, 10 Apr 2025 16:21:01 +0200
> From: Markus Armbruster
> Subject: Re: [PATCH 1/5] qapi/qom: Introduce kvm-pmu-filter object
>
> Zhao Liu writes:
>
> > Introduce the kvm-pmu-filter object and support the PMU
On Thu, Apr 10, 2025 at 10:07:15PM +0800, Ewan Hai wrote:
> Date: Thu, 10 Apr 2025 22:07:15 +0800
> From: Ewan Hai
> Subject: Re: [PATCH v2] target/i386: Fix model number of Zhaoxin YongFeng
> vCPU template
>
> On 4/10/25 8:22 PM, Paolo Bonzini wrote:
> >
> > On 4/7/25 04:07, Ewan Hai wrote:
>
> -Original Messages-
> From: "Dmitry Osipenko"
> Send time:Friday, 04/11/2025 05:59:11
> To: "Cong Liu"
> Cc: jiqian.c...@amd.com, akihiko.od...@daynix.com, alex.ben...@linaro.org,
> alexander.deuc...@amd.com, christian.koe...@amd.com,
> gert.wol...@collabora.com, gurchetansi...@chr
On Fri, Apr 11, 2025 at 2:19 AM Paolo Bonzini wrote:
>
> qtest_set_command_cb passed to g_once should match GThreadFunc,
> which it does not. But using g_once is actually unnecessary,
> because the function is called by riscv_harts_realize() under
> the Big QEMU Lock.
>
> Reported-by: Kohei Tokun
The 'want_zero' parameter to raw_co_block_status() was added so that
we can avoid potentially time-consuming lseek(SEEK_DATA) calls
throughout the file (working around poor filesystems that have O(n)
rather than O(1) extent probing). But when it comes to learning if a
file is completely sparse (fo
Prove that blockdev-mirror can now result in sparse destination files.
By making this a separate test, it was possible to test effects of
individual patches for the various pieces that all have to work
together for a sparse mirror to be successful.
Signed-off-by: Eric Blake
---
tests/qemu-iotest
There are enough optimizations possible when a file is known to read
as all zero that it is worth taking the extra time during
raw_open_common() to catch more than just 100% sparse files. In
particular, since our implementation of blockdev-create intentionally
allocates a small all-zero block at t
When mirroring, the goal is to ensure that the destination reads the
same as the source; this goal is met whether the destination is sparse
or fully-allocated. However, if the destination cannot efficiently
write zeroes, then any time the mirror operation wants to copy zeroes
from the source to th
This patch is purely mechanical, changing bool want_zero into the new
enum BlockStatusMode. As of this patch, all implementations are
unchanged (the old want_zero==true is now mode==BDRV_BSTAT_PRECISE),
but the callers in io.c are set up so that future patches will be able
to differente between al
When doing a sync=full mirroring, QMP drive-mirror requests full
zeroing if it did not just create the destination, and blockdev-mirror
requests full zeroing unconditionally. This is because during a full
sync, we must ensure that the portions of the disk that are not
otherwise touched by the sour
When mirroring images, it makes sense for the destination to be sparse
even if it was not connected with "discard":"unmap"; the only time the
destination should be fully allocated is if the user pre-allocated it,
or if the source was not sparse.
Eric Blake (6):
mirror: Skip pre-zeroing destinati
On 4/10/25 2:44 AM, Sairaj Kodilkar wrote:
From: Vasant Hegde
If vCPUs > 255 then x86 common code (x86_cpus_init()) call kvm_enable_x2apic().
But if vCPUs <= 255 then it won't call kvm_enable_x2apic().
Booting guest in x2apic mode, amd-iommu,xtsup=on and <= 255 vCPUs is
broken as it fails t
On 4/10/25 8:22 PM, Paolo Bonzini wrote:
On 4/7/25 04:07, Ewan Hai wrote:
The model number was mistakenly set to 0x0b (11) in commit ff04bc1ac4.
The correct value is 0x5b. This mistake occurred because the extended
model bits in cpuid[eax=0x1].eax were overlooked, and only the base
model was us
The H264 implementation only sends frames when it detects changes in
the server's framebuffer. This leads to artifacts when there are no
further changes, as the internal H264 encoder may still contain data.
This patch modifies the code to send a few additional frames in such
situations to flush th
On 4/2/25 15:10, Avihai Horon wrote:
On 26/03/2025 9:51, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
Also rename vfio_devices_all_device_dirty_tracking_started() while at
it and use the prefix 'vfio_container_devices_' for routines simply
looping over the
On 4/2/2025 7:56 PM, Daniel P. Berrangé wrote:
On Tue, Apr 01, 2025 at 09:01:24AM -0400, Xiaoyao Li wrote:
TDX advertises core crystal clock with cpuid[0x15] as 25MHz for TD
guests and it's unchangeable from VMM. As a result, TDX guest reads
the APIC timer as the same frequency, 25MHz.
Did you
The following changes since commit dfaecc04c46d298e9ee81bd0ca96d8754f1c27ed:
Merge tag 'pull-riscv-to-apply-20250407-1' of
https://github.com/alistair23/qemu into staging (2025-04-07 09:18:33 -0400)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/hw-misc-2025
From: Denis Rastyogin
This error was discovered by fuzzing qemu-img.
This commit fixes a division by zero error in the bench_cb() function
that occurs when using the bench command with a zero-sized image.
The issue arises because b->image_size can be zero, leading to a
division by zero in the m
On Friday, April 4, 2025 1:34:27 PM CEST BALATON Zoltan wrote:
> On Fri, 4 Apr 2025, Christian Schoenebeck wrote:
> > On Monday, March 31, 2025 3:05:24 PM CEST BALATON Zoltan wrote:
> >> On Sun, 23 Mar 2025, Christian Schoenebeck wrote:
> >>> On Sunday, March 16, 2025 1:20:46 AM CET BALATON Zoltan
On 4/7/2025 3:49 PM, Chenyi Qiang wrote:
Modify memory_region_set_ram_discard_manager() to return false if a
RamDiscardManager is already set in the MemoryRegion.
It doesn't return false, but -EBUSY.
The caller must
handle this failure, such as having virtio-mem undo its actions and fail
the
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 44 +++
target/arm/cpu.c | 12 ---
target/arm/cpu.h | 2 --
target/
An L2 KVM guest fails to boot inside a pSeries LPAR when booted with a
memory more than 128 GB and PCI device passthrough. The L2 guest also
crashes when it is booted with a memory greater than 128 GB and a PCI
device is hotplugged later.
The issue arises from a conditional check for `levels > 1`
The search list is currently hardcoded to: ["x264enc", "openh264enc"]
x264enc: is probably the best available software encoder
openh264enc: lower quality, but available on more systems.
We restrict encoders to a known list because each encoder requires
fine tuning to get reasonable/usable results
+x86 maintainers (you forgot to CC them)
On 10/04/2025 07:44, Sairaj Kodilkar wrote:
> From: Vasant Hegde
>
> If vCPUs > 255 then x86 common code (x86_cpus_init()) call
> kvm_enable_x2apic().
> But if vCPUs <= 255 then it won't call kvm_enable_x2apic().
>
> Booting guest in x2apic mode, amd-io
Commit 60d30cff847 ("target/ppc: Move SPR indirect registers into
PnvCore") was mismerged and moved the SPRs to power8-only, instead
of power9/10-only.
Fixes: 60d30cff847 ("target/ppc: Move SPR indirect registers into PnvCore")
Reviewed-by: Philippe Mathieu-Daudé
Cc: qemu-sta...@nongnu.org
Signed
Hi Philippe, thank you for the comments.
> > +static gpointer g_qtest_set_command_cb(
> > +bool (*pc_cb)(CharBackend *chr, gchar **words))
> > +{
>
> Why not use a GThreadFunc prototype, casting the argument?
Sure, I'll fix this.
> OK for the rest, but it might help to merge by corresponding
The secure-IPL-code-loading-attributes facility (SCLAF)
provides additional security during IPL.
Availability of SCLAF is determined by byte 136 bit 3 of the
SCLP Read Info block.
Signed-off-by: Zhuoying Cai
---
target/s390x/cpu_features.c | 1 +
target/s390x/cpu_features_def.h.inc | 1
On MacOS, UI event loop has to be ran in the main thread of a process.
Because of that restriction, on this platform, qemu main event loop is
ran on another thread [1].
This breaks record/replay feature, which expects thread running qemu_init
to initialize hold this lock, breaking associated funct
Signed-off-by: Pierrick Bouvier
---
tests/functional/test_aarch64_replay.py | 2 --
1 file changed, 2 deletions(-)
diff --git a/tests/functional/test_aarch64_replay.py
b/tests/functional/test_aarch64_replay.py
index 029fef3cbf8..bd6609d9149 100755
--- a/tests/functional/test_aarch64_replay.py
+
Recently, it was found that rr tests fail on MacOS, with a replay_mutex_unlock()
assertion. This is a recent regression, related to running qemu main event loop
in a separate thread, like first commit explain.
We first fix the regression, by handling the qemu replay mutex in the same way
we deal w
Mario Fleischmann writes:
> On 08.04.2025 16:37, Markus Armbruster wrote:
>
>> Alex Bennée writes:
>>
>>> Markus Armbruster writes:
>>>
Alex Bennée writes:
> Markus Armbruster writes:
>
>> Mario Fleischmann writes:
>>
>>> Apologies for the line wrapping in yest
On Thu, Apr 10, 2025 at 2:24 PM Kohei Tokunaga wrote:
> > >> has_int128_type is set to false on emscripten as of now to avoid errors
> > >> by
> > >> libffi.
> >
> > What is the error here? How hard would it be to test for it?
>
> When has_int128_type=true, I encountered a runtime error from lib
On 8/4/25 12:20, Klaus Jensen wrote:
From: Klaus Jensen
Fix regression when attaching private namespaces that gets attached to
the wrong controller.
Keep track of the original controller "owner" of private namespaces, and
only attach if this matches on controller enablement.
Fixes: 6ccca4b6bb
On 5/4/25 23:48, Bernhard Beschow wrote:
Guenter Roeck (2):
hw/arm/imx8mp-evk: Remove unimplemented cpu-idle-states properties
from devicetree
hw/arm/imx8mp-evk: Remove unimplemented nxp,imx8mp-fspi node from
devicetree
Patches 2 & 3 queued, thanks!
On 2025/04/10 16:48, 'Michael S. Tsirkin' via devel wrote:
On Thu, Apr 10, 2025 at 04:42:06PM +0900, Akihiko Odaki wrote:
virtio-net expects set_features() will be called when the feature set
used by the guest changes to update the number of virtqueues. Call it
during reset as reset clears all f
On 4/9/2025 3:39 AM, Markus Armbruster wrote:
Hi Steve, I apologize for the slow response.
Steve Sistare writes:
Using qom-list and qom-get to get all the nodes and property values in a
QOM tree can take multiple seconds because it requires 1000's of individual
QOM requests. Some managers fe
Hi Zhao,
On 4/10/25 2:45 AM, Zhao Liu wrote:
> On Sun, Mar 30, 2025 at 06:32:29PM -0700, Dongli Zhang wrote:
>> Date: Sun, 30 Mar 2025 18:32:29 -0700
>> From: Dongli Zhang
>> Subject: [PATCH v3 10/10] target/i386/kvm: don't stop Intel PMU counters
>> X-Mailer: git-send-email 2.43.5
>>
>> The kvm_
10.04.2025 12:54, Cong Liu пишет:
> I discovered that on an ARM64 environment, the 'virtio-gpu: Support
> asynchronous fencing' patch causes the virtual machine GUI to fail to
> display. Rolling back this patch and using virgl allows the virtual machine
> to start normally. When the VM screen is
v2: - Change the parameter name from "cmic" to "cmic-mctrs".
- If there is more than 1 controller in a subsystem, set CMIC.MCTRS
for each controller whether or not the cmic-mctrs parameter is set.
While testing Linux atomic writes with qemu-nvme v10.0.0-rc1, Linux was
incorrectly displa
If there are multiple controllers in a subsystem, CMIC.MCTRS should be set to on
for all controllers. For single controller subsystems, CMIC.MCTRS will be off by
default. A new subsystem specific parameter will allow setting CMIC.MCTRS for
single controller subsystems.
New NVMe Subsystem QEMU Para
Hi,
On 3/10/25 5:23 PM, Alireza Sanaee via wrote:
> Test new PPTT topolopy with cache representation.
>
> Signed-off-by: Alireza Sanaee
> Reviewed-by: Jonathan Cameron
> ---
> tests/qtest/bios-tables-test.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/tests/qtest/bios-tables-tes
From: Juraj Marcin
Commit aec21d3175 (qapi: Add InetSocketAddress member keep-alive)
introduces the keep-alive flag, but this flag is not copied together
with other options in qio_dns_resolver_lookup_sync_inet().
This patch fixes this issue and also prevents future ones by copying the
entire str
So that encoder can improve the picture quality.
Signed-off-by: Dietmar Maurer
---
ui/vnc.c | 25 -
ui/vnc.h | 3 +++
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/ui/vnc.c b/ui/vnc.c
index 2e60b55e47..4ba0b715fd 100644
--- a/ui/vnc.c
+++ b/ui/vnc.c
@@ -
The per-core SCRATCH0-7 registers are shared between big cores, which
was missed in the big-core implementation. It is difficult to model
well with the big-core == 2xPnvCore scheme we moved to, this fix
uses the even PnvCore to store the scrach data.
Also remove a stray log message that came in wi
The select&umask is the common way for x86 to identify the PMU event,
so support this way as the "x86-default" format in kvm-pmu-filter
object.
Signed-off-by: Zhao Liu
Tested-by: Yi Lai
---
Changes since RFC v2:
* Drop hexadecimal variants and support numeric version in QAPI
directly. (Danie
On 4/9/2025 1:35 PM, Alexey Kardashevskiy wrote:
>
>
> On 7/4/25 17:49, Chenyi Qiang wrote:
>> Modify memory_region_set_ram_discard_manager() to return false if a
>> RamDiscardManager is already set in the MemoryRegion. The caller must
>> handle this failure, such as having virtio-mem undo its
Currently, on a P10 KVM guest, the mitigations seen in the output of
"lscpu" command are different from the host. The reason for this
behaviour is that when the KVM guest makes the "h_get_cpu_characteristics"
hcall, QEMU does not consider the data it received from the host via the
KVM_PPC_GET_CPU_C
I discovered that on an ARM64 environment, the 'virtio-gpu: Support
asynchronous fencing' patch causes the virtual machine GUI to fail to display.
Rolling back this patch and using virgl allows the virtual machine to start
normally. When the VM screen is black, I can see some errors in QEMU. I u
Hi Ali,
On 3/10/25 5:23 PM, Alireza Sanaee via wrote:
> Specifying the cache layout in virtual machines is useful for
> applications and operating systems to fetch accurate information about
> the cache structure and make appropriate adjustments. Enforcing correct
> sharing information can lead to
GStreamer is required to implement H264 encoding for VNC. Please note
that QEMU already depends on this library when you enable Spice.
Signed-off-by: Dietmar Maurer
---
meson.build | 10 ++
meson_options.txt | 2 ++
scripts/meson-buildoptions.sh | 5 -
On 07.04.25 18:28, Eric Blake wrote:
On Fri, Apr 04, 2025 at 10:31:53PM +0300, Vladimir Sementsov-Ogievskiy wrote:
Actualize documentation and synchronize it for commands which actually
call the same functions internally.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
qapi/block-core.json |
Mario Fleischmann writes:
> Thanks a lot for the response, I really appreciate your time.
>
> On 07.04.2025 14:33, Markus Armbruster wrote:
>
>> Mario Fleischmann writes:
>>
>>> This patch series introduces support for the Multi-Core Debug (MCD) API, a
>>> commonly used debug interface by emula
- Split `write()` DR case into `write_data_register()`
Signed-off-by: Rakesh Jeyasingh
---
rust/hw/char/pl011/src/device.rs | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs
index 87153cdae1..bb2
Hi Zhao,
On 4/10/25 12:43 AM, Zhao Liu wrote:
> ...
>
>> TODO:
>> - This patch adds is_host_compat_vendor(), while there are something
>> like is_host_cpu_intel() from target/i386/kvm/vmsr_energy.c. A rework
>> may help move those helpers to target/i386/cpu*.
>
> vmsr_energy emulates R
Hi Zhao,
On 4/10/25 1:21 AM, Zhao Liu wrote:
> On Sun, Mar 30, 2025 at 06:32:28PM -0700, Dongli Zhang wrote:
>> Date: Sun, 30 Mar 2025 18:32:28 -0700
>> From: Dongli Zhang
>> Subject: [PATCH v3 09/10] target/i386/kvm: support perfmon-v2 for reset
>> X-Mailer: git-send-email 2.43.5
>>
>> Since per
On 2025/04/08 11:46 AM, Cédric Le Goater wrote:
> On 4/8/25 11:14, Amit Machhiwal wrote:
> > Hi Cédric,
> >
> > Thanks for taking a look at this patch. Please find my responses below:
> >
> > On 2025/04/08 08:29 AM, Cédric Le Goater wrote:
> > > Hello Amit,
> > >
> > > Please use --cover-letter
On Wed, 9 Apr 2025 12:49:36 -0300
Gustavo Romero wrote:
> Hi Igor,
>
> On 4/9/25 11:05, Igor Mammedov wrote:
> > On Fri, 4 Apr 2025 00:01:22 -0300
> > Gustavo Romero wrote:
> >
> >> Hi Phil,
> >>
> >> On 4/3/25 17:40, Philippe Mathieu-Daudé wrote:
> >>> We are going to fix the test_acpi_aa
On Sat, 5 Apr 2025, at 11:09, BALATON Zoltan wrote:
> On Fri, 4 Apr 2025, Alexey Kardashevskiy wrote:
> > On Tue, 1 Apr 2025, at 01:26, BALATON Zoltan wrote:
> >> The FDT does not normally store name properties but reconstructs it
> >> from path but each node in Open Firmware should at least hav
Hi Kohei,
first, congrats for this work!
It would be really nice to have this available upstream, starting with a
modest TCI port, before having the tcg backend also.
On 4/10/25 06:13, Kohei Tokunaga wrote:
Hi Philippe,
>
> The biggest problem I'm seeing is we no longer support 64-bit gues
Allow to call that function easily several times in next commit.
Signed-off-by: Pierrick Bouvier
---
target/arm/ptw.c | 24 ++--
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 754ef0d3a25..6ea39ee5755 100644
--- a/tar
It was reported that QEMU monitor command gva2gpa was reporting unmapped
memory for a valid access (qemu-system-aarch64), during a copy from
kernel to user space (__arch_copy_to_user symbol in Linux) [1].
This was affecting cpu_memory_rw_debug also, which
is used in numerous places in our codebase.
It was reported that QEMU monitor command gva2gpa was reporting unmapped
memory for a valid access (qemu-system-aarch64), during a copy from
kernel to user space (__arch_copy_to_user symbol in Linux) [1].
This was affecting cpu_memory_rw_debug also, which
is used in numerous places in our codebase.
It should be equivalent to previous code.
Allow to call common function to get a page address later.
Signed-off-by: Pierrick Bouvier
---
target/arm/ptw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 5e196cfa955..754ef0d3a25 100644
We'll reuse this function later.
Signed-off-by: Pierrick Bouvier
---
target/arm/ptw.c | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 8d4e9e07a94..5e196cfa955 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
Hi Zhao,
On 4/9/25 10:05 PM, Zhao Liu wrote:
> Hi Dongli,
>
> The logic is fine for me :-) And thank you to take my previous
> suggestion. When I revisit here after these few weeks, I have some
> thoughts:
>
>> +if (pmu_cap) {
>> +if ((pmu_cap & KVM_PMU_CAP_DISABLE) &&
>> +
On 3/17/25 9:41 AM, Thomas Huth wrote:
On 11/03/2025 16.16, Rorie Reyes wrote:
Handle interception of the CHSC SEI instruction for requests
indicating the guest's AP configuration has changed.
Signed-off-by: Rorie Reyes
Reviewed-by: Anthony Krowiak
Tested-by: Anthony Krowiak
---
target/s3
From: Guenter Roeck
The cpu-idle-states property causes a hard boot hang. Rather than documenting
the workaround, perform the removal from the devicetree automatically.
Signed-off-by: Guenter Roeck
Signed-off-by: Bernhard Beschow
[Bernhard: split patch, update documentation, adapt commit messa
This patch series refactors the rust PL011Registers read/write for DR:
Patch 1/2 extracts DR read logic
Patch 2/2 extracts DR write logic
Rakesh Jeyasingh (2):
rust/hw/char/pl011: Extract extract DR read logic into separate
function
rust/hw/char/pl011: Extract DR write logic into separate
Add iomem8 region register write operation emulation in generic write
function loongarch_pch_pic_write(), and use this function for iomem8
region.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 31 ++-
1 file changed, 10 insertions(+), 21 deletions(-)
diff
Queued, thanks.
Paolo
From: Juraj Marcin
To get a listening socket, we need to first create a socket, try binding
it to a certain port, and lastly starting listening to it. Each of these
operations can fail due to various reasons, one of them being that the
requested address/port is already in use. In such case, the f
After discussing with the I2C hardware designers, we confirmed that the I2c
design in AST2600 and AST2700 A1 is the same.
The datasheet will be updated accordingly for AST2700.
However, please note that bit 15 and bit 31 are not available on AST2700 A0
and FW do not set either bit 15 and bit 3
On 3/13/25 06:40, Steven Lee wrote:
AST2700 SSP(Secondary Service Processor) is a Cortex-M4 coprocessor
The patch adds support for SSP with following update:
- Introduce Aspeed27x0SSPSoCState structure in aspeed_soc.h
- Define memory map and IRQ map for AST27x0 A0 SSP SoC
- Implement initializat
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