Hi Zhao,
On 4/10/25 1:21 AM, Zhao Liu wrote:
> On Sun, Mar 30, 2025 at 06:32:28PM -0700, Dongli Zhang wrote:
>> Date: Sun, 30 Mar 2025 18:32:28 -0700
>> From: Dongli Zhang <dongli.zh...@oracle.com>
>> Subject: [PATCH v3 09/10] target/i386/kvm: support perfmon-v2 for reset
>> X-Mailer: git-send-email 2.43.5
>>
>> Since perfmon-v2, the AMD PMU supports additional registers. This update
>> includes get/put functionality for these extra registers.
>>
>> Similar to the implementation in KVM:
>>
>> - MSR_CORE_PERF_GLOBAL_STATUS and MSR_AMD64_PERF_CNTR_GLOBAL_STATUS both
>> use env->msr_global_status.
>> - MSR_CORE_PERF_GLOBAL_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_CTL both use
>> env->msr_global_ctrl.
>> - MSR_CORE_PERF_GLOBAL_OVF_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR
>> both use env->msr_global_ovf_ctrl.
>>
>> No changes are needed for vmstate_msr_architectural_pmu or
>> pmu_enable_needed().
>>
>> Signed-off-by: Dongli Zhang <dongli.zh...@oracle.com>
>> ---
>
> ...
>
>> diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
>> index 3a35fd741d..f4532e6f2a 100644
>> --- a/target/i386/kvm/kvm.c
>> +++ b/target/i386/kvm/kvm.c
>> @@ -2149,6 +2149,16 @@ static void kvm_init_pmu_info_amd(struct kvm_cpuid2
>> *cpuid, X86CPU *cpu)
>> }
>>
>> num_pmu_gp_counters = AMD64_NUM_COUNTERS_CORE;
>> +
>> + c = cpuid_find_entry(cpuid, 0x80000022, 0);
>> + if (c && (c->eax & CPUID_8000_0022_EAX_PERFMON_V2)) {
>> + pmu_version = 2;
>> + num_pmu_gp_counters = c->ebx & 0xf;
>> +
>> + if (num_pmu_gp_counters > MAX_GP_COUNTERS) {
>> + num_pmu_gp_counters = MAX_GP_COUNTERS;
>
> OK! KVM now supports 6 GP counters (KVM_MAX_NR_AMD_GP_COUNTERS).
Thank you very much for the Reviewed-by. I assume MAX_GP_COUNTERS is still good
to you here in the patch. It is to just do an upper-bound check.
Dongli Zhang
>
>> + }
>> + }
>> }
>
> Fine for me,
>
> Reviewed-by: Zhao Liu <zhao1....@intel.com>
>
