Hi Phil,
On 3/31/25 19:12, Philippe Mathieu-Daudé wrote:
Changes in the tables:
@@ -1,32 +1,32 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20240927 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
* Disassembly of tes
Hi Phil,
On 3/31/25 19:12, Philippe Mathieu-Daudé wrote:
GIC ITS can be disabled at runtime using '-M its=off',
which sets VirtMachineState::its = false. Check this
field to avoid advertising the ITS in the MADT table.
Reported-by: Udo Steinberg
Resolves: https://gitlab.com/qemu-project/qemu/-
Hi Phil,
On 3/31/25 19:12, Philippe Mathieu-Daudé wrote:
Prepare for ACPI table change in aarch64/virt/APIC.its_off.
The comment could be smth like:
Ignore APIC.its_off expected table (blob) for now until
we update it later, after fixing the code that generates
this table correctly.
?
Sig
Hi Phil,
On 3/31/25 19:12, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Please, put commit message (body) into the commits.
For example, the commit message here could quickly explain that the FACP table
changed because virtualization=on (due to PSCI conduit). I'm assum
On 31/03/2025 16.00, Shalini Chellathurai Saroja wrote:
Add Control-Program Identification data to the QEMU Object
Model (QOM), along with the timestamp in which the data was received.
Example:
virsh # qemu-monitor-command vm --pretty '{
"execute": "qom-get",
"arguments": {
"path": "/machine/scl
On 31/03/2025 16.00, Shalini Chellathurai Saroja wrote:
Register Control-Program Identification data with the live
migration infrastructure.
Signed-off-by: Shalini Chellathurai Saroja
Reviewed-by: Nina Schoetterl-Glausch
---
hw/s390x/sclpcpi.c | 27 +++
1 file change
Hi Fabiano,
On Tue, Apr 1, 2025 at 9:32 PM Fabiano Rosas wrote:
>
> Jack Wang writes:
>
> > I hit following error which testing migration in pure RoCE env:
> > "-incoming rdma:[::]:8089: RDMA ERROR: You only have RoCE / iWARP devices
> > in your
> > systems and your management software has spec
On 31/03/2025 16.00, Shalini Chellathurai Saroja wrote:
Implement the Service-Call Logical Processor (SCLP) event
type Control-Program Identification (CPI) in QEMU. This
event is used to send CPI identifiers from the guest to the
host. The CPI identifiers are: system type, system name,
system lev
On 25/03/31 08:41AM, Cédric Le Goater wrote:
> On 3/29/25 15:26, Aditya Gupta wrote:
> > Power8E and Power8NVL variants are not of much use in QEMU now, and not
> > being maintained either.
> >
> > Newer skiboot might not be able to boot Power8NVL since skiboot v7.0
> >
>
> It is worth mentionin
I hit following error which testing migration in pure RoCE env:
"-incoming rdma:[::]:8089: RDMA ERROR: You only have RoCE / iWARP devices in
your
systems and your management software has specified '[::]', but IPv6 over RoCE /
iWARP is not supported in Linux.#012'."
In our setup, we use rdma bind
On 2/4/25 06:06, Philippe Mathieu-Daudé wrote:
Cc'ing Pierrick
On 12/1/23 08:17, Philippe Mathieu-Daudé wrote:
On 11/1/23 21:02, Richard Henderson wrote:
On 1/10/23 08:43, Philippe Mathieu-Daudé wrote:
+++ b/target/arm/cpu.h
@@ -26,6 +26,7 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h
Hi ,
Thank you for reviewing the previous versions of this patch. I've
incorporated all the feedback in v4:
1. set .min_access_size=4
2. Simplified swapping to bswap32 only
Note: I realized after sending v4 that the commit message still referenced
the old size-specific swap approach -"Implement s
On 10/1/23 17:44, Philippe Mathieu-Daudé wrote:
GPT and GPIO are numbered from #1.
Fixes: 757282ada8 ("i.MX: Add i.MX7 SOC.")
Fixes: 31cbf933f0 ("i.MX: Add i.MX6UL SOC")
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/fsl-imx6ul.c | 4 ++--
hw/arm/fsl-imx7.c | 4 ++--
2 files changed, 4
Cc'ing Pierrick
On 12/1/23 08:17, Philippe Mathieu-Daudé wrote:
On 11/1/23 21:02, Richard Henderson wrote:
On 1/10/23 08:43, Philippe Mathieu-Daudé wrote:
+++ b/target/arm/cpu.h
@@ -26,6 +26,7 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "qapi/qapi-types-common.h"
+#includ
On 1/4/25 10:09, Philippe Mathieu-Daudé wrote:
All targets have been converted to TCGCPUOps::mmu_index(),
remove the now unused CPUClass::mmu_index().
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/cpu-mmu-index.h | 4 +---
include/hw/core/cpu.h| 2 --
2 files changed, 1 ins
On 25/3/25 05:58, Pierrick Bouvier wrote:
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 4
cpu-target.c | 4
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index
On Mon, Mar 31, 2025 at 07:26:33PM -0500, saman wrote:
> This change introduces initial support for tracing and logging in Rust-based
> QEMU code. As an example, tracing and logging have been implemented in the
> pl011 device, which is written in Rust.
>
> - Updated `rust/wrapper.h` to include the
Hi,
Gentle ping on this patch.
Thanks,
Jim Shu
On Thu, Mar 20, 2025 at 3:22 AM Jim Shu wrote:
>
> This patch series contains several sstc fixes:
>
> (1) Writing to ACLINT mtime should also update the period of S/VS-mode
> timer, just like M-mode timer.
> (2) VSTIP bit of $mip CSR should ch
On 3/19/2025 2:50 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Brian Cain
Sent: Friday, February 28, 2025 11:28 PM
To: qemu-devel@nongnu.org
Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@
On 3/17/2025 1:43 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Brian Cain
Sent: Friday, February 28, 2025 11:28 PM
To: qemu-devel@nongnu.org
Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@
On 3/3/2025 6:26 AM, Philippe Mathieu-Daudé wrote:
Hi Brian and Sid,
On 1/3/25 18:20, Brian Cain wrote:
From: Sid Manning
Co-authored-by: Matheus Tavares Bernardino
Co-authored-by: Damien Hedde
Signed-off-by: Brian Cain
---
MAINTAINERS | 2 +
docs/devel/hexagon-l2
Please separate the changes, one patch for POWERPC_DEPRECATED_CPU,
another for PowerNV deprecation. More CPUs could be deprecated.
By PowerNV deprecation, you mean Power8E/8NVL CPUs right ?
yes. Just the CPUs which implies the chips.
Like there's no powernv8e machine as such, and powernv8
Hi Nick,
On 1/4/25 13:44, Nicholas Piggin wrote:
This requires some adjustments to callers to avoid possible behaviour
changes for PCI devices.
Signed-off-by: Nicholas Piggin
---
include/hw/ipmi/ipmi.h | 5 +
hw/acpi/ipmi.c | 2 +-
hw/ipmi/isa_ipmi_bt.c | 1 +
On Thu, Mar 27, 2025 at 11:55:57AM -0400, Stefan Hajnoczi wrote:
> On Tue, Mar 25, 2025 at 05:06:54PM +0100, Hanna Czenczek wrote:
> > FUSE allows creating multiple request queues by "cloning" /dev/fuse FDs
> > (via open("/dev/fuse") + ioctl(FUSE_DEV_IOC_CLONE)).
> >
> > We can use this to impleme
On Tue, 1 Apr 2025, Nicholas Piggin wrote:
On Tue Apr 1, 2025 at 12:26 AM AEST, BALATON Zoltan wrote:
The FDT does not normally store name properties but reconstructs it
from path but each node in Open Firmware should at least have this
property. This is correctly handled in getprop but nextprop
On 4/1/25 03:32, Philippe Mathieu-Daudé wrote:
Move the TCG-specific cpu-ldst*.h headers to
the accel/tcg/ namespace.
Philippe Mathieu-Daudé (3):
exec: Restrict 'cpu-ldst-common.h' to accel/tcg/
exec: Restrict 'cpu_ldst.h' to accel/tcg/
exec: Do not include 'accel/tcg/cpu-ldst.h' in 'ex
TD guest can use TDG.VP.VMCALL to request
termination. KVM translates such request into KVM_EXIT_SYSTEM_EVENT with
type of KVM_SYSTEM_EVENT_TDX_FATAL.
Add hanlder for such exit. Parse and print the error message, and
terminate the TD guest in the handler.
Signed-off-by: Xiaoyao Li
---
Changes in
On 4/1/25 03:09, Philippe Mathieu-Daudé wrote:
mmu_index() is specific to TCG SoftMMU,
moveCPUClass::mmu_index() toTCGCPUOps::mmu_index().
Philippe Mathieu-Daudé (24):
hw/core/cpu: UpdateCPUClass::mmu_index docstring
accel/tcg: IntroduceTCGCPUOps::mmu_index() callback
target/alpha: Rest
On Tue, Apr 01, 2025 at 02:05:40PM +0200, Kevin Wolf wrote:
> > Maybe we could make setting @iothreads here and the generic
> > BlockExportOptions.iothread at the same time an error. That would save us
> > the explanation here.
>
> This raises the question if the better interface wouldn't be to c
On Tue, Mar 25, 2025 at 05:06:55PM +0100, Hanna Czenczek wrote:
> We probably want to support larger write sizes than just 4k; 64k seems
> nice. However, we cannot read partial requests from the FUSE FD, we
> always have to read requests in full; so our read buffer must be large
> enough to accomm
On 1/4/25 15:27, Nicholas Piggin wrote:
On Tue Apr 1, 2025 at 9:57 PM AEST, Philippe Mathieu-Daudé wrote:
Hi Nick,
On 1/4/25 13:44, Nicholas Piggin wrote:
This requires some adjustments to callers to avoid possible behaviour
changes for PCI devices.
Signed-off-by: Nicholas Piggin
---
incl
TDX architecture forcibly sets some CPUID bits for TD guest that VMM
cannot disable it. They are fixed1 bits.
Fixed1 bits are not covered by tdx_caps.cpuid (which only contians the
directly configurable bits), while fixed1 bits are supported for TD guest
obviously.
Add fixed1 bits to tdx_supporte
For TDX, only limited KVM PV features are supported.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/tdx.c | 20
1 file changed, 20 insertions(+)
diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c
index e07cd9a1ee15..7382b53fcc51 100644
--- a/target/i386/kvm/tdx.c
+++
On 4/1/25 09:43, Philippe Mathieu-Daudé wrote:
Be sure to allocate the temp frame if it wasn't.
Fixes: c896fe29d6c ("TCG code generator")
Reported-by: Michael Tokarev
Reported-by: Helge Konetzka
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2891
Resolves: https://gitlab.com/qemu-proj
From: Marco Cavenati
The SEEK_CUR case in qio_channel_block_seek was incorrectly using the
'whence' parameter instead of the 'offset' parameter when calculating the
new position.
Fixes: 65cf200a51 ("migration: introduce a QIOChannel impl for BlockDriverState
VMState")
Signed-off-by: Marco Caven
TDX doesn't support SMM and VMM cannot emulate SMM for TDX VMs because
VMM cannot manipulate TDX VM's memory.
Disable SMM for TDX VMs and error out if user requests to enable SMM.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
target/i386/kvm/tdx.c | 9 +
1 file changed, 9 inser
Jack Wang writes:
> I hit following error which testing migration in pure RoCE env:
> "-incoming rdma:[::]:8089: RDMA ERROR: You only have RoCE / iWARP devices in
> your
> systems and your management software has specified '[::]', but IPv6 over RoCE
> /
> iWARP is not supported in Linux.#012'."
On Wed, Apr 02, 2025 at 12:01:47AM +1000, Nicholas Piggin wrote:
> These little things came up when looking at behaviour of IPMI with
> the bmc-sim implementation running the ppc powernv machine, and
> trying to clean up error messages and missing features.
This all looks good to me. Thanks to Ph
On 1/4/25 16:59, Pierrick Bouvier wrote:
On 4/1/25 07:44, Philippe Mathieu-Daudé wrote:
On 1/4/25 16:33, Pierrick Bouvier wrote:
On 3/31/25 23:15, Philippe Mathieu-Daudé wrote:
Hi Pierrick,
On 1/4/25 01:42, Pierrick Bouvier wrote:
Nothing prevent plugins to be enabled on this platform for us
For QEMU VMs,
- PKS is configured via CPUID_7_0_ECX_PKS, e.g., -cpu xxx,+pks and
- PMU is configured by x86cpu->enable_pmu, e.g., -cpu xxx,pmu=on
While the bit 30 (PKS) and bit 63 (PERFMON) of TD's attributes are also
used to configure the PKS and PERFMON/PMU of TD, reuse the existing
configu
This is the v8 series of TDX QEMU enabling and the series is also available
at github:
https://github.com/intel-staging/qemu-tdx/tree/tdx-qemu-upstream-v8
To boot TD guest, please always use the latest TDX module (1.5) and OVMF
available.
Note, this series has a dependency on
https://lore.kernel.
Add a generic API for host PCI MMIO reads/writes
(e.g. Linux VFIO BAR accesses). The functions access
little endian memory and returns the result in
host cpu endianness.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Farhan Ali
---
include/qemu/host-pci-mmio.h | 116
On 4/1/25 01:24, Philippe Mathieu-Daudé wrote:
On 18/3/25 22:31, Richard Henderson wrote:
These need to be per-target for 'abi_ptr'. Expand inline to
the *_data_ra api with ra == 0.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 123 +++
Use the host PCI MMIO functions to read/write
to NVMe registers, rather than directly accessing
them.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Farhan Ali
---
block/nvme.c | 37 +
1 file changed, 21 insertions(+), 16 del
Starting with z15 (or newer) we can execute mmio
instructions from userspace. On older platforms
where we don't have these instructions available
we can fallback to using system calls to access
the PCI mapped resources.
This patch adds helper functions for mmio reads
and writes for s390x.
Reviewe
Hi,
Recently on s390x we have enabled mmap support for vfio-pci devices [1].
This allows us to take advantage and use userspace drivers on s390x. However,
on s390x we have special instructions for MMIO access. Starting with z15
(and newer platforms) we have new PCI Memory I/O (MIO) instructions w
On 3/31/25 23:15, Philippe Mathieu-Daudé wrote:
Hi Pierrick,
On 1/4/25 01:42, Pierrick Bouvier wrote:
Nothing prevent plugins to be enabled on this platform for user
binaries, only the option in the driver is missing.
Per commit 903e870f245 ("plugins/api: split out binary
path/start/end/entry
On Tue, Apr 01, 2025 at 18:57:30 +0300, Vladimir Sementsov-Ogievskiy wrote:
> For change, pause, resume, complete, dismiss and finalize actions
> corresponding job- and block-job commands are almost equal. The
> difference is in find_block_job_locked() vs find_job_locked()
> functions. What's diffe
If the dont-log flag is set in the 'timer use' field for the
'set watchdog' command, a watchdog timeout will not get logged as
a timer use expiration.
Signed-off-by: Nicholas Piggin
---
hw/ipmi/ipmi_bmc_sim.c | 26 +-
1 file changed, 17 insertions(+), 9 deletions(-)
diff
On 4/1/25 01:32, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
include/{exec => accel/tcg}/cpu-ldst-common.h | 6 +++---
include/exec/cpu_ldst.h | 2 +-
accel/tcg/translator.c| 2 +-
3 files changed, 5 insertions(+), 5
On 3/21/25 10:26, Jamin Lin wrote:
According to the AST2700 design, the data source address is 64-bit, with
R_HASH_SRC_HI storing bits [63:32] and R_HASH_SRC storing bits [31:0].
Similarly, the digest address is 64-bit, with R_HASH_DEST_HI storing bits
R_HASH_DIGEST_HIGH would be easier to unde
From: Xiaoyao Li
Introduce kvm_arch_pre_create_vcpu(), to perform arch-dependent
work prior to create any vcpu. This is for i386 TDX because it needs
call TDX_INIT_VM before creating any vcpu.
The specific implemnet of i386 will be added in the future patch.
Signed-off-by: Xiaoyao Li
Acked-by:
The following changes since commit 0f15892acaf3f50ecc20c6dad4b3ebdd701aa93e:
Merge tag 'pull-riscv-to-apply-20250328' of
https://github.com/alistair23/qemu into staging (2025-03-28 08:06:53 -0400)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/hw-misc-202503
To allow execute confidential guest specific cpu init operations.
Signed-off-by: Xiaoyao Li
---
Changes in v6:
- new patch;
---
target/i386/confidential-guest.h | 11 +++
target/i386/cpu.c| 10 ++
2 files changed, 21 insertions(+)
diff --git a/target/i386/confid
On Tue Apr 1, 2025 at 11:09 PM AEST, Corey Minyard wrote:
> On Tue, Apr 01, 2025 at 09:44:09PM +1000, Nicholas Piggin wrote:
>> This requires some adjustments to callers to avoid possible behaviour
>> changes for PCI devices.
>>
>> Signed-off-by: Nicholas Piggin
>> ---
>> include/hw/ipmi/ipmi.h
For change, pause, resume, complete, dismiss and finalize actions
corresponding job- and block-job commands are almost equal. The
difference is in find_block_job_locked() vs find_job_locked()
functions. What's different?
1. find_block_job_locked() do check, is found job a block-job. This OK
whe
ull-aspeed-20250401
for you to fetch changes up to 20ab88a9066bcacc28acbd7cbe2c617d90bfb27e:
hw/misc/aspeed_scu: Correct minimum access size for AST2500 / AST2600
(2025-04-01 11:29:25 +0200)
aspeed queue:
* Fixed SCU access size
Mask out unsupported bits and return failure if attempting to set
any. This is not required by the IPMI spec, but it does require that
system software not change bits it isn't aware of.
Signed-off-by: Nicholas Piggin
---
hw/ipmi/ipmi_bmc_sim.c | 10 +-
1 file changed, 9 insertions(+), 1
Implement TDX specific ConfidentialGuestSupportClass::kvm_init()
callback, tdx_kvm_init().
Mark guest state is proctected for TDX VM. More TDX specific
initialization will be added later.
Signed-off-by: Xiaoyao Li
---
Changes in v6:
- remove Acked-by from Gerd since the patch changed due to us
This patch adds the new VM state change cb type `VMChangeStateHandlerWithRet`,
which has return value for `VMChangeStateEntry`.
Thus, we can register a new VM state change cb with return value for device.
Note that `VMChangeStateHandler` and `VMChangeStateHandlerWithRet` are mutually
exclusive and
At the end of the VM live migration, the vhost device will be stopped.
Currently, if the vhost-user backend crashes, vhost device's set_status()
would not return failure, live migration won't perceive the disconnection
with the backend. After the live migration is successful, the stale inflight
IO
On 1/4/25 11:54, Aditya Gupta wrote:
On 25/03/31 01:37PM, Philippe Mathieu-Daudé wrote:
On 30/3/25 23:10, Aditya Gupta wrote:
<...snip...>
Reviewed-by: Philippe Mathieu-Daudé
Thanks for the tag, Philippe !
I will be posting a v5 with this patch split into 2 as suggested by
Cedric (one int
Invoke KVM_TDX_INIT_VM in kvm_arch_pre_create_vcpu() that
KVM_TDX_INIT_VM configures global TD configurations, e.g. the canonical
CPUID config, and must be executed prior to creating vCPUs.
Use kvm_x86_arch_cpuid() to setup the CPUID settings for TDX VM.
Note, this doesn't address the fact that Q
On 4/1/25 01:32, Philippe Mathieu-Daudé wrote:
Mechanical change using:
$ sed -i -e 's,exec/cpu_ldst,accel/tcg/cpu-ldst,' \
$(git grep -l exec/cpu_ldst.h)
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
On 4/1/25 01:32, Philippe Mathieu-Daudé wrote:
Only 2 files requiring "accel/tcg/cpu-ldst.h" API do not
include it:
- accel/tcg/cpu-exec.c
- target/arm/tcg/sve_helper.c
Include it there and remove it from "exec/exec-all.h".
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
On 4/1/25 07:44, Philippe Mathieu-Daudé wrote:
On 1/4/25 16:33, Pierrick Bouvier wrote:
On 3/31/25 23:15, Philippe Mathieu-Daudé wrote:
Hi Pierrick,
On 1/4/25 01:42, Pierrick Bouvier wrote:
Nothing prevent plugins to be enabled on this platform for user
binaries, only the option in the driver
On Tue, Mar 25, 2025 at 05:06:54PM +0100, Hanna Czenczek wrote:
> FUSE allows creating multiple request queues by "cloning" /dev/fuse FDs
> (via open("/dev/fuse") + ioctl(FUSE_DEV_IOC_CLONE)).
>
> We can use this to implement multi-threading.
>
> Note that the interface presented here differs fro
On 1/4/25 16:01, Nicholas Piggin wrote:
This requires some adjustments to callers to avoid possible behaviour
changes for PCI devices.
Signed-off-by: Nicholas Piggin
---
include/hw/ipmi/ipmi.h | 5 +
hw/acpi/ipmi.c | 3 ++-
hw/ipmi/isa_ipmi_bt.c | 1 +
hw/ipmi/i
On Thu, Mar 27, 2025 at 02:14:25PM +0100, Kevin Wolf wrote:
> Am 26.03.2025 um 18:46 hat Stefan Hajnoczi geschrieben:
> > On Wed, Mar 26, 2025 at 06:13:44PM +0100, Kevin Wolf wrote:
> > > Am 25.03.2025 um 21:49 hat ~h0lyalg0rithm geschrieben:
> > > > From: Suraj Shirvankar
> > > >
> > > > Signed-
On 1/4/25 16:33, Pierrick Bouvier wrote:
On 3/31/25 23:15, Philippe Mathieu-Daudé wrote:
Hi Pierrick,
On 1/4/25 01:42, Pierrick Bouvier wrote:
Nothing prevent plugins to be enabled on this platform for user
binaries, only the option in the driver is missing.
Per commit 903e870f245 ("plugins/
KVM mandates kernel_irqchip to be split mode.
Set it to split mode automatically when users don't provide an explicit
value, otherwise check it to be the split mode.
Suggested-by: Daniel P. Berrangé
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/tdx.c | 8
1 file changed, 8 insertions(
On Tue, Mar 25, 2025 at 05:06:51PM +0100, Hanna Czenczek wrote:
> Manually read requests from the /dev/fuse FD and process them, without
> using libfuse. This allows us to safely add parallel request processing
> in coroutines later, without having to worry about libfuse internals.
> (Technically,
On 18/3/25 22:31, Richard Henderson wrote:
These need to be per-target for 'abi_ptr'. Expand inline to
the *_data_ra api with ra == 0.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 123 ++--
accel/tcg/ldst_c
Be sure to allocate the temp frame if it wasn't.
Fixes: c896fe29d6c ("TCG code generator")
Reported-by: Michael Tokarev
Reported-by: Helge Konetzka
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2891
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2899
Signed-off-by: Philippe Ma
Reuse "-cpu,tsc-frequency=" to get user wanted tsc frequency and call VM
scope VM_SET_TSC_KHZ to set the tsc frequency of TD before KVM_TDX_INIT_VM.
Besides, sanity check the tsc frequency to be in the legal range and
legal granularity (required by TDX module).
Signed-off-by: Xiaoyao Li
Acked-by
AioContext has its own io_uring instance for file descriptor monitoring.
The disk I/O io_uring code was developed separately. Originally I
thought the characteristics of file descriptor monitoring and disk I/O
were too different, requiring separate io_uring instances.
Now it has become clear to me
Introduce the aio_add_sqe() API for submitting io_uring requests in the
current AioContext. This allows other components in QEMU, like the block
layer, to take advantage of io_uring features without creating their own
io_uring context.
This API supports nested event loops just like file descriptor
For some reason the patch series didn't reach the mailing list. Resending.
Every AioContext has an io_uring context for file descriptor monitoring. In
addition, block/io_uring.c also has an io_uring context for disk I/O. This
patch series eliminates the extra io_uring context so that AioContext ha
In the early days of io_uring it was possible for io_uring_setup(2) to
fail due to exhausting RLIMIT_MEMLOCK. QEMU's solution was to fall back
to epoll(7) or ppoll(2) when io_uring could not be used in an
AioContext.
Nowadays io_uring memory is accounted differently so io_uring_setup(2)
won't fail
On 4/1/25 02:20, Philippe Mathieu-Daudé wrote:
Rename riscv_cpu_mmu_index() -> rx_cpu_mmu_index().
Fixes: ef5cc166da1 ("target/rx: Populate CPUClass.mmu_index")
Signed-off-by: Philippe Mathieu-Daudé
---
target/rx/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by:
On 3/21/25 10:25, Jamin Lin wrote:
Currently, users define multiple local variables within different if-statements.
To improve readability and maintain consistency in variable naming, rename the
variables accordingly.
Introduced "sg_addr" to clearly indicate the scatter-gather mode buffer address
On 1/4/25 13:44, Nicholas Piggin wrote:
IPMI drivers use p/k suffix in variable names depending on bt or kcs.
The pci bt driver must have come from the kcs driver because it's
still using k suffixes in some cases. Rename.
Signed-off-by: Nicholas Piggin
---
hw/ipmi/pci_ipmi_bt.c | 38 +
From: Isaku Yamahata
Three sha384 hash values, mrconfigid, mrowner and mrownerconfig, of a TD
can be provided for TDX attestation. Detailed meaning of them can be
found:
https://lore.kernel.org/qemu-devel/31d6dbc1-f453-4cef-ab08-4813f4e0f...@intel.com/
Allow user to specify those values via pro
KVM translates TDG.VP.VMCALL to KVM_HC_MAP_GPA_RANGE, and QEMU
needs to enable user exit on KVM_HC_MAP_GPA_RANGE in order to handle the
memory conversion requested by TD guest.
Signed-off-by: Xiaoyao Li
---
changes in v6:
- new patch;
---
target/i386/kvm/tdx.c | 7 +++
1 file changed, 7 ins
Philippe Mathieu-Daudé writes:
> First, the VMapple machine only works with the ARM 'host' CPU
> type, which isn't accepted for QTest:
>
> $ qemu-system-aarch64 -M vmapple -accel qtest
> qemu-system-aarch64: The 'host' CPU type can only be used with KVM or HVF
>
> Second, the QTest framework
Nikita Shubin writes:
> From: Nikita Shubin
>
> Signed-off-by: Nikita Shubin
> ---
> tests/qtest/meson.build | 1 +
> tests/qtest/stm32-dma-test.c | 415 +++
> 2 files changed, 416 insertions(+)
> create mode 100644 tests/qtest/stm32-dma-test.c
>
> diff
Maintain a TDX specific supported CPUID set, and use it to mask the
common supported CPUID value of KVM. It can avoid newly added supported
features (reported via KVM_GET_SUPPORTED_CPUID) for common VMs being
falsely reported as supported for TDX.
As the first step, initialize the TDX supported CP
The TD HOB list is used to pass the information from VMM to TDVF. The TD
HOB must include PHIT HOB and Resource Descriptor HOB. More details can
be found in TDVF specification and PI specification.
Build the TD HOB in TDX's machine_init_done callback.
Co-developed-by: Isaku Yamahata
Signed-off-b
On 11.03.2025 14:04, Cédric Le Goater wrote:
On 3/7/25 14:45, Maciej S. Szmigiero wrote:
On 7.03.2025 13:03, Cédric Le Goater wrote:
On 3/7/25 11:57, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
There's already a max in-flight VFIO device state buffers *count* limit,
no. there is
This requires some adjustments to callers to avoid possible behaviour
changes for PCI devices.
Signed-off-by: Nicholas Piggin
---
include/hw/ipmi/ipmi.h | 5 +
hw/acpi/ipmi.c | 3 ++-
hw/ipmi/isa_ipmi_bt.c | 1 +
hw/ipmi/isa_ipmi_kcs.c | 1 +
hw/ipmi/pci_ipmi_bt.
On 3/21/25 10:26, Jamin Lin wrote:
Enable accumulative mode for direct access mode operations. In direct access
mode, only a single source buffer is used, so the "iovec" count is set to 1.
If "acc_mode" is enabled:
1. Accumulate "total_req_len" with the current request length ("plen").
2. Check f
Integrate TDX's TDX_REPORT_FATAL_ERROR into QEMU GuestPanic facility
Originated-from: Isaku Yamahata
Signed-off-by: Xiaoyao Li
Acked-by: Markus Armbruster
---
Changes in v8:
- use g_strdup() for copy string;
- use the new data ABI of KVM_SYSTEM_EVENT_TDX_FATAL to grab gpa info;
Changes in v6:
On Mon, 2025-03-31 at 16:00 +0200, Shalini Chellathurai Saroja wrote:
> Add Control-Program Identification data to the QEMU Object
> Model (QOM), along with the timestamp in which the data was received.
>
> Example:
> virsh # qemu-monitor-command vm --pretty '{
> "execute": "qom-get",
> "arguments
Some CPUID bits are controlled by XFAM. They are not covered by
tdx_caps.cpuid (which only contians the directly configurable bits), but
they are actually supported when the related XFAM bit is supported.
Add these XFAM controlled bits to TDX supported CPUID bits based on the
supported_xfam.
Besi
On 3/21/25 10:26, Jamin Lin wrote:
The AST2700 CPU, based on the Cortex-A35, is a 64-bit processor with a 64-bit
DRAM address space. To support future AST2700 updates, a new "digest_addr"
variable is introduced with a 64-bit data type.
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_hace.c | 4 ++
Mask out unsupported bits and return failure if attempting to set
any. This is not required by the IPMI spec, but it does require that
system software not change bits it isn't aware of.
Signed-off-by: Nicholas Piggin
---
hw/ipmi/ipmi_bmc_sim.c | 10 +-
1 file changed, 9 insertions(+), 1
KVM neithers allow writing to MSR_IA32_APICBASE for TDs, nor allow for
KVM_SET_LAPIC[*].
Note, KVM_GET_LAPIC is also disallowed for TDX. It is called in the path
do_kvm_cpu_synchronize_state()
-> kvm_arch_get_registers()
-> kvm_get_apic()
and it's already disllowed for confidential gues
Invoke KVM_TDX_FINALIZE_VM to finalize the TD's measurement and make
the TD vCPUs runnable once machine initialization is complete.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
target/i386/kvm/tdx.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/i386/kvm/tdx.c b/target/i
These little things came up when looking at behaviour of IPMI with
the bmc-sim implementation running the ppc powernv machine, and
trying to clean up error messages and missing features.
Since v1 (thanks to Corey for review and suggestions):
- Added fwinfo to PCI devices
- Report interrupt number
Linux issues this command when booting a powernv machine.
Signed-off-by: Nicholas Piggin
---
include/hw/ipmi/ipmi.h | 10 +++
hw/ipmi/ipmi_bmc_sim.c | 68 --
hw/ipmi/ipmi_bt.c | 2 ++
hw/ipmi/ipmi_kcs.c | 1 +
4 files changed, 79 insertions(
1 - 100 of 188 matches
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