On 3/21/25 10:26, Jamin Lin wrote:
The AST2700 CPU, based on the Cortex-A35, is a 64-bit processor with a 64-bit
DRAM address space. To support future AST2700 updates, a new "digest_addr"
variable is introduced with a 64-bit data type.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
---
hw/misc/aspeed_hace.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index 9771d6e490..8cf3f194a5 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/misc/aspeed_hace.c
@@ -148,6 +148,7 @@ static void do_hash_operation(AspeedHACEState *s, int algo,
bool sg_mode,
bool sg_acc_mode_final_request = false;
g_autofree uint8_t *digest_buf = NULL;
struct iovec iov[ASPEED_HACE_MAX_SG];
+ uint64_t digest_addr = 0;
Error *local_err = NULL;
uint32_t total_msg_len;
size_t digest_len = 0;
@@ -257,7 +258,8 @@ static void do_hash_operation(AspeedHACEState *s, int algo,
bool sg_mode,
return;
}
- if (address_space_write(&s->dram_as, s->regs[R_HASH_DEST],
+ digest_addr = deposit64(digest_addr, 0, 32, s->regs[R_HASH_DEST]);
As on the previous patch, an helper would be useful and is there
an alignment constraint ?
Thanks,
C.
+ if (address_space_write(&s->dram_as, digest_addr,
MEMTXATTRS_UNSPECIFIED,
digest_buf, digest_len)) {
qemu_log_mask(LOG_GUEST_ERROR,
