> -Original Message-
> From: Cédric Le Goater
> Sent: Friday, March 7, 2025 3:44 PM
> To: Jamin Lin ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Andrew Jeffery ;
> Joel Stanley ; open list:All patches CC here
> ; open list:ASPEED BMCs
>
> Cc: Troy Lee
> Subject: Re: [PATCH v6 00/29] Sup
Currently, these trace events only refer to INTC. To simplify the INTC model,
both INTC(CPU Die) and INTCIO(IO Die) will share the same helper functions.
However, it is difficult to recognize whether these trace events are comes from
INTC or INTCIO. To make these trace events more readable, adds o
John Snow writes:
> ``:error: descr`` can now be used to document error conditions. The
> format of the description is not defined here; so the ability to name
> specific types is left to the document writer.
>
> Signed-off-by: John Snow
By convention, the description is a bullet list, but we d
John Snow writes:
> This adds special rendering for Sphinx's typed field lists.
>
> This patch does not add any QAPI-aware markup, rendering, or
> cross-referencing for the type names, yet. That feature requires a
> subclass to TypedField which will happen in its own commit quite a bit
> later in
On 06/03/2025 13.46, Stefan Hajnoczi wrote:
Let people know that QEMU is participating in Google Summer of Code so
that they can apply for an internship this summer.
Thanks, looks good, applied now:
https://www.qemu.org/2025/03/06/gsoc-2025/
Thomas
On 3/7/25 04:59, Jamin Lin wrote:
Currently, the size of the "regs" array is 0x2000, which is too large. So far,
it only uses "GICINT128 to `GICINT134", and the offsets from 0 to 0x1000 are
unused. To save code size and avoid mapping large unused gaps, update to only
map the useful set of registe
To improve readability, sort the IRQ table by IRQ number.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed_ast27x0.c | 50 -
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_as
Currently, AST2700 SoC only supports A0. To support AST2700 A1, rename its IRQ
table and machine name.
To follow the machine deprecation rule, the initial machine "ast2700-evb" is
aliased to "ast2700a0-evb." In the future, we will alias "ast2700-evb" to new
SoCs, such as "ast2700a1-evb."
Signed-o
Hello,
On 3/6/25 19:05, Nabih Estefan wrote:
Hi Cédric,
We have a custom machine and a custom image using the AST27x0 A0. I ran
some of our internal tests using these patches. They even fixed some of the
errors we’d been seeing recently!
I’m also working on testing through the A1 patches, will
On 3/3/2025 3:30 AM, Dongli Zhang wrote:
> QEMU uses the kvm_get_msrs() function to save Intel PMU registers from KVM
> and kvm_put_msrs() to restore them to KVM. However, there is no support for
> AMD PMU registers. Currently, has_pmu_version and num_pmu_gp_counters are
> initialized based on cpui
Let people know that QEMU is participating in Google Summer of Code so
that they can apply for an internship this summer.
Signed-off-by: Stefan Hajnoczi
---
_posts/2025-03-06-gsoc-2025.md | 40 ++
1 file changed, 40 insertions(+)
create mode 100644 _posts/2025-03
On 3/7/25 04:59, Jamin Lin wrote:
v1:
1. Refactor INTC model to support both INTC0 and INTC1.
2. Support AST2700 A1.
3. Create ast2700a0-evb machine.
v2:
To streamline the review process, split the following patch series into
three parts.
https://patchwork.kernel.org/project/q
> I didn't know if I would need to wait until this patch is merged into
> mainline QEMU. That's why I didn't add my signed-off.
No problem if Xiaoyao is okay with it (copyright of patches need to
honor the original author & signed-off). IMO, if your series is accepted
first, it also helps to reduc
On 3/3/2025 3:30 AM, Dongli Zhang wrote:
> When the PERFCORE is disabled with "-cpu host,-perfctr-core", it is
> reflected in in guest dmesg.
>
> [0.285136] Performance Events: AMD PMU driver.
>
> However, the guest CPUID indicates the PerfMonV2 is still available.
>
> CPU:
>Extended Per
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
On 3/7/25 04:59, Jamin Lin wrote:
Currently, the size of the "regs" array is 0x2000, which is too large. To save
code size and avoid mapping large unused gaps, will update it to only map the
useful set of registers. This update will support multiple sub-regions with
different sizes.
To address t
> 1. Remove "kvm_enabled() && IS_AMD_CPU(env)" since the bit is reserved by
> Intel.
>
> 2. Add your Reviewed-by.
Yes, this is exactly what I mean!
Regards,
Zhao
On Thu, 2025-03-06 at 15:49 -0700, Alex Williamson wrote:
> On Fri, 7 Mar 2025 02:01:20 +0800
> Tomita Moeko wrote:
>
> > This patchset intends to decouple existing quirks from legacy mode.
> > Currently all quirks depends on legacy mode (except x-igd-opregion),
> > which includes following cond
Replace legacy reset callback register device_class_set_legacy_reset()
with new function resettable_class_set_parent_phases(). With new API,
it will call reset callback of parent object and then itself.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_extioi.c | 12
include/hw/
Here add reset support with LoongArch irqchips, including pch pic, ipi
and extioi interrupt controllers. For ipi irqchip, reset interface is
missing. For extioi irqchip, legacy reset callback is replaced with
new API and internal HW/SW states are cleared also. For pch pic irqchip,
legacy reset call
Add reset support with extioi irqchip, and register reset callback
support with new API resettable_class_set_parent_phases(). Clear
internal HW registers and SW state when virt machine resets.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_extioi_common.c | 41 +++
inc
Float register name f0 - f31 is not recognized with clang compiler
with LoongArch64 target, its name should be $f0 - $f31. It is ok
for both gcc and clang compiler.
Signed-off-by: Bibo Mao
---
host/include/loongarch64/host/bufferiszero.c.inc | 6 --
1 file changed, 4 insertions(+), 2 deletio
John Snow writes:
> Add a little special markup for registering "Since:" information. Adding
> it as an option instead of generic content lets us hoist the information
> into the Signature bar, optionally put it in the index, etc.
>
> Signed-off-by: John Snow
> ---
> docs/sphinx/qapi_domain.py
Refactors the INTC to distinguish between input and output pin indices,
improving interrupt handling clarity and accuracy.
Updated the functions to handle both input and output pin indices.
Added detailed logging for input and output pin indices in trace events.
These changes ensure that the INTC
The INTC controller supports GICINT128 to GICINT136, mapping 1:1 to input and
output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was used to
derive the IRQ index numbers.
However, the INTC controller also supports GICINT192_201, mapping 1 input IRQ
pin to 10 output IRQ pins. The pin nu
The virtio_balloon test is currently hanging for unknown reasons
when being run on the shared gitlab CI runners (which don't provide
KVM, thus it's running in TCG mode there). All other functional tests
that use the same asset (the Fedora 31 kernel) have already been
marked to work only with KVM in
John Snow writes:
> This commit adds a stubbed version of QAPICommand that utilizes the
> QAPIObject class, the qapi:command directive, the :qapi:cmd:
> cross-reference role, and the "command" object type in the QAPI object
> registry.
>
> This commit also adds the aforementioned generic QAPIObje
John Snow writes:
> Create a compat module that handles sphinx cross-version compatibility
> issues. For the inaugural function, add a nested_parse() helper that
> handles differences in line number tracking for nested directive body
> parsing.
>
> Spoilers: there are more cross-version hacks to
The behavior of the enable and status registers is almost identical between
INTC(CPU Die) and INTCIO(IO Die). To reduce duplicated code, adds
"aspeed_intc_enable_handler" functions to handle enable register write
behavior and "aspeed_intc_status_handler" functions to handle status
register write be
Modified the temperature hwmon path to use a wildcard to handle different SDK
versions: "cat /sys/bus/i2c/devices/1-004d/hwmon/hwmon*/temp1_input".
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
tests/functional/test_aarch64_aspeed.py | 4 ++--
1 file changed, 2 insertions(+), 2 del
The INTC controller supports GICINT128 to GICINT136, mapping 1:1 to input and
output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was used to
derive the IRQ index numbers.
However, the INTC controller also supports GICINT192_201, mapping 1 input IRQ
pin to 10 output IRQ pins. The pin nu
On 3/6/25 15:41, Richard Henderson wrote:
Re-use the TARGET_PAGE_BITS_VARY mechanism to define
TARGET_PAGE_SIZE and friends when not compiling per-target.
Inline qemu_target_page_{size,mask,bits} as they are now trivial.
Signed-off-by: Richard Henderson
---
After this, we could in fact remove
Currently, the size of the regs array is 0x2000, which is too large. So far,
it only use GICINT128 - GICINT134, and the offsets from 0 to 0x1000 are unused.
To save code size, introduce a new class attribute "reg_size" to set the
different register sizes for the INTC models in AST2700 and add a reg
Currently, the size of the "regs" array is 0x2000, which is too large. To save
code size and avoid mapping large unused gaps, will update it to only map the
useful set of registers. This update will support multiple sub-regions with
different sizes.
To address the redundant size issue, replace the
Added a new method "start_ast2700_test" to the "AST2x00MachineSDK" class and
this method centralizes the logic for starting the AST2700 test, making it
reusable for different test cases.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
tests/functional/test_aarch64_aspeed.py | 29
Added support for multiple output pins in the INTC controller to
accommodate the AST2700 A1.
Introduced "num_outpins" to represent the number of output pins. Updated the
IRQ handling logic to initialize and connect output pins separately from input
pins. Modified the "aspeed_soc_ast2700_realize" f
Updated Aspeed27x0SoCState to include an intc[2] array instead of a single
AspeedINTCState instance. Modified aspeed_soc_ast2700_get_irq and
aspeed_soc_ast2700_get_irq_index to correctly reference the corresponding
interrupt controller instance and OR gate index.
Currently, only GIC 192 to 201 are
The behavior of the INTC set IRQ is almost identical between INTC and INTCIO.
To reduce duplicated code, introduce the "aspeed_intc_set_irq_handler" function
to handle both INTC and INTCIO IRQ behavior. No functional change.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/intc/asp
This update introduces support for handling multi-output IRQs in the AST2700
interrupt controller (INTC), specifically for GICINT192_201. GICINT192_201 maps
1:10 to input IRQ 0 and output IRQs 0 to 9. Each status bit corresponds to a
specific IRQ.
Implemented "aspeed_intc_set_irq_handler_multi_out
Add AST2700 INTC design guidance and its block diagram.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
docs/specs/aspeed-intc.rst | 136 +
docs/specs/index.rst | 1 +
2 files changed, 137 insertions(+)
create mode 100644 docs/specs/aspeed
Introduce "aspeed_machine_ast2700a1_evb_class_init" to initialize the
AST2700 A1 EVB.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed.c | 24
1 file changed, 24 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 18f7c450da..82f4
The design of INTC controllers has significantly changed in AST2700 A1.
There are a total of 480 interrupt sources in AST2700 A1. For interrupt numbers
from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the
limitation of interrupt numbers of processors, the interrupts are merged e
Introduce a new ast2700 INTCIO class to support AST2700 INTCIO.
Added new register definitions for INTCIO, including enable and status
registers for IRQs GICINT192 through GICINT197.
Created a dedicated IRQ array for INTCIO, supporting six input pins and six
output pins, aligning with the newly def
Currently, these IRQ tables support from GIC 128 - 136 for AST2700 A0.
These IRQ tables can be reused for AST2700 A1 from GIC 192 - 197.
Updates the interrupt mapping to include support for AST2700 A1 by extending
the existing mappings to the new GIC range.
Signed-off-by: Jamin Lin
Reviewed-by: C
Currently, the size of the "regs" array is 0x2000, which is too large. So far,
it only uses "GICINT128 to `GICINT134", and the offsets from 0 to 0x1000 are
unused. To save code size and avoid mapping large unused gaps, update to only
map the useful set of registers:
INTC register [0x1000 – 0x1804]
According to the AST2700 datasheet, the INTC(CPU DIE) controller has 16KB
(0x4000) of register space, and the INTCIO (I/O DIE) controller has 1KB (0x400)
of register space.
Introduced a new class attribute "mem_size" to set different memory sizes for
the INTC models in AST2700.
Signed-off-by: Jam
The previous implementation set the "aspeed_intc_ops" struct, containing read
and write callbacks, to be used when I/O is performed on the INTC region.
Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used
for INTC (CPU Die).
To support the INTCIO (IO Die) model, introduces
On Fri, 7 Mar 2025 02:01:20 +0800
Tomita Moeko wrote:
> This patchset intends to decouple existing quirks from legacy mode.
> Currently all quirks depends on legacy mode (except x-igd-opregion),
> which includes following conditions:
> * Machine type is i440fx
> * IGD device is at guest BDF 00:0
Hi Cedric,
> Subject: Re: [PATCH v5 04/29] hw/intc/aspeed: Support setting different
> register size
>
> On 3/6/25 11:38, Jamin Lin wrote:
> > Currently, the size of the regs array is 0x2000, which is too large.
> > So far, it only use GICINT128 - GICINT134, and the offsets from 0 to 0x1000
> are
On 3/6/25 11:38, Jamin Lin wrote:
According to the AST2700 datasheet, the INTC(CPU DIE) controller has 16KB
(0x4000) of register space, and the INTCIO (I/O DIE) controller has 1KB (0x400)
of register space.
Introduced a new class attribute "mem_size" to set different memory sizes for
the INTC mo
On 3/5/2025 1:52 PM, Michael S. Tsirkin wrote:
On Tue, Mar 04, 2025 at 06:37:47PM +, Suravee Suthikulpanit wrote:
The QEMU-emulated AMD IOMMU PCI device is implemented based on the AMD I/O
Virtualization Technology (IOMMU) Specification [1]. The PCI id for this
device is platform-specific
On 3/6/2025 3:58 PM, Daniel P. Berrangé wrote:
On Thu, Mar 06, 2025 at 09:11:53AM +0200, Yan Vugenfirer wrote:
On Wed, Mar 5, 2025 at 8:54 AM Michael S. Tsirkin wrote:
On Tue, Mar 04, 2025 at 06:37:47PM +, Suravee Suthikulpanit wrote:
The QEMU-emulated AMD IOMMU PCI device is implement
For LoongArch th min tlb_ps is 12(4KB), for TLB code,
the tlb_ps may be 0,this may case UndefinedBehavior
Add a check-tlb_ps fuction to check tlb_ps,
to make sure the tlb_ps is avalablie. we check tlb_ps
when get the tlb_ps from tlb->misc or CSR bits.
1. cpu reset
set CSR_PWCL.PTBASE and CSR_STL
The following changes since commit e8a01102936286e012ed0f00bd7f3b7474d415c9:
Merge tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu into
staging (2025-03-05 21:58:23 +0800)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20250
some tlb instructions get the tlb_ps from tlb->misc but the
value may has been initialized to 0,just check the tlb_ps skip
the function and write a log.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-Id: <20250305063311.830674-2-gaos...@loongson.cn>
---
target/loongarch/tcg/tlb_helpe
On Thu, Mar 6, 2025 at 4:47 PM Deepak Gupta wrote:
>
> Commit f06bfe3dc38c ("target/riscv: implement zicfiss instructions") adds
> `ssamoswap` instruction. `ssamoswap` takes the code-point from existing
> reserved encoding (and not a zimop like other shadow stack instructions).
> If shadow stack i
Hi Cedric
> Subject: Re: [PATCH v5 03/29] hw/intc/aspeed: Introduce dynamic allocation
> for regs array
>
> On 3/6/25 11:38, Jamin Lin wrote:
> > Currently, the size of the "regs" array is 0x2000, which is too large.
> > To save code size and avoid mapping large unused gaps, will update it
> > to
On 3/6/25 15:41, Richard Henderson wrote:
diff --git a/page-vary-target.c b/page-vary-target.c
index 343b4adb95..1b4a9a10be 100644
--- a/page-vary-target.c
+++ b/page-vary-target.c
@@ -37,5 +37,7 @@ void finalize_target_page_bits(void)
{
#ifdef TARGET_PAGE_BITS_VARY
finalize_target_page
On Thu, Mar 6, 2025 at 4:47 PM Deepak Gupta wrote:
>
> Commit f06bfe3dc38c ("target/riscv: implement zicfiss instructions") adds
> `ssamoswap` instruction. `ssamoswap` takes the code-point from existing
> reserved encoding (and not a zimop like other shadow stack instructions).
> If shadow stack i
Extract the implicit MO_TE definition in order to replace
it by runtime variable in the next commit.
Mechanical change using:
$ for n in UW UL UQ UO SW SL SQ; do \
sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
$(git grep -l MO_TE$n target/microblaze); \
done
Signed-off-by: Philip
Signed-off-by: Pierrick Bouvier
---
hw/hyperv/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/hyperv/meson.build b/hw/hyperv/meson.build
index a9f2045a9af..5acd709bdd5 100644
--- a/hw/hyperv/meson.build
+++ b/hw/hyperv/meson.build
@@ -2,5 +2,5 @@ specific_ss.add
On Thu, Mar 6, 2025 at 11:00 PM Paolo Bonzini wrote:
>
> On 3/6/25 02:16, Alistair Francis wrote:
> > On Wed, Feb 19, 2025 at 3:01 AM Paolo Bonzini wrote:
> >>
> >> There is nothing that overwrites env->misa_mxl, so it is a constant. Do
> >
> > The idea is that misa_mxl can change, although that
On 3/6/25 08:39, Peter Maydell wrote:
In linux-user/arm/cpu_loop.c we define a full set of get/put
macros for both code and data (since the endianness handling
is different between the two). However the only one we actually
use is get_user_code_u32(). Remove the rest.
We leave a comment noting h
Re-use the TARGET_PAGE_BITS_VARY mechanism to define
TARGET_PAGE_SIZE and friends when not compiling per-target.
Inline qemu_target_page_{size,mask,bits} as they are now trivial.
Signed-off-by: Richard Henderson
---
After this, we could in fact remove qemu_target_page_foo(), etc.
We certainly do
On 3/5/25 11:18, Philippe Mathieu-Daudé wrote:
CPU_TLB_DYN_*_BITS definitions are only used by accel/tcg/cputlb.c
and accel/tcg/translate-all.c. Move them to accel/tcg/tb-internal.h.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tb-internal.h | 27 +++
include/e
On 3/6/25 08:39, Peter Maydell wrote:
The A32_BANKED_REG_{GET,SET} macros are only used inside target/arm;
move their definitions to cpregs.h. There's no need to have them
defined in all the code that includes cpu.h.
Signed-off-by: Peter Maydell
---
target/arm/cpregs.h | 28 +++
The functions arm_current_el() and arm_el_is_aa64() are used only in
target/arm and in hw/intc/arm_gicv3_cpuif.c. They're functions that
query internal state of the CPU. Move them out of cpu.h and into
internals.h.
This means we need to include internals.h in arm_gicv3_cpuif.c, but
this is justi
On 3/6/25 08:39, Peter Maydell wrote:
In the Arm ARM, rule R_TYTWB states that returning to AArch32
is an illegal exception return if:
* AArch32 is not supported at any exception level
* the target EL is configured for AArch64 via SCR_EL3.RW
or HCR_EL2.RW or via CPU state at reset
We che
Hi Maciej,
we are currently working toward building a single QEMU binary able to
emulate all architectures, and one prerequisite is to remove duplication
of compilation units (some are duplicated per target now, because of
compile time defines).
So the work here is to replace those compile t
On 3/6/25 08:39, Peter Maydell wrote:
When EL1 doesn't support AArch32, the HCR_EL2.RW bit is supposed to
be RAO/WI. We don't enforce this. This isn't a problem yet because
at the moment all of our CPU types with AArch64 support AArch32 at
all exception levels, but in the future this is likely
On 3/6/25 09:58, Philippe Mathieu-Daudé wrote:
On 6/3/25 17:23, Pierrick Bouvier wrote:
On 3/6/25 08:19, Richard Henderson wrote:
On 3/5/25 22:41, Pierrick Bouvier wrote:
Replace TARGET_PAGE.* by runtime calls
Signed-off-by: Pierrick Bouvier
---
hw/hyperv/syndbg.c | 7 ---
hw/h
On 3/6/25 08:39, Peter Maydell wrote:
+/* Return the effective value of SCR_EL3.RW */
+static inline bool arm_scr_rw_eff(CPUARMState *env)
+{
+/*
+ * SCR_EL3.RW has an effective value of 1 if:
+ * - we are NS and EL2 is implemented but doesn't support AArch32
+ * - we are S and
On Fri, 7 Mar 2025 02:01:27 +0800
Tomita Moeko wrote:
> So far, IGD-specific quirks all require enabling legacy mode, which is
> toggled by assigning IGD to 00:02.0. However, some quirks, like the BDSM
> and GGC register quirks, should be applied to all supported IGD devices.
> A new config opti
On 3/6/25 08:39, Peter Maydell wrote:
The functions arm_current_el() and arm_el_is_aa64() are used only in
target/arm and in hw/intc/arm_gicv3_cpuif.c. They're functions that
query internal state of the CPU. Move them out of cpu.h and into
internals.h.
This means we need to include internals.h
Em Wed, 5 Mar 2025 02:21:26 +0100
Philippe Mathieu-Daudé escreveu:
> From: Gavin Shan
>
> acpi_ghes_memory_errors() is the only caller, no need to expose
> the function. Besides, the last 'return' in this function isn't
> necessary and remove it.
>
> No functional changes intended.
Please re
On 3/6/25 08:39, Peter Maydell wrote:
The arm_cpu_data_is_big_endian() and related functions are now used
only in target/arm; they can be moved to internals.h.
The motivation here is that we would like to move arm_current_el()
to internals.h.
Signed-off-by: Peter Maydell
---
target/arm/cpu.h
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
On 3/6/25 08:39, Peter Maydell wrote:
We would like to move arm_el_is_aa64() to internals.h; however, it is
used by access_secure_reg(). Make that function not be inline, so
that it can stay in cpu.h.
access_secure_reg() is used only in two places:
* in hflags.c
* in the user-mode arm emula
On 3/6/25 08:39, Peter Maydell wrote:
At the top of linux-user/aarch64/cpu_loop.c we define a set of
macros for reading and writing data and code words, but we never
use these macros. Delete them.
Signed-off-by: Peter Maydell
---
linux-user/aarch64/cpu_loop.c | 48 -
On 2/28/25 21:25, Brian Cain wrote:
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/cpu_bits.h | 2 ++
target/hexagon/gen_tcg_funcs.py | 32 +++-
2 files changed, 21 insertions(+), 13 deletions(-)
diff --git a/target/hexagon/cpu_bits.h b/ta
Commit:8205bc1 ("target/riscv: introduce ssp and enabling controls for
zicfiss") introduced CSR_SSP but it mis-interpreted the spec on access
to CSR_SSP in M-mode. Gated to CSR_SSP is not gated via `xSSE`. But
rather rules clearly specified in section "22.2.1. Shadow Stack Pointer
(ssp) CSR access
Consider the CPU ENDI bit, swap instructions when the CPU
endianness doesn't match the binary one.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20241105130431.22564-17-phi...@linaro.org>
---
target/microblaze/cpu.h | 7 +++
target/microblaze/transl
On 3/6/25 07:28, BALATON Zoltan wrote:
On Thu, 6 Mar 2025, Daniel P. Berrangé wrote:
On Thu, Mar 06, 2025 at 02:45:52PM +0100, BALATON Zoltan wrote:
On Thu, 6 Mar 2025, Daniel P. Berrangé wrote:
On Thu, Mar 06, 2025 at 12:34:13PM +0100, Paolo Bonzini wrote:
Il gio 6 mar 2025, 10:27 Philippe M
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
From: "Maciej S. Szmigiero"
All callers to migration_incoming_state_destroy() other than
postcopy_ram_listen_thread() do this call with BQL held.
Since migration_incoming_state_destroy() ultimately calls "load_cleanup"
SaveVMHandlers and it will soon call BQL-sensitive code it makes sense
to alw
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
On 2025-03-05 17:06, Daniel P. Berrangé wrote:
On Mon, Feb 24, 2025 at 01:04:47PM +0100, Shalini Chellathurai Saroja
wrote:
Add Control-Program Identification (CPI) to the QEMU Object
Model (QOM). The CPI identifiers provide information about
the guest operating system. The CPI identifiers are:
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
On 6.03.2025 07:41, Pierrick Bouvier wrote:
Replace TARGET_PAGE.* by runtime calls.
Seems like this patch subject/title is not aligned
well with its content, or a least incomplete.
Also, could you provide more detailed information
why TARGET_PAGE_SIZE is getting replaced by
qemu_target_page_si
Commit 35c653c4029 ("tcg: Add 128-bit guest memory
primitives") introduced the use of bswap128() which is
declared in "qemu/int128.h", commit de95016dfbf ("accel/tcg:
Implement helper_{ld,st}*_mmu for user-only") introduced the
other bswap*() uses, which are declared in "qemu/bswap.h".
Include the
ping
On 9/1/25 13:54, Philippe Mathieu-Daudé wrote:
Hi Nick,
Ping? (series fully reviewed)
On 20/12/24 22:30, Philippe Mathieu-Daudé wrote:
Since v3:
- Addressed Nick & Harsh review comments
Remove the tswap() calls on ePAPR, and convert
them to big-endian LD/ST API on sPAPR.
On Thu, Mar 06, 2025 at 04:59:39PM +0100, Eric Auger wrote:
> >>> +++ b/include/system/host_iommu_device.h
> >>> @@ -22,10 +22,16 @@
> >>> *
> >>> * @hw_caps: host platform IOMMU capabilities (e.g. on IOMMUFD this
> >> represents
> >>> * the @out_capabilities value returned from IOM
From: Phil Dennis-Jordan
decode_bytes reads 1, 2, 4, or 8 bytes at a time. The destination
variable should therefore be a uint64_t, not a target_ulong.
Signed-off-by: Phil Dennis-Jordan
Fixes: ff2de1668c9 ("i386: hvf: remove addr_t")
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20241209203
When EL1 doesn't support AArch32, the HCR_EL2.RW bit is supposed to
be RAO/WI. We don't enforce this. This isn't a problem yet because
at the moment all of our CPU types with AArch64 support AArch32 at
all exception levels, but in the future this is likely to no longer
be true. Enforce the RAO/WI
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