Re: [PATCH 4/8] target/riscv: add helper to get CSR name

Hi Andrew, On Mon, Feb 17, 2025 at 10:01 PM Andrew Jones wrote: > > On Mon, Feb 17, 2025 at 04:17:24PM +0800, Yong-Xuan Wang wrote: > > Add a helper function to get CSR name from CSR number. > > > > Signed-off-by: Yong-Xuan Wang > > --- > > target/riscv/cpu.h | 6 +- > > 1 file changed, 5 i

Re: [PATCH 5/5] ui/console-vc: implement DCH (delete) and ICH (insert) commands

Hi On Sun, Feb 23, 2025 at 6:56 PM Roman Penyaev wrote: > > This patch implements DCH (delete character) and ICH (insert > character) commands. > > DCH - Delete Character: >"As characters are deleted, the remaining characters between the > cursor and right margin move to the left. Charact

Re: [PATCH 0/8] riscv: AIA: kernel-irqchip=off support

Hi Kashyap, On Tue, Feb 18, 2025 at 11:53 PM Kashyap Chamarthy wrote: > > On Mon, Feb 17, 2025 at 04:17:20PM +0800, Yong-Xuan Wang wrote: > > This series introduces the user-space AIA MSI emulation when using KVM > > acceleration. > > > > After this series, RISC-V QEMU virt machine with KVM accel

Re: [PATCH 3/5] hw/riscv: Make FDT optional for MPFS

On Mon, Feb 24, 2025 at 3:43 PM Sebastian Huber wrote: > > - Am 24. Feb 2025 um 6:22 schrieb Alistair Francis alistai...@gmail.com: > > > On Fri, Feb 14, 2025 at 4:27 PM Sebastian Huber > > wrote: > >> > >> Real-time kernels such as RTEMS or Zephyr may use a static device tree > >> built into

Re: [PATCH 3/5] hw/riscv: Make FDT optional for MPFS

- Am 24. Feb 2025 um 6:22 schrieb Alistair Francis alistai...@gmail.com: > On Fri, Feb 14, 2025 at 4:27 PM Sebastian Huber > wrote: >> >> Real-time kernels such as RTEMS or Zephyr may use a static device tree >> built into the kernel image. Do not require to use the -dtb option if >> -kernel

Re: [PATCH 3/5] hw/riscv: Make FDT optional for MPFS

On Fri, Feb 14, 2025 at 4:27 PM Sebastian Huber wrote: > > Real-time kernels such as RTEMS or Zephyr may use a static device tree > built into the kernel image. Do not require to use the -dtb option if > -kernel is used for the microchip-icicle-kit machine. That's a fair point, but it might also

Re: [PATCH 2/5] hw/riscv: More flexible FDT placement for MPFS

On Fri, Feb 14, 2025 at 4:26 PM Sebastian Huber wrote: > > If the kernel entry is in the high DRAM area, place the FDT into this > area. > > Signed-off-by: Sebastian Huber Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/microchip_pfsoc.c | 11 +-- > 1 file changed, 9 insertio

RE: [PATCH v3 21/28] hw/misc/aspeed_hace: Fix boot issue in the Crypto Manager Self Test

Hi Cedric, > Subject: Re: [PATCH v3 21/28] hw/misc/aspeed_hace: Fix boot issue in the > Crypto Manager Self Test > > On 2/21/25 06:43, Jamin Lin wrote: > > Hi Cedric, > > > >> Subject: Re: [PATCH v3 21/28] hw/misc/aspeed_hace: Fix boot issue in > >> the Crypto Manager Self Test > >> > >> On 2/13/

Re: [PATCH 0/5] Improve Microchip Polarfire SoC customization

On Fri, Feb 21, 2025 at 4:31 AM Conor Dooley wrote: > > +cc qemu-riscv, Alistar. > > On Fri, Feb 14, 2025 at 07:24:37AM +0100, Sebastian Huber wrote: > > Booting the microchip-icicle-kit machine using the latest PolarFire SoC > > Hart Software Services (HSS) no longer works since Qemu lacks suppor

Re: [RFC PATCH] hw/display: add blocklist for known bad drivers

On 2/21/25 19:01, Alex Bennée wrote: ... > diff --git a/stubs/host-gpu.c b/stubs/host-gpu.c > new file mode 100644 > index 00..7bf76ee4f6 > --- /dev/null > +++ b/stubs/host-gpu.c Looks okay Nit: host-gpu is a too generic name, IMO. Name should reflect Vulkan dedication, like host-vk-gpu.c

[PATCH] target/riscv/kvm: Add some exts support

From: Quan Zhou When the Sscofpmf/Svade/Svadu/Smnpm/Ssnpm exts is available expose it to the guest so that guest can use it. Signed-off-by: Quan Zhou --- target/riscv/kvm/kvm-cpu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c

Re: [PULL 15/50] hw/char: sifive_uart: Print uart characters async

On Sat, Feb 22, 2025 at 1:27 AM Clément Chigot wrote: > > On Fri, Feb 14, 2025 at 1:52 PM Clément Chigot wrote: > > > > Hi Alistair, > > > > I've an issue following this patch. When the system is reset (e.g > > using HTIF syscalls), the fifo might not be empty and thus some > > characters are los

Re: [PATCH] linux-user/riscv: Disable unsupported SA_RESTORER

On Mon, Feb 3, 2025 at 8:58 AM Thomas Weißschuh wrote: > > Linux on riscv does not support SA_RESTORER. > Currently QEMU thinks there is a field 'sa_restorer' in the middle of > 'struct sigaction' which does not actually exist. > This leads to corrupted data and out-of-bounds accesses. > > Signed-

Re: Perf in QEMU

On Tue, Feb 18, 2025 at 11:56 PM 蓝色的梦想 <1058183...@qq.com> wrote: > > Hello! > > I am a graduate student currently studying in school. Recently, I used > QEMU 9.0.2 to create virtual machines with ARM, x86, and RISC-V architectures > for experiments. During the process, I found that the ‘perf

Re: [PATCH for-10.0 00/11] riscv: IOMMU HPM support

On Thu, Dec 5, 2024 at 11:33 PM Daniel Henrique Barboza wrote: > > Hi, > > This is a re-submission of the original Hardware Performance Monitor > IOMMU support sent by Tomasz back in July 2023 [1] in the first version > of the IOMMU emulation. In the second version of that work [2] sent in > Febru

[PATCH v2 4/8] target/loongarch: Add paravirt ipi feature detection

Paravirt ipi feature is OnOffAuto type, feature detection is added to check whether it is supported by KVM host. Signed-off-by: Bibo Mao --- target/loongarch/cpu.h | 2 ++ target/loongarch/kvm/kvm.c | 36 +++- 2 files changed, 37 insertions(+), 1 deletion(-)

[PATCH v2 8/8] target/loongarch: Add virtual extioi feature enabling

Feature virtual extioi is loongArch virt machine property rather than vCPU property in qemu side. However it is vCPU property in KVM kernel side, here add loongArch virt machine property checking and enable virt extioi feature when vCPU is created. Signed-off-by: Bibo Mao --- hw/loongarch/virt.c

Re: [PATCH qemu v2] target/riscv: Check ext_zca for misaligned return address of mret/sret.

On Mon, Feb 3, 2025 at 3:34 PM ~yuming wrote: > > From: Yu-Ming Chang > > We only check RVC to allow 16-bit aligned return addreses. This will > cause issues when only ext_zca is enabled without RVC: 16-bit > instructions are allowed, but 16-bit aligned return address are not. > We should also ch

[PATCH 06/10] docs/qapidoc: remove example section support

Since commit 3c5f6114 (qapi: remove "Example" doc section), Example sections no longer exist, so this support in qapidoc is now dead code. Signed-off-by: John Snow --- docs/sphinx/qapidoc.py | 9 + 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/docs/sphinx/qapidoc.py b/docs

[PATCH 08/10] qapi/schema: add __repr__ to QAPIDoc.Section

Makes debugging far more pleasant when you can just print(section) and get something reasonable to display. Signed-off-by: John Snow --- scripts/qapi/parser.py | 9 + 1 file changed, 9 insertions(+) diff --git a/scripts/qapi/parser.py b/scripts/qapi/parser.py index c3004aa70c6..617711b1

Re: [PATCH] linux-user/riscv: Disable unsupported SA_RESTORER

On Mon, Feb 3, 2025 at 8:58 AM Thomas Weißschuh wrote: > > Linux on riscv does not support SA_RESTORER. > Currently QEMU thinks there is a field 'sa_restorer' in the middle of > 'struct sigaction' which does not actually exist. > This leads to corrupted data and out-of-bounds accesses. > > Signed-

Re: [PATCH for-10.0 10/11] hw/riscv: add IOMMU HPM trace events

On Thu, Dec 5, 2024 at 11:34 PM Daniel Henrique Barboza wrote: > > Add a handful of trace events to allow for an easier time debugging the > HPM feature. > > Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Alistair > --- > hw/riscv/riscv-iommu-hpm.c | 10 ++ > hw/ri

[PATCH 07/10] qapi: expand tags to all doc sections

This patch adds an explicit section "kind" to all QAPIDoc sections. Members/Features are now explicitly marked as such, with the name now being stored in a dedicated "name" field (which qapidoc.py was not actually using anyway.) The qapi-schema tests are updated to account for the new section name

[PATCH 02/10] python: add qapi static analysis tests

Update the python tests to also check qapi. No idea why I didn't do this before. I guess I was counting on moving it under python/ and then just forgot after that was NACKed. Oops, this turns out to be really easy. flake8, isort and mypy use the tool configuration from the existing python director

[PATCH 00/10] qapi: misc testing and doc patches

GitLab: https://gitlab.com/jsnow/qemu/-/pipelines/1684045409 This is a series of random qapi and documentation patches; Patches 1-3: Formalize QAPI python testing (finally ...) Patches 4-10: Miscellaneous patches and fixes related to the documentation overhaul project; but were standalone enough

[PATCH 10/10] docs: disambiguate cross-references

These references are not in and of themselves problems at the moment, however, the forthcoming qapidoc conversion series will begin adding cross-reference targets that conflict with these existing targets. As a result, cross-references such as "migration", "qom", "replay" will become ambiguous. Mo

[PATCH 09/10] qapi/source: allow multi-line QAPISourceInfo advancing

This is for the sake of the new rST generator (the "transmogrifier") so we can advance multiple lines on occasion while keeping the generated<-->source mappings accurate. next_line now simply takes an optional n parameter which chooses the number of lines to advance. This is used mainly when conv

[PATCH 05/10] qapi/parser: adjust info location for doc body section

Instead of using the info object for the doc block as a whole (which always points to the very first line of the block), update the info pointer for each call to ensure_untagged_section when the existing section is otherwise empty. This way, Sphinx error information will match precisely to where th

[PATCH 03/10] qapi: delete un-needed python static analysis configs

The pylint config is being left in place because the settings differ enough from the python/ directory settings that we need a chit-chat on how to merge them O:-) Everything else can go. Signed-off-by: John Snow --- scripts/qapi/.flake8| 3 --- scripts/qapi/.isort.cfg | 7 --- scripts/q

[PATCH 04/10] docs/qapidoc: support header-less freeform sections

The code as written crashes when a free-form documentation block doesn't start with a heading or subheading, for example: | ## | # Just text, no heading. | ## The code will attempt to use the `node` variable uninitialized. To fix, create a generic block to insert the doc text into. (This patch a

[PATCH 01/10] qapi: update pylintrc config

If you've got a newer pylint, it'll whine about positional arguments separately from the regular ones. Update the configuration to ignore both categories of warning. Signed-off-by: John Snow --- scripts/qapi/pylintrc | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/qapi/pylintrc b/scr

Re: [PATCH for-10.0 11/11] docs/specs/riscv-iommu.rst: add HPM support info

On Thu, Dec 5, 2024 at 11:33 PM Daniel Henrique Barboza wrote: > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > docs/specs/riscv-iommu.rst | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/docs/specs/riscv-iommu.rst b/docs/specs/riscv-iommu.r

Re: [PATCH for-10.0 09/11] hw/riscv/riscv-iommu.c: add RISCV_IOMMU_CAP_HPM cap

On Thu, Dec 5, 2024 at 11:34 PM Daniel Henrique Barboza wrote: > > From: Tomasz Jeznach > > Now that we have every piece in place we can advertise CAP_HTM to > software, allowing any HPM aware driver to make use of the counters. > > HPM is enabled/disabled via the 'hpm-counters' attribute. Defaul

Re: [PATCH for-10.0 08/11] hw/riscv/riscv-iommu: add hpm events mmio write

On Thu, Dec 5, 2024 at 11:34 PM Daniel Henrique Barboza wrote: > > From: Tomasz Jeznach > > To support hpm events mmio writes, done via > riscv_iommu_process_hpmevt_write(), we're also adding the 'hpm-counters' > IOMMU property that are used to determine the amount of counters > available in the

[PATCH v2 2/8] target/loongarch: Mov kvm specified vcpu property to kvm directory

LBT and PMU feature is supported only in kvm mode, move property about these two features to function kvm_loongarch_cpu_post_init(). Signed-off-by: Bibo Mao --- target/loongarch/cpu.c | 40 ++ target/loongarch/kvm/kvm.c | 35 +++

[PATCH v2 3/8] target/loongarch: Add CPU property for paravirt ipi feature

Property kvm-pv-ipi is added to paravirt ipi feature, it is specially for kvm mode. Signed-off-by: Bibo Mao --- target/loongarch/cpu.h| 1 + target/loongarch/kvm/kvm.c| 18 ++ target/loongarch/loongarch-qmp-cmds.c | 2 +- 3 files changed, 20 insertio

[PATCH v2 7/8] target/loongarch: Add kvm steal time feature detection

Paravirt steal time feature is OnOffAuto type, feature detection is added to check whether it is supported on KVM host. Signed-off-by: Bibo Mao --- target/loongarch/cpu.h | 1 + target/loongarch/kvm/kvm.c | 20 2 files changed, 21 insertions(+) diff --git a/target/loon

[PATCH v2 1/8] target/loongarch: Add post init function for kvm mode

Some features such as LBT and PMU are implemented in kvm mode, With para-virt features in future, post init function is added for kvm mode, so that property for these features will be created in kvm post init function. Signed-off-by: Bibo Mao --- target/loongarch/cpu.c | 2 +- target/loongar

[PATCH v2 0/8] target/loongarch: Add paravirt feature support

Paravirt features is enabled by default if it is supported by KVM host, such as KVM_FEATURE_IPI and KVM_FEATURE_STEAL_TIME, however paravirt feature KVM_FEATURE_VIRT_EXTIOI is controlled from qemu VMM rather KVM host. >From qemu VMM side, all paravirt features should be controlled. Here property o

[PATCH v2 6/8] target/loongarch: Add CPU property for kvm steal time feature

Property kvm-steal-time is added for kvm steal time feature, it is specially for kvm mode. Signed-off-by: Bibo Mao --- target/loongarch/cpu.h| 1 + target/loongarch/kvm/kvm.c| 18 ++ target/loongarch/loongarch-qmp-cmds.c | 2 +- 3 files changed, 20 i

[PATCH v2 5/8] target/loongarch: Add paravirt ipi feature enabling

The similiar with cpucfg register, paravirt ipi feature is set in function kvm_arch_put_registers(). Instead the paravirt feature can be enabled only once, it cannot be changed dynamically. Signed-off-by: Bibo Mao --- target/loongarch/kvm/kvm.c | 36 1 file c

Re: [PATCH for-10.0 07/11] hw/riscv/riscv-iommu: add IOHPMCYCLES mmio write

On Thu, Dec 5, 2024 at 11:34 PM Daniel Henrique Barboza wrote: > > From: Tomasz Jeznach > > RISCV_IOMMU_REG_IOHPMCYCLES writes are done by > riscv_iommu_process_hpmcycle_write(), called by the mmio write callback > via riscv_iommu_process_hpm_writes(). > > Signed-off-by: Tomasz Jeznach > Signed-

Re: [PATCH for-10.0 06/11] hw/riscv/riscv-iommu: add IOCOUNTINH mmio writes

On Thu, Dec 5, 2024 at 11:35 PM Daniel Henrique Barboza wrote: > > From: Tomasz Jeznach > > RISCV_IOMMU_REG_IOCOUNTINH is done by riscv_iommu_process_iocntinh_cy(), > which is called during riscv_iommu_mmio_write() callback via a new > riscv_iommu_pricess_hpm_writes() helper. > > Signed-off-by: T

[PATCH v2 2/3] hw/intc/aplic: refine the APLIC realize

When the APLIC is emulated in the kernel, the GPIO output lines to CPUs can be remove. In this case the APLIC trigger CPU interrupts by KVM APIs. This patch also move the code that claim the CPU interrupts to the beginning of APLIC realization. This can avoid the unnecessary resource allocation be

[PATCH v2 3/3] hw/intc/aplic: refine kvm_msicfgaddr

Let kvm_msicfgaddr use the same format with mmsicfgaddr and smsicfgaddr. Signed-off-by: Yong-Xuan Wang --- hw/intc/riscv_aplic.c | 24 +--- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index e5714267c096..5964cd

[PATCH v2 1/3] hw/intc/imsic: refine the IMSIC realize

When the IMSIC is emulated in the kernel, the GPIO output lines to CPUs and aia_ireg_rmw_fn setting can be remove. In this case the IMSIC trigger CPU interrupts by KVM APIs, and the RMW of IREG is handled in kernel. This patch also move the code that claim the CPU interrupts to the beginning of IM

[PATCH v2 0/3] riscv: AIA: refinement for KVM acceleration

Reorder the code to reduce the conditional checking and remove unnecessary resource setting when using in-kernl AIA irqchip. --- v2: - remove the code reordering of the riscv-virt machine since it can't work with NUMA setting. (Daniel) Yong-Xuan Wang (3): hw/intc/imsic: refine the IMSIC reali

Re: [PATCH for-10.0 05/11] hw/riscv/riscv-iommu: instantiate hpm_timer

On Thu, Dec 5, 2024 at 11:35 PM Daniel Henrique Barboza wrote: > > From: Tomasz Jeznach > > The next HPM related changes requires the HPM overflow timer to be > initialized by the riscv-iommu base emulation. > > Signed-off-by: Tomasz Jeznach > Signed-off-by: Daniel Henrique Barboza Acked-by: A

Re: [PATCH for-10.0 04/11] hw/riscv/riscv-iommu: add riscv_iommu_hpm_incr_ctr()

On Thu, Dec 5, 2024 at 11:33 PM Daniel Henrique Barboza wrote: > > From: Tomasz Jeznach > > This function will increment a specific counter, generating an interrupt > when an overflow occurs. > > Some extra changes in riscv-iommu.c were required to add this new > helper in riscv-iommu-hpm.c: > >

Re: [PATCH for-10.0 03/11] hw/riscv/riscv-iommu: add riscv-iommu-hpm file

On Thu, Dec 5, 2024 at 11:35 PM Daniel Henrique Barboza wrote: > > From: Tomasz Jeznach > > The HPM (Hardware Performance Monitor) support consists of almost 7 > hundred lines that would be put on top of the base riscv-iommu > emulation. > > To avoid clogging riscv-iommu.c, add a separated riscv-

Re: [PATCH for-10.0 02/11] hw/riscv/riscv-iommu-bits.h: HPM bits

On Thu, Dec 5, 2024 at 11:33 PM Daniel Henrique Barboza wrote: > > From: Tomasz Jeznach > > Add the relevant HPM (High Performance Monitor) bits that we'll be using > in the next patches. > > Signed-off-by: Tomasz Jeznach > Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Al

Re: [PATCH for-10.0 01/11] hw/riscv/riscv-iommu.h: add missing headers

On Thu, Dec 5, 2024 at 11:32 PM Daniel Henrique Barboza wrote: > > This header is incomplete, i.e. it is using definitions that are being > supplied by the .c files that are including it. > > Adding this header into a fresh .c file will result in errors: > > /home/danielhb/work/qemu/hw/riscv/riscv

Re: [PATCH 1/3] target/riscv/cpu: ignore TCG init for KVM CPUs in reset_hold

On Fri, Feb 21, 2025 at 2:14 AM Daniel Henrique Barboza wrote: > > riscv_cpu_reset_hold() does a lot of TCG-related initializations that > aren't relevant for KVM, but nevertheless are impacting the reset state > of KVM vcpus. > > When running a KVM guest, kvm_riscv_reset_vcpu() is called at the e

Re: [PATCH v2] vdpa: Allow vDPA to work on big-endian machine

On Sat, Feb 22, 2025 at 3:08 AM Konstantin Shkolnyy wrote: > > Add .set_vnet_le() function that always returns success, assuming that > vDPA h/w always implements LE data format. Otherwise, QEMU disables vDPA and > outputs the message: > "backend does not support LE vnet headers; falling back on u

RE: [PATCH 4/5] pcie, virtio: Remove redundant pm_cap

Hi Cédric, >-Original Message- >From: Cédric Le Goater >Subject: Re: [PATCH 4/5] pcie, virtio: Remove redundant pm_cap > >Hello Zhenzhong, > >On 2/21/25 07:12, Duan, Zhenzhong wrote: >> >> >>> -Original Message- >>> From: Alex Williamson >>> Subject: [PATCH 4/5] pcie, virtio: Rem

RE: [PATCH 0/5] PCI: Implement basic PCI PM capability backing

>-Original Message- >From: Alex Williamson >Subject: [PATCH 0/5] PCI: Implement basic PCI PM capability backing > >Eric recently identified an issue[1] where during graceful shutdown >of a VM in a vIOMMU configuration, the guest driver places the device >into the D3 power state, the vIOM

Re: [PATCH v2 2/3] binfmt: Normalize host CPU architecture

On Tue, Jan 28, 2025 at 4:29 AM Andrea Bolognani wrote: > > Right now information regarding the family each CPU type belongs > to is recorded in two places: the large data table at the top of > the script, and the qemu_host_family() function. > > We can make things better by mapping host CPU archi

Re: [PATCH v2 1/3] binfmt: Shuffle things around

On Tue, Jan 28, 2025 at 4:29 AM Andrea Bolognani wrote: > > This should make no difference from the functional point of > view and it's just preparation for upcoming changes. > > Signed-off-by: Andrea Bolognani Reviewed-by: Alistair Francis Alistair > --- > scripts/qemu-binfmt-conf.sh | 17 +

Re: [PATCH v2 0/3] target/riscv/kvm: update to Linux 6.14-rc3

On Sat, Feb 22, 2025 at 12:19 AM Daniel Henrique Barboza wrote: > > Hi, > > In this version all changes were made in patch 2. In the first posting I > forgot to update how riscv,isa was going to be calculated when > ext_ziccrse is set by KVM. > > A change was made in isa_edata_arr[] to use ext_zic

Re: [PATCH v2 5/9] hw/char/bcm2835_aux: Really use RX FIFO depth

On 2/20/25 01:28, Philippe Mathieu-Daudé wrote: While we model a 8-elements RX FIFO since the BCM2835 AUX model was introduced in commit 97398d900ca ("bcm2835_aux: add emulation of BCM2835 AUX block") we only read 1 char at a time! Have the IOCanReadHandler handler return how many elements are a

Re: [PATCH v2 9/9] hw/char/sh_serial: Return correct number of empty RX FIFO elements

On 2/20/25 01:29, Philippe Mathieu-Daudé wrote: In the IOCanReadHandler sh_serial_can_receive(), if the Serial Control Register 'Receive Enable' bit is set (bit 4), then we return a size of (1 << 4) which happens to be equal to 16, so effectively SH_RX_FIFO_LENGTH. The IOReadHandler, sh_serial_r

Re: [PATCH v2 8/9] hw/char/mcf_uart: Really use RX FIFO depth

On 2/20/25 01:29, Philippe Mathieu-Daudé wrote: While we model a 4-elements RX FIFO since the MCF UART model was introduced in commit 20dcee94833 ("MCF5208 emulation"), we only read 1 char at a time! Have the IOCanReadHandler handler return how many elements are available, and use that in the IO

Re: [PATCH v2 7/9] hw/char/mcf_uart: Use FIFO_DEPTH definition instead of magic values

On 2/20/25 01:29, Philippe Mathieu-Daudé wrote: Defines FIFO_DEPTH and use it, fixing coding style. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel --- hw/char/mcf_uart.c | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH v2 6/9] hw/char/imx_serial: Really use RX FIFO depth

On 2/20/25 01:28, Philippe Mathieu-Daudé wrote: While we model a 32-elements RX FIFO since the IMX serial model was introduced in commit 988f2442971 ("hw/char/imx_serial: Implement receive FIFO and ageing timer") we only read 1 char at a time! Have the IOCanReadHandler handler return how many el

Re: [PATCH v2 4/9] hw/char/pl011: Really use RX FIFO depth

On 2/20/25 01:28, Philippe Mathieu-Daudé wrote: While we model a 16-elements RX FIFO since the PL011 model was introduced in commit cdbdb648b7c ("ARM Versatile Platform Baseboard emulation"), we only read 1 char at a time! Have the IOCanReadHandler handler return how many elements are available,

Re: [PATCH v2 3/9] hw/char/pl011: Improve RX flow tracing events

On 2/20/25 01:28, Philippe Mathieu-Daudé wrote: Log FIFO use (availability and depth). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Luc Michel --- hw/char/pl011.c | 10 ++ hw/char/trace-events | 7 --- 2 files changed, 10 insertions(+), 7 d

Re: [PATCH v2 2/9] hw/char/pl011: Simplify a bit pl011_can_receive()

On 2/20/25 01:28, Philippe Mathieu-Daudé wrote: Introduce 'fifo_depth' and 'fifo_available' local variables to better express the 'r' variable use. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel --- hw/char/pl011.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)

Seeking help on implementing sync over ivshmem shared memory

Hi Team , Seeking help on implementing sync over ivshmem shared memory , As part of internal project we could able to achieve shared ivshmem with doorbell mechanism ,But in order to achieve shared memory synchronisation we are trying to add atomic operation over this shared memory area variables

[PATCH 4/5] ui/console-vc: add support for cursor DECSC and DECRC commands

There are aliases for save and restore cursor commands: * save cursor `ESC 7` (DEC Save Cursor [1], older VT100) `ESC [ s` (CSI Save Cursor, standard ANSI) * load cursor `ESC 8` (DEC Restore Cursor [2], older VT100) `ESC [ u` (CSI Restore Cursor, standard ANSI) This c

[PATCH 2/5] ui/console-vc: report to the application instead of screen rendering

Terminal Device Status Report (DSR) [1] should be sent to an application, not rendered to the screen. This patch fixes rendering of terminal report, which appears only on the graphical screen of the terminal (console "vc") and can be reproduced by the following command: echo -en '\e[6n'; IFS=

[PATCH 5/5] ui/console-vc: implement DCH (delete) and ICH (insert) commands

This patch implements DCH (delete character) and ICH (insert character) commands. DCH - Delete Character: "As characters are deleted, the remaining characters between the cursor and right margin move to the left. Character attributes move with the characters. The terminal adds blank spa

[PATCH 1/5] ui/console-vc: introduce parsing of the 'ESC ( ' sequence

This change introduces parsing of the 'ESC ( ' sequence, which is supposed to change character set [1]. In the QEMU case, the introduced parsing logic does not actually change the character set, but simply parses the sequence and does not let output of a tool to be corrupted with leftovers: `top` s

[PATCH 0/5] ui/console-vc: various fixes and improvements

This patch series brings several fixes and improvements to the QEMU virtual console (VC), making it more usable and aligning it better with VT100 spec. The updates include support for inserting and deleting characters, better cursor handling and correct position reporting. Without these changes, th

[PATCH 3/5] ui/console-vc: report cursor position in the screen not in the scroll buffer

The format of the CSI cursor position report is `ESC[row;columnR`, where `row` is a row of a cursor in the screen, not in the scrollback buffer. What's the difference? Let's say the terminal screen has 24 lines, no matter how long the scrollback buffer may be, the last line is the 24th. For exampl

Re: [PATCH v2 04/18] hw/arm: Add i.MX 8M Plus EVK board

Am 10. Februar 2025 17:30:01 UTC schrieb Peter Maydell : >On Tue, 4 Feb 2025 at 09:21, Bernhard Beschow wrote: >> >> As a first step, implement the bare minimum: CPUs, RAM, interrupt controller, >> serial. All other devices of the A53 memory map are represented as >> TYPE_UNIMPLEMENTED_DEVICE,

[PATCH v2 07/18] hw/arm/fsl-imx8mp: Add USDHC storage controllers

The USDHC emulation allows for running real-world images such as those generated by Buildroot. Convert the board documentation accordingly instead of running a Linux kernel with ephemeral storage. Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow --- docs/system/arm/imx8mp-evk.rst | 18

[PATCH v2 11/18] hw/arm/fsl-imx8mp: Add SPI controllers

Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow --- docs/system/arm/imx8mp-evk.rst | 1 + include/hw/arm/fsl-imx8mp.h| 8 hw/arm/fsl-imx8mp.c| 26 ++ 3 files changed, 35 insertions(+) diff --git a/docs/system/arm/imx8mp-evk.rst b/doc

[PATCH v2 15/18] hw/arm/fsl-imx8mp: Add USB support

Split the USB MMIO regions to better keep track of the implemented vs. unimplemented regions. Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow --- docs/system/arm/imx8mp-evk.rst | 1 + include/hw/arm/fsl-imx8mp.h| 12 +++ hw/arm/fsl-imx8mp.c| 37 ++

[PATCH v2 09/18] hw/arm/fsl-imx8mp: Add GPIO controllers

Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow --- docs/system/arm/imx8mp-evk.rst | 1 + include/hw/arm/fsl-imx8mp.h| 14 + hw/arm/fsl-imx8mp.c| 55 ++ 3 files changed, 70 insertions(+) diff --git a/docs/system/arm/imx8mp-evk.

[PATCH v2 13/18] hw/arm/fsl-imx8mp: Implement general purpose timers

Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow --- docs/system/arm/imx8mp-evk.rst | 1 + include/hw/arm/fsl-imx8mp.h| 11 +++ include/hw/timer/imx_gpt.h | 1 + hw/arm/fsl-imx8mp.c| 53 ++ hw/timer/imx_gpt.c | 25 ++

[PATCH v2 14/18] hw/arm/fsl-imx8mp: Add Ethernet controller

The i.MX 8M Plus SoC actually has two ethernet controllers, the usual ENET one and a Designware one. There is no device model for the latter, so only add the ENET one. Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow --- docs/system/arm/imx8mp-evk.rst | 1 + include/hw/arm/fsl-imx8mp

[PATCH v2 04/18] hw/arm: Add i.MX 8M Plus EVK board

As a first step, implement the bare minimum: CPUs, RAM, interrupt controller, serial. All other devices of the A53 memory map are represented as TYPE_UNIMPLEMENTED_DEVICE, i.e. the whole memory map is provided. This allows for running Linux without it crashing due to invalid memory accesses. Signe

[PATCH v2 02/18] hw/pci-host/designware: Prevent device attachment on internal PCIe root bus

On the real device, the PCIe root bus is only connected to a PCIe bridge and does not allow for direct attachment of devices. Doing so in QEMU results in no PCI devices being detected by Linux. Instead, PCI devices should plug into the secondary PCIe bus spawned by the internal PCIe bridge. Unfort

[PATCH v2 17/18] hw/arm/fsl-imx8mp: Add on-chip RAM

Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow --- include/hw/arm/fsl-imx8mp.h | 1 + hw/arm/fsl-imx8mp.c | 11 +++ 2 files changed, 12 insertions(+) diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h index 4dbe30f524..03f057c7db 100644 --- a/inc

[PATCH v2 18/18] hw/rtc: Add Ricoh RS5C372 RTC emulation

The implementation just allows Linux to determine date and time. Signed-off-by: Bernhard Beschow --- MAINTAINERS| 2 + hw/rtc/rs5c372.c | 236 + tests/qtest/rs5c372-test.c | 43 +++ hw/rtc/Kconfig | 5 + hw/rtc/me

[PATCH v2 03/18] hw/gpio/pca955*: Move Kconfig switches next to implementations

The move of the Kconfig bits to hw/gpio is fixing a bug in 6328d8ffa6cb9d ("misc/pca955*: Move models under hw/gpio"), which moved the code but forgot to move the Kconfig sections. Fixes: 6328d8ffa6cb9d "misc/pca955*: Move models under hw/gpio" Signed-off-by: Bernhard Beschow --- hw/gpio/Kconfig

[PATCH v2 08/18] hw/arm/fsl-imx8mp: Add PCIe support

Linux checks for the PLLs in the PHY to be locked, so implement a model emulating that. Signed-off-by: Bernhard Beschow --- MAINTAINERS | 2 + docs/system/arm/imx8mp-evk.rst | 1 + include/hw/arm/fsl-imx8mp.h | 10 +++ include/hw/pci-host/fsl_imx8m_phy.h |

[PATCH v2 00/18] Add i.MX 8M Plus EVK machine

This series adds a new aarch64 machine to QEMU: i.MX 8M Plus EVK [1]. It allows for running Linux distributions such as Buildroot (freescale_imx8mpevk_defconfig) and Arch Linux [2] via direct kernel boot. U-Boot does not work yet. I plan to use this machine in CI and I also want to make it availabl

[PATCH v2 06/18] hw/arm/fsl-imx8mp: Add SNVS

SNVS contains an RTC which allows Linux to deal correctly with time. This is particularly useful when handling persistent storage which will be done in the next patch. Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow --- docs/system/arm/imx8mp-evk.rst | 1 + include/hw/arm/fsl-imx8mp

[PATCH v2 12/18] hw/arm/fsl-imx8mp: Add watchdog support

Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow --- docs/system/arm/imx8mp-evk.rst | 1 + include/hw/arm/fsl-imx8mp.h| 7 +++ hw/arm/fsl-imx8mp.c| 28 hw/arm/Kconfig | 1 + 4 files changed, 37 insertions(+) diff --gi

[PATCH v2 10/18] hw/arm/fsl-imx8mp: Add I2C controllers

Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow --- docs/system/arm/imx8mp-evk.rst | 1 + include/hw/arm/fsl-imx8mp.h| 11 +++ hw/arm/fsl-imx8mp.c| 29 + hw/arm/Kconfig | 2 ++ 4 files changed, 43 insertions(+) dif

[PATCH v2 16/18] hw/arm/fsl-imx8mp: Add boot ROM

On a real device, the boot ROM contains the very first instructions the CPU executes. Also, U-Boot calls into the ROM to determine the boot device. While we're not actually implementing this here, let's create the infrastructure and add a dummy ROM with all zeros. This allows for implementing a ROM

[PATCH v2 05/18] hw/arm/fsl-imx8mp: Implement clock tree

Fixes quite a few stack traces during the Linux boot process. Also provides the clocks for devices added later, e.g. enet1. Signed-off-by: Bernhard Beschow --- MAINTAINERS | 2 + docs/system/arm/imx8mp-evk.rst | 1 + include/hw/arm/fsl-imx8mp.h | 4 + include/hw/mi

[PATCH v2 01/18] hw/usb/hcd-dwc3: Align global registers size with Linux

While at it add missing GUSB2RHBCTL register as found in i.MX 8M Plus reference manual. Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow --- include/hw/usb/hcd-dwc3.h | 2 +- hw/usb/hcd-dwc3.c | 5 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/include/hw/

Re: [PATCH v2 16/18] hw/arm/fsl-imx8mp: Add boot ROM

Am 17. Februar 2025 22:48:23 UTC schrieb Bernhard Beschow : > > >Am 17. Februar 2025 13:28:42 UTC schrieb Peter Maydell >: >>On Tue, 4 Feb 2025 at 09:21, Bernhard Beschow wrote: >>> >>> On a real device, the boot ROM contains the very first instructions the CPU >>> executes. Also, U-Boot calls

Re: [PATCH v2 18/18] hw/rtc: Add Ricoh RS5C372 RTC emulation

Am 10. Februar 2025 22:48:24 UTC schrieb Bernhard Beschow : > > >Am 10. Februar 2025 14:26:00 UTC schrieb "Philippe Mathieu-Daudé" >: >>On 6/2/25 22:58, Bernhard Beschow wrote: >>> >>> >>> Am 6. Februar 2025 17:32:31 UTC schrieb Peter Maydell >>> : On Tue, 4 Feb 2025 at 09:21, Bernhard