On Thu, Dec 5, 2024 at 11:33 PM Daniel Henrique Barboza <dbarb...@ventanamicro.com> wrote: > > Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > docs/specs/riscv-iommu.rst | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/docs/specs/riscv-iommu.rst b/docs/specs/riscv-iommu.rst > index b1538c9ead..000c7e1f57 100644 > --- a/docs/specs/riscv-iommu.rst > +++ b/docs/specs/riscv-iommu.rst > @@ -82,6 +82,8 @@ Several options are available to control the capabilities > of the device, namely: > - "off" (Out-of-reset translation mode: 'on' for DMA disabled, 'off' for > 'BARE' (passthrough)) > - "s-stage": enable s-stage support > - "g-stage": enable g-stage support > +- "hpm-counters": number of hardware performance counters available. Maximum > value is 31. > + Default value is 31. Use 0 (zero) to disable HPM support > > riscv-iommu-sys device > ---------------------- > -- > 2.47.1 > >
