On Thu, Dec 5, 2024 at 11:34 PM Daniel Henrique Barboza
<dbarb...@ventanamicro.com> wrote:
>
> Add a handful of trace events to allow for an easier time debugging the
> HPM feature.
>
> Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Acked-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> hw/riscv/riscv-iommu-hpm.c | 10 ++++++++++
> hw/riscv/trace-events | 5 +++++
> 2 files changed, 15 insertions(+)
>
> diff --git a/hw/riscv/riscv-iommu-hpm.c b/hw/riscv/riscv-iommu-hpm.c
> index 5518c287a5..c5034bff79 100644
> --- a/hw/riscv/riscv-iommu-hpm.c
> +++ b/hw/riscv/riscv-iommu-hpm.c
> @@ -39,6 +39,8 @@ uint64_t riscv_iommu_hpmcycle_read(RISCVIOMMUState *s)
> const uint64_t ctr_prev = s->hpmcycle_prev;
> const uint64_t ctr_val = s->hpmcycle_val;
>
> + trace_riscv_iommu_hpm_read(cycle, inhibit, ctr_prev, ctr_val);
> +
> if (get_field(inhibit, RISCV_IOMMU_IOCOUNTINH_CY)) {
> /*
> * Counter should not increment if inhibit bit is set. We can't
> really
> @@ -61,6 +63,8 @@ static void hpm_incr_ctr(RISCVIOMMUState *s, uint32_t
> ctr_idx)
> cntr_val = ldq_le_p(&s->regs_rw[RISCV_IOMMU_REG_IOHPMCTR_BASE + off]);
> stq_le_p(&s->regs_rw[RISCV_IOMMU_REG_IOHPMCTR_BASE + off], cntr_val + 1);
>
> + trace_riscv_iommu_hpm_incr_ctr(cntr_val);
> +
> /* Handle the overflow scenario. */
> if (cntr_val == UINT64_MAX) {
> /*
> @@ -244,6 +248,8 @@ void riscv_iommu_process_iocntinh_cy(RISCVIOMMUState *s,
> bool prev_cy_inh)
> return;
> }
>
> + trace_riscv_iommu_hpm_iocntinh_cy(prev_cy_inh);
> +
> if (!(inhibit & RISCV_IOMMU_IOCOUNTINH_CY)) {
> /*
> * Cycle counter is enabled. Just start the timer again and update
> @@ -268,6 +274,8 @@ void riscv_iommu_process_hpmcycle_write(RISCVIOMMUState
> *s)
> const uint64_t val = riscv_iommu_reg_get64(s,
> RISCV_IOMMU_REG_IOHPMCYCLES);
> const uint32_t ovf = riscv_iommu_reg_get32(s,
> RISCV_IOMMU_REG_IOCOUNTOVF);
>
> + trace_riscv_iommu_hpm_cycle_write(ovf, val);
> +
> /*
> * Clear OF bit in IOCNTOVF if it's being cleared in IOHPMCYCLES
> register.
> */
> @@ -352,6 +360,8 @@ void riscv_iommu_process_hpmevt_write(RISCVIOMMUState *s,
> uint32_t evt_reg)
> return;
> }
>
> + trace_riscv_iommu_hpm_evt_write(ctr_idx, ovf, val);
> +
> /* Clear OF bit in IOCNTOVF if it's being cleared in IOHPMEVT register.
> */
> if (get_field(ovf, BIT(ctr_idx + 1)) &&
> !get_field(val, RISCV_IOMMU_IOHPMEVT_OF)) {
> diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events
> index aaa2c0eb94..846f5f19c7 100644
> --- a/hw/riscv/trace-events
> +++ b/hw/riscv/trace-events
> @@ -19,3 +19,8 @@ riscv_iommu_sys_irq_sent(uint32_t vector) "IRQ sent to
> vector %u"
> riscv_iommu_sys_msi_sent(uint32_t vector, uint64_t msi_addr, uint32_t
> msi_data, uint32_t result) "MSI sent to vector %u msi_addr 0x%lx msi_data
> 0x%x result %u"
> riscv_iommu_sys_reset_hold(int reset_type) "reset type %d"
> riscv_iommu_pci_reset_hold(int reset_type) "reset type %d"
> +riscv_iommu_hpm_read(uint64_t cycle, uint32_t inhibit, uint64_t ctr_prev,
> uint64_t ctr_val) "cycle 0x%lx inhibit 0x%x ctr_prev 0x%lx ctr_val 0x%lx"
> +riscv_iommu_hpm_incr_ctr(uint64_t cntr_val) "cntr_val 0x%lx"
> +riscv_iommu_hpm_iocntinh_cy(bool prev_cy_inh) "prev_cy_inh %d"
> +riscv_iommu_hpm_cycle_write(uint32_t ovf, uint64_t val) "ovf 0x%x val 0x%lx"
> +riscv_iommu_hpm_evt_write(uint32_t ctr_idx, uint32_t ovf, uint64_t val)
> "ctr_idx 0x%x ovf 0x%x val 0x%lx"
> --
> 2.47.1
>
>
