Thank you for your response.
On 11/4/24 20:51:40, Richard Henderson wrote:
> User emulation does not have multiple mappings of the same physical page
> like system mode does. This is because in user emulation we have only one
> process to emulate.
To clarify, is the reason QEMU does not use `CF
On 11/4/24 22:29, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
This way it is clearly known when there's no more data to send for that
device.
Signed-off-by: Maciej S. Szmigiero
---
hw/vfio/migration.c | 8
hw/vfio/trace-events | 1 +
include/hw/vfio/
05.11.2024 10:45, Michael Tokarev wrote:
target/riscv/csr.c: Fix an access to VXSAT
hw/intc: Don't clear pending bits on IRQ lowering
target/riscv: Set vtype.vill on CPU reset
hw/intc/riscv_aplic: Check and update pending when write sourcecfg
target/riscv/kvm: set 'aia_mode' to default in error
On 2024/11/03 22:34, Bernhard Beschow wrote:
Instead of defining redundant constants and using magic numbers reuse the
existing MII constants.
Signed-off-by: Bernhard Beschow
cc: Akihiko Odaki
Reviewed-by: Akihiko Odaki
For TDX, some CPUID feature bit is configured via TD attributes. Adjust
the supported CPUID to mask off the bit if its matched attribute is
unsupported.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.h | 4
target/i386/kvm/tdx.c | 54 +++
2 files
>-Original Message-
>From: CLEMENT MATHIEU--DRIF
>Sent: Tuesday, November 5, 2024 2:36 PM
>Subject: Re: [PATCH 2/3] intel_iommu: Add missed sanity check for 256-bit
>invalidation queue
>
>I saw the pull request, just a few questions/comments in case there is a
>new spin.
>These are not h
31.10.2024 06:52, Alistair Francis wrote:
From: TANG Tiancheng
...
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1619c3acb6..a63a29744c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -709,8 +709,11 @@ static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
#ifdef C
>-Original Message-
>From: Liu, Yi L
>Sent: Tuesday, November 5, 2024 2:30 PM
>Subject: Re: [PATCH v4 13/17] intel_iommu: piotlb invalidation should notify
>unmap
>
>On 2024/11/4 16:15, Duan, Zhenzhong wrote:
>>
>>> vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
Implement TDX specific ConfidentialGuestSupportClass::kvm_init()
callback, tdx_kvm_init().
Mark guest state is proctected for TDX VM. More TDX specific
initialization will be added later.
Signed-off-by: Xiaoyao Li
---
Changes in v6:
- remove Acked-by from Gerd since the patch changed due to us
TDX doesn't support SMM and VMM cannot emulate SMM for TDX VMs because
VMM cannot manipulate TDX VM's memory.
Disable SMM for TDX VMs and error out if user requests to enable SMM.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
target/i386/kvm/tdx.c | 9 +
1 file changed, 9 inser
Hi,
lgtm
Thanks
cmd
On 04/11/2024 13:55, Zhenzhong Duan wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> According to VTD spec, Figure 11-22, Invalidation Queue Tail Register,
> "When
TDX vcpu needs to be initialized by SEAMCALL(TDH.VP.INIT) and KVM
provides vcpu level IOCTL KVM_TDX_INIT_VCPU for it.
KVM_TDX_INIT_VCPU needs the address of the HOB as input. Invoke it for
each vcpu after HOB list is created.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
target/i386/kv
To do cgs specific feature checking. Note the feature checking in
x86_cpu_filter_features() is valid for non-cgs VMs. For cgs VMs like
TDX, what features can be supported has more restrictions.
Signed-off-by: Xiaoyao Li
---
target/i386/confidential-guest.h | 13 +
target/i386/kvm/kvm
On 2024/11/4 20:55, Zhenzhong Duan wrote:
IEC descriptor is 128-bit invalidation descriptor, must be padded with
128-bits of 0s in the upper bytes to create a 256-bit descriptor when
the invalidation queue is configured for 256-bit descriptors (IQA_REG.DW=1).
Fixes: 02a2cbc872df ("x86-iommu: int
Bit 28 of TD attribute, named SEPT_VE_DISABLE. When set to 1, it disables
EPT violation conversion to #VE on guest TD access of PENDING pages.
Some guest OS (e.g., Linux TD guest) may require this bit as 1.
Otherwise refuse to boot.
Add sept-ve-disable property for tdx-guest object, for user to c
On 2024/11/4 20:55, Zhenzhong Duan wrote:
According to VTD spec, Figure 11-22, Invalidation Queue Tail Register,
"When Descriptor Width (DW) field in Invalidation Queue Address Register
(IQA_REG) is Set (256-bit descriptors), hardware treats bit-4 as reserved
and a value of 1 in the bit will resu
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 29 +
target/i386/cpu.h | 5 +
2 files changed, 34 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e728fb6b9f10..472ab206d8fe 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5507,
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/tdx.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c
index 9cb099e160e4..05475edf72bd 100644
--- a/target/i386/kvm/tdx.c
+++ b/target/i386/kvm/tdx.c
@@ -734,6 +734,13 @@ static int tdx_check_fe
On 2024/11/5 14:12, Duan, Zhenzhong wrote:
-Original Message-
From: Liu, Yi L
Sent: Tuesday, November 5, 2024 1:05 PM
Subject: Re: [PATCH 2/3] intel_iommu: Add missed sanity check for 256-bit
invalidation queue
On 2024/11/4 20:55, Zhenzhong Duan wrote:
According to VTD spec, a 256-b
Validate TD attributes with tdx_caps that fixed-0 bits must be zero and
fixed-1 bits must be set.
Besides, sanity check the attribute bits that have not been supported by
QEMU yet. e.g., debug bit, it will be allowed in the future when debug
TD support lands in QEMU.
Signed-off-by: Xiaoyao Li
Ac
Expose mark_unavailable_features() out of cpu.c so that it can be used
by TDX when features are masked off.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 4 ++--
target/i386/cpu.h | 2 ++
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
ind
Because for TDX case, there are also fixed-1 bits that enfored by TDX
module.
Signed-off-by: Xiaoyao Li
---
target/i386/confidential-guest.h | 20 ++--
target/i386/kvm/kvm.c| 2 +-
target/i386/sev.c| 4 ++--
3 files changed, 13 insertions(+), 13 dele
For TDs, only MSR_IA32_UCODE_REV in kvm_init_msrs() can be configured
by VMM, while the features enumerated/controlled by other MSRs except
MSR_IA32_UCODE_REV in kvm_init_msrs() are not under control of VMM.
Only configure MSR_IA32_UCODE_REV for TDs.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoff
KVM doesn't allow wirting to MSR_IA32_APICBASE for TDs.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
target/i386/kvm/kvm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index 8909fce14909..c39e879a77e9 100644
--- a/target/i386/kv
TDX only supports readonly for shared memory but not for private memory.
In the view of QEMU, it has no idea whether a memslot is used as shared
memory of private. Thus just mark kvm_readonly_mem_enabled to false to
TDX VM for simplicity.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
t
KVM translates TDG.VP.VMCALL to KVM_HC_MAP_GPA_RANGE, and QEMU
needs to enable user exit on KVM_HC_MAP_GPA_RANGE in order to handle the
memory conversion requested by TD guest.
Signed-off-by: Xiaoyao Li
---
changes in v6:
- new patch;
---
target/i386/kvm/tdx.c | 7 +++
1 file changed, 7 ins
It will need special handling for TDX VMs all around the QEMU.
Introduce is_tdx_vm() helper to query if it's a TDX VM.
Cache tdx_guest object thus no need to cast from ms->cgs every time.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
Reviewed-by: Isaku Yamahata
---
changes in v3:
- replace
Mask off the CPUID bits as unsupported if its matched XFAM bit is
not supported. Otherwise, it might fail the check in setup_td_xfam() as
unsupported XFAM being requested.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/tdx.c | 38 ++
1 file changed, 38 insertio
TDX uses CPUID 0x1f to configure TD guest's CPU topology. So set
enable_cpuid_0x1f for TDs.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/tdx.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c
index 289722a129ce..19ce90df4143 100644
--- a/targ
From: Sean Christopherson
Don't get/put state of TDX VMs since accessing/mutating guest state of
production TDs is not supported.
Note, it will be allowed for a debug TD. Corresponding support will be
introduced when debug TD support is implemented in the future.
Signed-off-by: Sean Christopher
Currently cpu->nr_cores and cpu->nr_threads are initialized in
qemu_init_vcpu(), which is called a bit late in *cpu_realizefn() for
each ARCHes.
x86 arch would like to set CPUID_HT in env->features[FEAT_1_EDX] based
on the value of cpu->nr_threads * cpu->nr_cores. It requires nr_cores
and nr_threa
Introduce kvm_arch_pre_create_vcpu(), to perform arch-dependent
work prior to create any vcpu. This is for i386 TDX because it needs
call TDX_INIT_VM before creating any vcpu.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
Changes in v3:
- pass @errp to kvm_arch_pre_create_vcpu(); (Per Da
The TD HOB list is used to pass the information from VMM to TDVF. The TD
HOB must include PHIT HOB and Resource Descriptor HOB. More details can
be found in TDVF specification and PI specification.
Build the TD HOB in TDX's machine_init_done callback.
Co-developed-by: Isaku Yamahata
Signed-off-b
Currently, QEMU exposes CPUID 0x1f to guest only when necessary, i.e.,
when topology level that cannot be enumerated by leaf 0xB, e.g., die or
module level, are configured for the guest, e.g., -smp xx,dies=2.
However, TDX architecture forces to require CPUID 0x1f to configure CPU
topology.
Introd
After TDVF is loaded to bios MemoryRegion, it needs parse TDVF metadata.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
hw/i386/pc_sysfw.c | 7 +++
target/i386/kvm/tdx-stub.c | 5 +
target/i386/kvm/tdx.c | 5 +
target/i386/kvm/tdx.h | 3 +++
4 files changed,
From: Isaku Yamahata
TDX VM needs to boot with its specialized firmware, Trusted Domain
Virtual Firmware (TDVF). QEMU needs to parse TDVF and map it in TD
guest memory prior to running the TDX VM.
A TDVF Metadata in TDVF image describes the structure of firmware.
QEMU refers to it to setup memor
From: Isaku Yamahata
TSC of TDs is not accessible and KVM doesn't allow access of
MSR_IA32_TSC for TDs. To avoid the assert() in kvm_get_tsc, make
kvm_synchronize_all_tsc() noop for TDs,
Signed-off-by: Isaku Yamahata
Reviewed-by: Connor Kuehl
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
Add docs/system/i386/tdx.rst for TDX support, and add tdx in
confidential-guest-support.rst
Signed-off-by: Xiaoyao Li
---
Changes in v6:
- Add more information of "Feature configuration"
- Mark TD Attestation as future work because KVM now drops the support
of it.
Changes in v5:
- Add TD a
To execute confidential guest specific cpu realize operations.
Signed-off-by: Xiaoyao Li
---
changes in v6:
- new patch;
---
target/i386/confidential-guest.h | 12
target/i386/cpu.c| 13 -
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/ta
Integrate TDX's TDX_REPORT_FATAL_ERROR into QEMU GuestPanic facility
Originated-from: Isaku Yamahata
Signed-off-by: Xiaoyao Li
---
Changes in v6:
- change error_code of GuestPanicInformationTdx from uint64_t to
uint32_t, to only contains the bit 31:0 returned in r12.
Changes in v5:
- mention
The RAM of TDX VM can be classified into two types:
- TDX_RAM_UNACCEPTED: default type of TDX memory, which needs to be
accepted by TDX guest before it can be used and will be all-zeros
after being accepted.
- TDX_RAM_ADDED: the RAM that is ADD'ed to TD guest before running, and
can be
They will be used by TDX.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 3 ---
target/i386/cpu.h | 5 +
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 119b38bcb0c1..8c507ad406e7 100644
--- a/target/i386/cpu.c
+++ b/target/i386/c
Invoke KVM_TDX_FINALIZE_VM to finalize the TD's measurement and make
the TD vCPUs runnable once machine initialization is complete.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
target/i386/kvm/tdx.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/i386/kvm/tdx.c b/targ
1. QEMU's support for Intel PT is borken in general, thus doesn't
support for TDX.
2. Only limited KVM PV features are supported for TD guest.
3. Drop the AMD specific bits that are reserved on Intel platform.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/tdx.c | 44
From: Isaku Yamahata
TDVF firmware (CODE and VARS) needs to be copied to TD's private
memory via KVM_TDX_INIT_MEM_REGION, as well as TD HOB and TEMP memory.
If the TDVF section has TDVF_SECTION_ATTRIBUTES_MR_EXTEND set in the
flag, calling KVM_TDX_EXTEND_MEMORY to extend the measurement.
After
For TDX guest, KVM doesn't allow phys_bits configuration and the
phys_bits can only be native/host value.
Add the logic to set cpu->phys_bits to host value when user doesn't
give a explicit one and error out when user desires a different one
than host value.
Signed-off-by: Xiaoyao Li
---
Changes
Because it's fixed1 bit that enforced by TDX module.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/tdx.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c
index 05475edf72bd..4cb1f4ac3479 100644
--- a/target/i386/kvm/tdx.c
+++ b/target/i386/kvm/
Add a new bool member, eoi_intercept_unsupported, to X86MachineState
with default value false. Set true for TDX VM.
Inability to intercept eoi causes impossibility to emulate level
triggered interrupt to be re-injected when level is still kept active.
which affects interrupt controller emulation.
From: Isaku Yamahata
When level trigger isn't supported on x86 platform,
forcibly report edge trigger in acpi tables.
Signed-off-by: Isaku Yamahata
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
hw/i386/acpi-build.c | 99 ---
hw/i386/acpi-commo
Introduce tdx-guest object which inherits X86_CONFIDENTIAL_GUEST,
and will be used to create TDX VMs (TDs) by
qemu -machine ...,confidential-guest-support=tdx0 \
-object tdx-guest,id=tdx0
It has one QAPI member 'attributes' defined, which allows user to set
TD's attributes directly.
From: Isaku Yamahata
Three sha384 hash values, mrconfigid, mrowner and mrownerconfig, of a TD
can be provided for TDX attestation. Detailed meaning of them can be
found:
https://lore.kernel.org/qemu-devel/31d6dbc1-f453-4cef-ab08-4813f4e0f...@intel.com/
Allow user to specify those values via pro
Legacy PIC (8259) cannot be supported for TDX VMs since TDX module
doesn't allow directly interrupt injection. Using posted interrupts
for the PIC is not a viable option as the guest BIOS/kernel will not
do EOI for PIC IRQs, i.e. will leave the vIRR bit set.
Hence disable PIC for TDX VMs and erro
TD guest can use TDG.VP.VMCALL to request
termination. KVM translates such request into KVM_EXIT_SYSTEM_EVENT with
type of KVM_SYSTEM_EVENT_TDX_FATAL.
Add hanlder for such exit. Parse and print the error message, and
terminate the TD guest in the handler.
Signed-off-by: Xiaoyao Li
---
Changes in
To allow execute confidential guest specific cpu init operations.
Signed-off-by: Xiaoyao Li
---
Changes in v6:
- new patch;
---
target/i386/confidential-guest.h | 11 +++
target/i386/cpu.c| 10 ++
2 files changed, 21 insertions(+)
diff --git a/target/i386/confid
For each TDVF sections, QEMU needs to copy the content to guest
private memory via KVM API (KVM_TDX_INIT_MEM_REGION).
Introduce a field @mem_ptr for TdxFirmwareEntry to track the memory
pointer of each TDVF sections. So that QEMU can add/copy them to guest
private memory later.
TDVF sections can
Add UEFI definitions for literals, enums, structs, GUIDs, etc... that
will be used by TDX to build the UEFI Hand-Off Block (HOB) that is passed
to the Trusted Domain Virtual Firmware (TDVF).
All values come from the UEFI specification [1], PI spec [2] and TDVF
design guide[3].
[1] UEFI Specificat
TDX VM requires VM type to be KVM_X86_TDX_VM. Implement tdx_kvm_type()
as X86ConfidentialGuestClass->kvm_type.
Signed-off-by: Xiaoyao Li
---
Changes in v6:
- new added patch;
---
target/i386/kvm/kvm.c | 1 +
target/i386/kvm/tdx.c | 12
2 files changed, 13 insertions(+)
diff --git
KVM provides TDX capabilities via sub command KVM_TDX_CAPABILITIES of
IOCTL(KVM_MEMORY_ENCRYPT_OP). Get the capabilities when initializing
TDX context. It will be used to validate user's setting later.
Since there is no interface reporting how many cpuid configs contains in
KVM_TDX_CAPABILITIES, Q
For QEMU VMs,
- PKS is configured via CPUID_7_0_ECX_PKS, e.g., -cpu xxx,+pks and
- PMU is configured by x86cpu->enable_pmu, e.g., -cpu xxx,pmu=on
While the bit 30 (PKS) and bit 63 (PERFMON) of TD's attributes are also
used to configure the PKS and PERFMON/PMU of TD, reuse the existing
configu
Reuse "-cpu,tsc-frequency=" to get user wanted tsc frequency and call VM
scope VM_SET_TSC_KHZ to set the tsc frequency of TD before KVM_TDX_INIT_VM.
Besides, sanity check the tsc frequency to be in the legal range and
legal granularity (required by TDX module).
Signed-off-by: Xiaoyao Li
Acked-by
Hi,
lgtm
Thanks
cmd
On 04/11/2024 13:55, Zhenzhong Duan wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> IEC descriptor is 128-bit invalidation descriptor, must be padded with
> 128-
I saw the pull request, just a few questions/comments in case there is a
new spin.
These are not hard requirements, the current version looks good as well.
On 04/11/2024 13:55, Zhenzhong Duan wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from
From: Chao Peng
TDVF(OVMF) needs to run at private memory for TD guest. TDX cannot
support pflash device since it doesn't support read-only private memory.
Thus load TDVF(OVMF) with -bios option for TDs.
Use memory_region_init_ram_guest_memfd() to allocate the MemoryRegion
for TDVF because it ne
Pull in recent TDX updates, which are not backwards compatible.
It's just to make this series runnable. It will be updated by script
scripts/update-linux-headers.sh
once TDX support is upstreamed in linux kernel
Signed-off-by: Xiaoyao Li
---
linux-headers/asm-x86/kvm.h | 70 ++
This is the v6 series of TDX QEMU enabling. The matching KVM is
https://github.com/intel/tdx/tree/tdx_kvm_dev-2024-10-30
This series is also available in github:
https://github.com/intel-staging/qemu-tdx/tree/tdx-qemu-upstream-v6.1
Note, to boot a TD, it requires 1)TDX module 1.5.06.00.0744[0], o
On 2024/11/5 14:03, Duan, Zhenzhong wrote:
-Original Message-
From: Liu, Yi L
Sent: Tuesday, November 5, 2024 1:56 PM
Subject: Re: [PATCH v4 15/17] intel_iommu: Introduce a property x-fls for
scalable modern mode
On 2024/11/5 11:11, Duan, Zhenzhong wrote:
+DEFINE_PROP_BOOL("x-f
>-Original Message-
>From: Liu, Yi L
>Sent: Tuesday, November 5, 2024 1:05 PM
>Subject: Re: [PATCH 2/3] intel_iommu: Add missed sanity check for 256-bit
>invalidation queue
>
>On 2024/11/4 20:55, Zhenzhong Duan wrote:
>> According to VTD spec, a 256-bit descriptor will result in an inval
>-Original Message-
>From: Liu, Yi L
>Sent: Tuesday, November 5, 2024 1:56 PM
>Subject: Re: [PATCH v4 15/17] intel_iommu: Introduce a property x-fls for
>scalable modern mode
>
>On 2024/11/5 11:11, Duan, Zhenzhong wrote:
>
>> +DEFINE_PROP_BOOL("x-fls", IntelIOMMUState, scalable_m
From: Prasad Pandit
While starting a vhost device, updating iotlb entries
via 'vhost_device_iotlb_miss' may return an error.
qemu-kvm: vhost_device_iotlb_miss:
700871,700871: Fail to update device iotlb
Fail device start when such an error occurs.
Signed-off-by: Prasad Pandit
---
hw/vi
On 2024/11/5 11:11, Duan, Zhenzhong wrote:
+DEFINE_PROP_BOOL("x-fls", IntelIOMMUState, scalable_modern, FALSE),
DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control,
false),
a question: is there any requirement on the layout of this array? Should
new fields added in the
On 2024/11/4 20:55, Zhenzhong Duan wrote:
According to VTD spec, a 256-bit descriptor will result in an invalid
descriptor error if submitted in an IQ that is setup to provide hardware
with 128-bit descriptors (IQA_REG.DW=0). Meanwhile, there are old inv desc
types (e.g. iotlb_inv_desc) that can
On 11/4/24 19:53, Demin Han wrote:
It seems that you already have a wrapper script (qemu-risv64.sh). You can
replace it and read command line from $@, which contains the command
passed to it.
In the case of llvm-test-suite, you can set TEST_SUITE_RUN_UNDER to a
wrapper adding a specific plugi
Thanks for the review.
Feel free to pull the patch in your next PR, so it can be available for
release 9.2.
Regards,
Pierrick
On 11/4/24 18:37, Alistair Francis wrote:
On Tue, Nov 5, 2024 at 8:23 AM Pierrick Bouvier
wrote:
Introduced in 0c54ac, "hw/riscv: add RISC-V IOMMU base emulation"
>
> It seems that you already have a wrapper script (qemu-risv64.sh). You can
> replace it and read command line from $@, which contains the command
> passed to it.
> >> In the case of llvm-test-suite, you can set TEST_SUITE_RUN_UNDER to a
> >> wrapper adding a specific plugin, its options, and g
On 11/4/24 19:31, Demin Han wrote:
-Original Message-
From: Pierrick Bouvier
Sent: 2024年11月5日 10:50
To: Demin Han ; qemu-devel@nongnu.org
Cc: alex.ben...@linaro.org; erdn...@crans.org; ma.mando...@gmail.com
Subject: Re: [PATCH] plugins: add plugin API to get args passed to binary
On
From: Ilya Leoshkevich
bsd-user qemu-x86_64 almost immediately dies with:
qemu: 0x4002201a68: unhandled CPU exception 0xd - aborting
on FreeBSD 14.1-RELEASE. This is an instruction that requires
alignment:
(gdb) x/i 0x4002201a68
0x4002201a68:movaps %xmm0,-0x40(%rbp)
and
From: Jessica Clarke
Currently we only set it on fork.
Note: Upstream (blitz) commit also did new threads, but that code isn't
in qemu project repo yet.
Signed-off-by: Jessica Clarke
Pull-Request: https://github.com/qemu-bsd-user/qemu-bsd-user/pull/52
Reviewed-by: Warner Losh
Signed-off-by: W
The following changes since commit daaf51001a13da007d7dde72e1ed3b06bc490791:
Merge tag 'seabios-hppa-v17-pull-request' of
https://github.com/hdeller/qemu-hppa into staging (2024-11-04 16:01:23 +)
are available in the Git repository at:
g...@gitlab.com:bsdimp/qemu.git tags/bsd-user-2024q
From: Ilya Leoshkevich
While qemu-system can set tb-size using -accel tcg,tb-size=n, there
is no similar knob for qemu-bsd-user. Add one in a way similar to how
one-insn-per-tb is already handled.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Ilya Leoshkevich
Reviewed-by: Philippe Mathie
Hi,
this test was recently broken by 34a889 (migration: Drop
migration_is_idle()).
Reproduce with:
meson test -C build -t 1 --setup slow --num-processes 1
--print-errorlogs io-raw-055 --verbose
1/1 qemu:block-slow+slow / io-raw-055RUNNING
>>> ASAN_OPTIONS=halt_on_error=1:abort_on_e
On Thu, Sep 19, 2024 at 3:15 AM Max Chou wrote:
>
> Hi,
>
> This version fixes several issues in v5
> - The cross page bound checking issue
> - The mismatch vl comparison in the early exit checking of vext_ldst_us
> - The endian issue when host is big endian
>
> Thank for Richard Henderson's sugge
On 11/4/24 1:26 AM, Salil Mehta wrote:
Refactor GICv3 code for TCG and KVM to initialize the GIC CPU interface
register information by introducing a new common hook
`ARMGICv3CommonClass::init_cpu_reginfo`. This hook can be assigned to
the respective TCG or KVM variants during the GICv3 initializa
> -Original Message-
> From: Pierrick Bouvier
> Sent: 2024年11月5日 10:50
> To: Demin Han ; qemu-devel@nongnu.org
> Cc: alex.ben...@linaro.org; erdn...@crans.org; ma.mando...@gmail.com
> Subject: Re: [PATCH] plugins: add plugin API to get args passed to binary
>
> On 11/4/24 18:29, Demin H
>-Original Message-
>From: Liu, Yi L
>Sent: Monday, November 4, 2024 3:23 PM
>Subject: Re: [PATCH v4 15/17] intel_iommu: Introduce a property x-fls for
>scalable modern mode
>
>On 2024/11/4 14:25, Duan, Zhenzhong wrote:
>>
>>
>>> -Original Message-
>>> From: Liu, Yi L
>>> Sent:
On 2024/11/5 06:22, Pierrick Bouvier wrote:
Introduced in 0c54ac, "hw/riscv: add RISC-V IOMMU base emulation"
../hw/riscv/riscv-iommu.c:187:17: error: redefinition of '_pext_u64'
187 | static uint64_t _pext_u64(uint64_t val, uint64_t ext)
| ^
D:/a/_temp/msys64/clan
On 11/4/24 18:29, Demin Han wrote:
-Original Message-
From: Pierrick Bouvier
Sent: 2024年11月5日 5:22
To: Demin Han ; qemu-devel@nongnu.org
Cc: alex.ben...@linaro.org; erdn...@crans.org; ma.mando...@gmail.com
Subject: Re: [PATCH] plugins: add plugin API to get args passed to binary
On 11
>-Original Message-
>From: Michael S. Tsirkin
>Subject: Re: [PATCH 2/3] intel_iommu: Add missed sanity check for 256-bit
>invalidation queue
>
>On Mon, Nov 04, 2024 at 08:55:35PM +0800, Zhenzhong Duan wrote:
>> According to VTD spec, a 256-bit descriptor will result in an invalid
>> des
On Tue, Nov 5, 2024 at 8:23 AM Pierrick Bouvier
wrote:
>
> Introduced in 0c54ac, "hw/riscv: add RISC-V IOMMU base emulation"
>
> ../hw/riscv/riscv-iommu.c:187:17: error: redefinition of '_pext_u64'
>
> 187 | static uint64_t _pext_u64(uint64_t val, uint64_t ext)
>
> | ^
>
>
Hello:
This patch was applied to netdev/net-next.git (main)
by Jakub Kicinski :
On Sat, 02 Nov 2024 16:52:17 -0500 you wrote:
> From: David Woodhouse
>
> The VMCLOCK device gives support for accurate timekeeping even across
> live migration, unlike the KVM PTP clock. To help ensure that users c
> -Original Message-
> From: Pierrick Bouvier
> Sent: 2024年11月5日 5:22
> To: Demin Han ; qemu-devel@nongnu.org
> Cc: alex.ben...@linaro.org; erdn...@crans.org; ma.mando...@gmail.com
> Subject: Re: [PATCH] plugins: add plugin API to get args passed to binary
>
> On 11/1/24 22:10, Demin Han
From: Vivek Kasireddy
Since gdk_window_get_root_coords() expects a position within the window,
we need to translate Guest's cooridinates to window local coordinates
by multiplying them with the scaling factor.
Cc: Marc-André Lureau
Signed-off-by: Vivek Kasireddy
Signed-off-by: Dongwon Kim
---
On Sat, 02 Nov 2024 16:52:17 -0500 David Woodhouse wrote:
> From: David Woodhouse
>
> The VMCLOCK device gives support for accurate timekeeping even across
> live migration, unlike the KVM PTP clock. To help ensure that users can
> always use ptp_vmclock where it's available in preference to ptp
Paolo Bonzini writes:
> On 11/3/24 10:54, Junjie Mao wrote:
>> Paolo Bonzini writes:
>>
>>> diff --git a/rust/qemu-api-macros/src/lib.rs
>>> b/rust/qemu-api-macros/src/lib.rs
>>> index a4bc5d01ee8..c2ea22101e4 100644
>>> --- a/rust/qemu-api-macros/src/lib.rs
>>> +++ b/rust/qemu-api-macros/src
On 11/4/24 1:24 AM, Salil Mehta wrote:
Extract common GIC and CPU interrupt wiring code to improve code
readability and modularity, supporting reuse in future patch sets. This
refactor is benign and introduces *no* functional changes.
Note: This patch has been isolated from a larger patch set to
On 11/4/24 11:26 PM, Peter Maydell wrote:
On Sun, 3 Nov 2024 at 15:25, Salil Mehta wrote:
Extract common GIC and CPU interrupt wiring code to improve code
readability and modularity, supporting reuse in future patch sets. This
refactor is benign and introduces *no* functional changes.
Note: T
On 11/4/24 1:22 AM, Salil Mehta wrote:
Refactor vCPU properties code from the `machvirt_init()` main loop with
the following goals:
1. Enable code reuse in future patch sets.
2. Improve code readability.
3. Separate out the one-time initialization of (secure-)Tagged memory,
handling potentia
On Tue, Nov 5, 2024 at 2:35 AM Thomas Huth wrote:
>
> Casting a "uint32_t *" to a "uint8_t *" to get to the lowest 8-bit
> part of the value does not work on big endian hosts. We've got to
> take the proper detour through an 8-bit variable.
>
> Fixes: 53c1557b23 ("hw/char: sifive_uart: Print uart
On Mon, Nov 4, 2024 at 10:40 PM Daniel Henrique Barboza
wrote:
>
> 'mode' will never be RISCV_IOMMU_CAP_SV32. We are erroring out in the
> 'switch' right before it if 'mode' isn't 0, 8, 9 or 10.
>
> 'mode' should be check with RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32.
>
> Reported by Coverity via a "DE
On Mon, Nov 4, 2024 at 10:41 PM Daniel Henrique Barboza
wrote:
>
> Coverity reports an unsigned overflow when doing:
>
> for (; depth-- > 0; ) {
>
> When depth = 0 inside riscv_iommu_ctx_fetch().
>
> Building it with a recent GCC the code doesn't actually break with depth
> = 0, i.e. the compa
On Tue, Nov 5, 2024 at 3:36 AM Andrew Jones wrote:
>
> Free the temporary register list.
>
> Fixes: 608bdebb6075 ("target/riscv/kvm: support KVM_GET_REG_LIST")
> Signed-off-by: Andrew Jones
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/kvm/kvm-cpu.c | 2 ++
> 1 file ch
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