[PATCH v5 34/43] accel/tcg/plugin: Use copy_op in append_{udata, mem}_cb

Better to re-use the existing function for copying ops. Acked-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- accel/tcg/plugin-gen.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/

[PATCH v5 18/43] tcg: Massage process_op_defs()

From: Philippe Mathieu-Daudé In preparation of introducing paired registers, massage a bit process_op_defs()'s switch case. Signed-off-by: Richard Henderson [PMD: Split from bigger patch, 1/3] Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221219220925.79218-2-phi...@linaro.org> --- tcg

[PATCH v5 40/43] tcg: Factor init_ffi_layouts() out of tcg_context_init()

From: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-Id: <2022074101.2069454-27-richard.hender...@linaro.org> [PMD: Split from bigger patch] Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221122180804.938-3-phi...@linaro.org> --- tcg/t

[PATCH v5 06/43] hw/mips: Use QEMU_IOTHREAD_LOCK_GUARD in cpu_mips_irq_request

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- hw/mips/mips_int.c | 11 +-- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c index 2db5e10fe0..73437cd90f 100644 --- a/hw/mips/mips_int.c +++ b/hw/mips/mips_int.

[PATCH v5 32/43] accel/tcg/plugin: Don't search for the function pointer index

The function pointer is immediately after the output and input operands; no need to search. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- accel/tcg/plugin-gen.c | 29 +++-- 1 file changed, 11 insertions(+), 18 deletions(-) diff --git a/accel/t

[PATCH v5 33/43] accel/tcg/plugin: Avoid duplicate copy in copy_call

We copied all of the arguments in copy_op_nocheck. We only need to replace the one argument that we change. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- accel/tcg/plugin-gen.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/accel/tcg/pl

[PATCH v5 19/43] tcg: Introduce paired register allocation

There are several instances where we need to be able to allocate a pair of registers to related inputs/outputs. Add 'p' and 'm' register constraints for this, in order to be able to allocate the even/odd register first or second. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 2 + tc

[PATCH v5 43/43] tcg: Add TCGHelperInfo argument to tcg_out_call

This eliminates an ifdef for TCI, and will be required for expanding the call for TCGv_i128. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg.c| 12 ++-- tcg/aarch64/tcg-target.c.inc | 12 +--- tcg/arm/tcg-target.c.inc

[PATCH v5 07/43] target/ppc: Use QEMU_IOTHREAD_LOCK_GUARD in ppc_maybe_interrupt

Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- target/ppc/excp_helper.c | 11 +-- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index add4d54ae7..287659c74d

[PATCH v5 30/43] tcg: Replace TCG_TARGET_EXTEND_ARGS with TCG_TARGET_CALL_ARG_I32

For 64-bit hosts that had TCG_TARGET_EXTEND_ARGS, set TCG_TARGET_CALL_ARG_I32 to TCG_CALL_ARG_EXTEND. Otherwise, use TCG_CALL_ARG_NORMAL. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 1 + tcg/arm/tcg-target.h | 1 + tcg/i386/t

[PATCH v5 20/43] accel/tcg: Set cflags_next_tb in cpu_common_initfn

While we initialize this value in cpu_common_reset, that isn't called during startup, so set it as well in init. This fixes -singlestep versus the very first TB. Fixes: 04f5b647ed07 ("accel/tcg: Handle -singlestep in curr_cflags") Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- hw

[PATCH v5 29/43] tcg: Replace TCG_TARGET_CALL_ALIGN_ARGS with TCG_TARGET_CALL_ARG_I64

For 32-bit hosts when TCG_TARGET_CALL_ALIGN_ARGS was set, use TCG_CALL_ARG_EVEN. For 64-bit hosts, TCG_TARGET_CALL_ALIGN_ARGS was silently ignored, so always use TCG_CALL_ARG_NORMAL. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +-

[PATCH v5 24/43] tcg: Simplify calls to temp_sync vs mem_coherent

The first thing that temp_sync does is check mem_coherent, so there's no need for the caller to do so. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 0f580

[PATCH v5 36/43] tcg: Vary the allocation size for TCGOp

We have been allocating a worst case number of arguments to support calls. Instead, allow the size to vary. By default leave space for 4 args, to maximize reuse, but allow calls to increase the number of args to 32. Signed-off-by: Richard Henderson [PMD: Split patch in two] Signed-off-by: Philip

[PATCH v5 25/43] tcg: Allocate TCGTemp pairs in host memory order

Allocate the first of a pair at the lower address, and the second of a pair at the higher address. This will make it easier to find the beginning of the larger memory block. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 4 ++-- tcg/tcg.c

[PATCH v5 14/43] tci: MAX_OPC_PARAM_IARGS is no longer used

Unused since commit 7b7d8b2d9a ("tcg/tci: Use ffi for calls"). Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c| 1 - tcg/tci/tcg-target.c.inc | 4 2 files changed, 5 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index bdfac83492..05a241

[PATCH v5 37/43] tcg: Use output_pref wrapper function

We will shortly have the possibility of more that two outputs, though only for calls (for which preferences are moot). Avoid direct references to op->output_pref[] when possible. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 5 + tcg/tcg.c

[PATCH v5 35/43] tcg: Pass number of arguments to tcg_emit_op() / tcg_op_insert_*()

From: Philippe Mathieu-Daudé In order to have variable size allocated TCGOp, pass the number of arguments we use (and would allocate) up to tcg_op_alloc(). This alters tcg_emit_op(), tcg_op_insert_before() and tcg_op_insert_after() prototypes. In tcg_op_alloc() ensure the number of arguments is

[PATCH v5 12/43] tcg: Tidy tcg_reg_alloc_op

Replace goto allocate_in_reg with a boolean. Remove o_preferred_regs which isn't used, except to copy. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg.c | 45 + 1 file changed, 21 insertions(+), 24 deletions(-) diff -

[PATCH v5 08/43] target/ppc: Use QEMU_IOTHREAD_LOCK_GUARD in cpu_interrupt_exittb

In addition, use tcg_enabled instead of !kvm_enabled. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- target/ppc/helper_regs.c | 14 -- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/target/ppc/helper_reg

[PATCH v5 22/43] tcg: Move TCG_{LOW,HIGH} to tcg-internal.h

Move the error-generating fallback from tcg-op.c, and replace "_link_error" with modern QEMU_ERROR markup. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 33 + include/tcg/tcg.h| 12 tcg/tcg-intern

[PATCH v5 26/43] tcg: Move TCG_TYPE_COUNT outside enum

The count is not itself an enumerator. Move it outside to prevent the compiler from considering it with -Wswitch-enum. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/tcg/tc

[PATCH v5 10/43] hw/ppc: Use QEMU_IOTHREAD_LOCK_GUARD in ppc_set_irq

Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- hw/ppc/ppc.c | 10 +- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index dc86c1c7db..4e816c68c7 100644 --- a/hw/ppc/ppc.c +++ b/hw/pp

[PATCH v5 42/43] tcg/aarch64: Merge tcg_out_callr into tcg_out_call

There is only one use, and BLR is perhaps even more self-documentary than CALLR. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aar

[PATCH v5 39/43] tcg: Convert typecode_to_ffi from array to function

From: Philippe Mathieu-Daudé In the unlikely case of invalid typecode mask, the function will abort instead of returning a NULL pointer. Signed-off-by: Richard Henderson Message-Id: <2022074101.2069454-27-richard.hender...@linaro.org> [PMD: Split from bigger patch] Reviewed-by: Richard Hend

[PATCH v5 28/43] tcg: Introduce TCGCallReturnKind and TCGCallArgumentKind

Prepare to replace a bunch of separate ifdefs with a consistent way to describe the ABI of a function call. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 15 +++ 1 file changed, 15 insertions(+) diff --git a/

[PATCH v5 23/43] tcg: Add temp_subindex to TCGTemp

Record the location of a TCGTemp within a larger object. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 1 + tcg/tcg.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index d207bc47be..afa18986b1

[PATCH v5 41/43] tcg: Move ffi_cif pointer into TCGHelperInfo

Instead of requiring a separate hash table lookup, put a pointer to the CIF into TCGHelperInfo. Signed-off-by: Richard Henderson Message-Id: <2022074101.2069454-27-richard.hender...@linaro.org> [PMD: Split from bigger patch] Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud

[PATCH v5 01/43] tcg: convert tcg/README to rst

From: Mark Cave-Ayland Convert tcg/README to rst and move it to docs/devel as a new "TCG Intermediate Representation" page. There are a few minor changes to improve the aesthetic of the final output which are as follows: - Rename the title from "Tiny Code Generator - Fabrice Bellard" to "TCG

[PATCH v5 27/43] tcg: Introduce tcg_type_size

Add a helper function for computing the size of a type. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 16 tcg/tcg.c | 27 --- 2 files changed, 28 insertions(+), 15 deletions(-) diff --git a/include/

[PATCH v5 09/43] target/riscv: Use QEMU_IOTHREAD_LOCK_GUARD in riscv_cpu_update_mip

Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 10 +- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 278d163803..241d06bab8 10064

[PATCH v5 15/43] tcg: Fix tcg_reg_alloc_dup*

The assignment to mem_coherent should be done with any modification, not simply with a newly allocated register. Signed-off-by: Richard Henderson --- tcg/tcg.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 05d2b70ab7..371908b34b 100644 --- a/

[PATCH v5 03/43] tcg/s390x: Fix coding style

From: Philippe Mathieu-Daudé We are going to modify this code, so fix its style first to avoid: ERROR: spaces required around that '*' (ctx:VxV) #281: FILE: tcg/s390x/tcg-target.c.inc:1224: +uintptr_t mask = ~(0xull << i*16); ^ Revie

[PATCH v5 11/43] accel/tcg: Use QEMU_IOTHREAD_LOCK_GUARD in io_readx/io_writex

Narrow the scope of the lock to the actual read/write, moving the cpu_transation_failed call outside the lock. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 25 - 1 file changed, 8 insertions(+), 17 deletions(-) diff --git

[PATCH v5 38/43] tcg: Reorg function calls

Pre-compute the function call layout for each helper at startup. Drop TCG_CALL_DUMMY_ARG, as we no longer need to leave gaps in the op->args[] array. This allows several places to stop checking for NULL TCGTemp, to which TCG_CALL_DUMMY_ARG mapped. For tcg_gen_callN, loop over the arguments once.

[PATCH v5 13/43] tcg: Remove TCG_TARGET_STACK_GROWSUP

The hppa host code has been removed since 2013; this should have been deleted at the same time. Fixes: 802b5081233a ("tcg-hppa: Remove tcg backend") Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 1 - tcg/arm/tcg-target.h | 1 - tcg/tcg

[PATCH v5 05/43] qemu/main-loop: Introduce QEMU_IOTHREAD_LOCK_GUARD

Create a wrapper for locking/unlocking the iothread lock. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/qemu/main-loop.h | 29 + 1 file changed, 29 insertions(+) diff --git a/include/qemu/main-loop.h b/include/qemu/main-loop.h inde

[PATCH v5 31/43] tcg: Use TCG_CALL_ARG_EVEN for TCI special case

Change 32-bit tci TCG_TARGET_CALL_ARG_I32 to TCG_CALL_ARG_EVEN, to force 32-bit values to be aligned to 64-bit. With a small reorg to the argument processing loop, this neatly replaces an ifdef for CONFIG_TCG_INTERPRETER. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson ---

[PATCH v5 21/43] target/sparc: Avoid TCGV_{LOW,HIGH}

Use the official extend/extract functions instead of routines that will shortly be internal to tcg. Cc: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/translate.c | 21 - 1 file changed, 4 insertions(+), 17 deletions(-

[PATCH v5 04/43] tcg: Cleanup trailing whitespace

Remove whitespace at end of line, plus one place this also highlights some missing braces. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg.c| 33 + tcg/ppc/tcg-target.c.inc | 2 +- 2 files changed, 18 insertions(+

[PATCH v5 00/43] tcg misc patches

For v5, I've not omitted some of the reviewed patches, as I did for v4. There are only a couple of patches lacking review: 15-tcg-Fix-tcg_reg_alloc_dup.patch 19-tcg-Introduce-paired-register-allocation.patch 36-tcg-Vary-the-allocation-size-for-TCGOp.patch 38-tcg-Reorg-function-calls.patch

[PATCH v5 16/43] tcg: Centralize updates to reg_to_temp

Create two new functions, set_temp_val_{reg,nonreg}. Assert that the reg_to_temp mapping is correct before any changes are made. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg.c | 159 +- 1 file changed, 85 insertions(+)

[PATCH v5 17/43] tcg: Remove check_regs

We now check the consistency of reg_to_temp[] with each update, so the utility of checking consistency at the end of each opcode is minimal. In addition, the form of this check is quite expensive, consuming 10% of a checking-enabled build. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderso

[PATCH v5 02/43] meson: Move CONFIG_TCG_INTERPRETER to config_host

Like CONFIG_TCG, the enabled method of execution is a host property not a guest property. This exposes the define to compile-once files. Acked-by: Paolo Bonzini Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- meson.build | 4 +--- 1 file changed, 1 insertion(+), 3 del

Re: [PATCH v3 0/2] hw/arm/virt: Handle HVF in finalize_gic_version()

On 12/23/22 01:01, Alexander Graf wrote: The finalize_gic_version() function tries to determine which GIC version the current accelerator / host combination supports. During the initial HVF porting efforts, I didn't realize that I also had to touch this function. Then Zenghui brought up this func

Re: [PATCH 0/6] hw/arm: Fix smpboot[] on big-endian hosts and remove tswap32()

On 12/22/22 13:55, Philippe Mathieu-Daudé wrote: Philippe Mathieu-Daudé (6): hw/arm/aspeed: Fix smpboot[] on big-endian hosts hw/arm/raspi: Fix smpboot[] on big-endian hosts hw/arm/exynos4210: Remove tswap32() calls and constify smpboot[] hw/arm/npcm7xx: Remove tswap32() calls and con

Re: [RFC PATCH 43/43] target/loongarch: Implement vldi

On 12/24/22 00:16, Song Gao wrote: +static bool trans_vldi(DisasContext *ctx, arg_vldi *a) +{ +TCGv_i32 twd = tcg_constant_i32(a->vd); +TCGv_i32 tui = tcg_constant_i32(a->imm); + +CHECK_SXE; +gen_helper_vldi(cpu_env, twd, tui); +return true; +} + The constant should be expan

Re: [RFC PATCH 42/43] target/loongarch: Implement vld vst

On 12/24/22 00:16, Song Gao wrote: This patch includes: - VLD[X], VST[X]; - VLDREPL.{B/H/W/D}; - VSTELM.{B/H/W/D}. Signed-off-by: Song Gao --- target/loongarch/disas.c| 34 +++ target/loongarch/helper.h | 12 + target/loongarch/insn_trans/trans_lsx.c.i

Re: [RFC PATCH 40/43] target/loongarch: Implement vreplve vpack vpick

On 12/24/22 00:16, Song Gao wrote: +TRANS(vreplve_b, gen_vvr, gen_helper_vreplve_b) +TRANS(vreplve_h, gen_vvr, gen_helper_vreplve_h) +TRANS(vreplve_w, gen_vvr, gen_helper_vreplve_w) +TRANS(vreplve_d, gen_vvr, gen_helper_vreplve_d) +TRANS(vreplvei_b, gen_vv_i, gen_helper_vreplvei_b) +TRANS(vreplve

Re: [RFC PATCH 39/43] target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vr

On 12/24/22 00:16, Song Gao wrote: +DEF_HELPER_4(vinsgr2vr_b, void, env, i32, i32, i32) +DEF_HELPER_4(vinsgr2vr_h, void, env, i32, i32, i32) +DEF_HELPER_4(vinsgr2vr_w, void, env, i32, i32, i32) +DEF_HELPER_4(vinsgr2vr_d, void, env, i32, i32, i32) +DEF_HELPER_4(vpickve2gr_b, void, env, i32, i32, i

Re: [RFC PATCH 38/43] target/loongarch: Implement vbitsel vset

On 12/24/22 00:16, Song Gao wrote: +DEF_HELPER_5(vbitsel_v, void, env, i32, i32, i32, i32) This is tcg_gen_gvec_bitsel. The immediate version would require dupi. r~

Re: [RFC PATCH 36/43] target/loongarch: Implement vseq vsle vslt

On 12/24/22 00:16, Song Gao wrote: +DEF_HELPER_4(vseq_b, void, env, i32, i32, i32) +DEF_HELPER_4(vseq_h, void, env, i32, i32, i32) +DEF_HELPER_4(vseq_w, void, env, i32, i32, i32) +DEF_HELPER_4(vseq_d, void, env, i32, i32, i32) +DEF_HELPER_4(vseqi_b, void, env, i32, i32, i32) +DEF_HELPER_4(vseqi_h

Re: [RFC PATCH 23/43] target/loongarch: Implement vsll vsrl vsra vrotr

On 12/24/22 00:16, Song Gao wrote: +DEF_HELPER_4(vsll_b, void, env, i32, i32, i32) +DEF_HELPER_4(vsll_h, void, env, i32, i32, i32) +DEF_HELPER_4(vsll_w, void, env, i32, i32, i32) +DEF_HELPER_4(vsll_d, void, env, i32, i32, i32) +DEF_HELPER_4(vslli_b, void, env, i32, i32, i32) +DEF_HELPER_4(vslli_h

Re: [RFC PATCH 22/43] target/loongarch: Implement LSX logic instructions

On 12/24/22 00:16, Song Gao wrote: +TRANS(vand_v, gen_vvv, gen_helper_vand_v) +TRANS(vor_v, gen_vvv, gen_helper_vor_v) +TRANS(vxor_v, gen_vvv, gen_helper_vxor_v) +TRANS(vnor_v, gen_vvv, gen_helper_vnor_v) +TRANS(vandn_v, gen_vvv, gen_helper_vandn_v) +TRANS(vorn_v, gen_vvv, gen_helper_vorn_v) Th

Re: [RFC PATCH 21/43] target/loongarch: Implement vmskltz/vmskgez/vmsknz

On 12/24/22 00:16, Song Gao wrote: +static void do_vmskltz(vec_t *Vd, vec_t *Vj, int bit, int n) +{ +switch (bit) { +case 8: +Vd->H[0] |= ((0x80 & Vj->B[n]) == 0) << n; +break; +case 16: +Vd->H[0] |= ((0x8000 & Vj->H[n]) == 0) << n; +break; +case 32

Re: [RFC PATCH 20/43] target/loongarch: Implement vsigncov

On 12/24/22 00:16, Song Gao wrote: +static void do_vsigncov(vec_t *Vd, vec_t *Vj, vec_t *Vk, int bit, int n) +{ +switch (bit) { +case 8: +Vd->B[n] = (Vj->B[n] == 0x0) ? 0 : + (Vj->B[n] < 0) ? -Vk->B[n] : Vk->B[n]; +break; +case 16: +Vd->H[n] =

Re: [RFC PATCH 18/43] target/loongarch: Implement vsat

On 12/24/22 00:16, Song Gao wrote: +TRANS(vsat_b, gen_vv_i, gen_helper_vsat_b) +TRANS(vsat_h, gen_vv_i, gen_helper_vsat_h) +TRANS(vsat_w, gen_vv_i, gen_helper_vsat_w) +TRANS(vsat_d, gen_vv_i, gen_helper_vsat_d) +TRANS(vsat_bu, gen_vv_i, gen_helper_vsat_bu) +TRANS(vsat_hu, gen_vv_i, gen_helper_vsa

Re: [RFC PATCH 16/43] target/loongarch: Implement vmadd/vmsub/vmaddw{ev/od}

On 12/24/22 00:16, Song Gao wrote: +TRANS(vmadd_b, gen_vvv, gen_helper_vmadd_b) +TRANS(vmadd_h, gen_vvv, gen_helper_vmadd_h) +TRANS(vmadd_w, gen_vvv, gen_helper_vmadd_w) +TRANS(vmadd_d, gen_vvv, gen_helper_vmadd_d) +TRANS(vmsub_b, gen_vvv, gen_helper_vmsub_b) +TRANS(vmsub_h, gen_vvv, gen_helper_v

Re: [RFC PATCH 15/43] target/loongarch: Implement vmul/vmuh/vmulw{ev/od}

On 12/24/22 00:16, Song Gao wrote: +DEF_HELPER_4(vmul_b, void, env, i32, i32, i32) +DEF_HELPER_4(vmul_h, void, env, i32, i32, i32) +DEF_HELPER_4(vmul_w, void, env, i32, i32, i32) +DEF_HELPER_4(vmul_d, void, env, i32, i32, i32) These are tcg_gen_gvec_mul. +DEF_HELPER_4(vmuh_b, void, env, i32,

Re: [RFC PATCH 14/43] target/loongarch: Implement vmax/vmin

On 12/24/22 00:16, Song Gao wrote: +INSN_LSX(vmax_b, vvv) +INSN_LSX(vmax_h, vvv) +INSN_LSX(vmax_w, vvv) +INSN_LSX(vmax_d, vvv) +INSN_LSX(vmin_b, vvv) +INSN_LSX(vmin_h, vvv) +INSN_LSX(vmin_w, vvv) +INSN_LSX(vmin_d, vvv

Re: [RFC PATCH 13/43] target/loongarch: Implement vadda

On 12/24/22 00:16, Song Gao wrote: +TRANS(vadda_b, gen_vvv, gen_helper_vadda_b) +TRANS(vadda_h, gen_vvv, gen_helper_vadda_h) +TRANS(vadda_w, gen_vvv, gen_helper_vadda_w) +TRANS(vadda_d, gen_vvv, gen_helper_vadda_d) These can be implemented with abs + add. r~

Re: [RFC PATCH 12/43] target/loongarch: Implement vabsd

On 12/24/22 00:16, Song Gao wrote: +INSN_LSX(vabsd_b, vvv) +INSN_LSX(vabsd_h, vvv) +INSN_LSX(vabsd_w, vvv) +INSN_LSX(vabsd_d, vvv) +INSN_LSX(vabsd_bu, vvv) +INSN_LSX(vabsd_hu, vvv) +INSN_LSX(vabsd_wu, vvv) +INSN_LSX(vabsd_du, vvv

Re: [RFC PATCH 11/43] target/loongarch: Implement vavg/vavgr

On 12/24/22 00:16, Song Gao wrote: +TRANS(vavg_b, gen_vvv, gen_helper_vavg_b) +TRANS(vavg_h, gen_vvv, gen_helper_vavg_h) +TRANS(vavg_w, gen_vvv, gen_helper_vavg_w) +TRANS(vavg_d, gen_vvv, gen_helper_vavg_d) +TRANS(vavg_bu, gen_vvv, gen_helper_vavg_bu) +TRANS(vavg_hu, gen_vvv, gen_helper_vavg_hu)

Re: [RFC PATCH 10/43] target/loongarch: Implement vaddw/vsubw

On 12/24/22 00:16, Song Gao wrote: +TRANS(vaddwev_h_b, gen_vvv, gen_helper_vaddwev_h_b) +TRANS(vaddwev_w_h, gen_vvv, gen_helper_vaddwev_w_h) +TRANS(vaddwev_d_w, gen_vvv, gen_helper_vaddwev_d_w) +TRANS(vaddwev_q_d, gen_vvv, gen_helper_vaddwev_q_d) +TRANS(vaddwod_h_b, gen_vvv, gen_helper_vaddwod_h_

Re: [RFC PATCH 09/43] target/loongarch: Implement vhaddw/vhsubw

On 12/24/22 00:15, Song Gao wrote: +#define S_EVEN(a, bit) \ +int64_t)(a)) << (64 - bit / 2)) >> (64 - bit / 2)) + +#define U_EVEN(a, bit) \ +uint64_t)(a)) << (64 - bit / 2)) >> (64 - bit / 2)) + +#define S_ODD(a, bit) \ +int64_t)(a)) << (64 - bit)) >> (64 - bi

Re: [RFC PATCH 01/43] target/loongarch: Add vector data type vec_t

On 12/24/22 00:15, Song Gao wrote: +union vec_t { +int8_t B[LSX_LEN / 8]; +int16_t H[LSX_LEN / 16]; +int32_t W[LSX_LEN / 32]; +int64_t D[LSX_LEN / 64]; +__int128 Q[LSX_LEN / 128]; Oh, you can't use __int128 directly. It won't compile on 32-bit hosts. r~

Re: [RFC PATCH 08/43] target/loongarch: Implement vsadd/vssub

On 12/24/22 00:15, Song Gao wrote: +TRANS(vsadd_b, gen_vvv, gen_helper_vsadd_b) +TRANS(vsadd_h, gen_vvv, gen_helper_vsadd_h) +TRANS(vsadd_w, gen_vvv, gen_helper_vsadd_w) +TRANS(vsadd_d, gen_vvv, gen_helper_vsadd_d) +TRANS(vsadd_bu, gen_vvv, gen_helper_vsadd_bu) +TRANS(vsadd_hu, gen_vvv, gen_helpe

Re: [RFC PATCH 07/43] target/loongarch: Implement vneg

On 12/24/22 00:15, Song Gao wrote: +TRANS(vneg_b, gen_vv, gen_helper_vneg_b) +TRANS(vneg_h, gen_vv, gen_helper_vneg_h) +TRANS(vneg_w, gen_vv, gen_helper_vneg_w) +TRANS(vneg_d, gen_vv, gen_helper_vneg_d) These can be implemented with tcg_gen_gvec_neg. r~

Re: [RFC PATCH 06/43] target/loongarch: Implement vaddi/vsubi

On 12/24/22 00:15, Song Gao wrote: +static bool gen_vv_i(DisasContext *ctx, arg_vv_i *a, + void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32)) +{ +TCGv_i32 vd = tcg_constant_i32(a->vd); +TCGv_i32 vj = tcg_constant_i32(a->vj); +TCGv_i32 imm = tcg_constant_i32(a->i

Re: [RFC PATCH 01/43] target/loongarch: Add vector data type vec_t

On 12/24/22 00:15, Song Gao wrote: +union fpr_t { +uint64_t d; +vec_t vec; +}; + struct LoongArchTLB { uint64_t tlb_misc; /* Fields corresponding to CSR_TLBELO0/1 */ @@ -251,7 +267,7 @@ typedef struct CPUArchState { uint64_t gpr[32]; uint64_t pc; -uint64_t

Re: [RFC PATCH 05/43] target/loongarch: Implement vadd/vsub

On 12/24/22 00:15, Song Gao wrote: +static bool gen_vvv(DisasContext *ctx, arg_vvv *a, +void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32)) +{ +TCGv_i32 vd = tcg_constant_i32(a->vd); +TCGv_i32 vj = tcg_constant_i32(a->vj); +TCGv_i32 vk = tcg_constant_i32(a->vk);

Re: [RFC PATCH 01/43] target/loongarch: Add vector data type vec_t

On 12/24/22 00:15, Song Gao wrote: +#define LSX_LEN (128) +typedef union vec_t vec_t; +union vec_t { +int8_t B[LSX_LEN / 8]; +int16_t H[LSX_LEN / 16]; +int32_t W[LSX_LEN / 32]; +int64_t D[LSX_LEN / 64]; +__int128 Q[LSX_LEN / 128]; +}; + +typedef union fpr_t fpr_t; +unio

Re: [RFC PATCH 00/43] Add LoongArch LSX instructions

On 12/24/22 00:15, Song Gao wrote: Hi, Merry Christmas! This series adds LoongArch LSX instructions, Since the LoongArch Vol2 is not open, So we use 'RFC' title. That is unfortunate, as it makes reviewing this difficult. Is there a timeline for this being published? In the meantime, I can at

[PATCH 2/4] accel/tcg: Use g_free_rcu for user-exec interval trees

Because we allow lockless lookups, we have to be careful when it is freed. Use rcu to delay the free until safe. Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 18 ++ 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/u

[PATCH 0/4] accel/tcg: Fixes for user-only page tracking

Fix all three bugs pointed out by Ilya, and for the moment at least, adjust the testcase to set read+write for writability. r~ Ilya Leoshkevich (1): tests/tcg/multiarch: add vma-pthread.c Richard Henderson (3): accel/tcg: Fix tb_invalidate_phys_page_unwind accel/tcg: Use g_free_rcu for u

[PATCH 3/4] accel/tcg: Handle false negative lookup in page_check_range

As in page_get_flags, we need to try again with the mmap lock held if we fail a page lookup. Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 39 --- 1 file changed, 32 insertions(+), 7 deletions(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/u

[PATCH 1/4] accel/tcg: Fix tb_invalidate_phys_page_unwind

When called from syscall(), we are not within a TB and pc == 0. We can skip the check for invalidating the current TB. Signed-off-by: Richard Henderson --- accel/tcg/tb-maint.c | 78 1 file changed, 43 insertions(+), 35 deletions(-) diff --git a/acce

[PATCH 4/4] tests/tcg/multiarch: add vma-pthread.c

From: Ilya Leoshkevich Add a test that locklessly changes and exercises page protection bits from various threads. This helps catch race conditions in the VMA handling. Signed-off-by: Ilya Leoshkevich Message-Id: <20221223120252.513319-1-...@linux.ibm.com> Signed-off-by: Richard Henderson ---

Re: [PATCH] tests/tcg/multiarch: add vma-pthread.c

On 12/23/22 04:02, Ilya Leoshkevich wrote: +static void *thread_write(void *arg) +{ +struct context *ctx = arg; +struct timespec *ts; +size_t i, j; +int ret; + +for (i = 0; ctx->mutator_count; i++) { +j = (i & PAGE_IDX_MASK) | PAGE_IDX_W_MASK; +/* Write directl

Re: [PULL v2 07/14] accel/tcg: Use interval tree for user-only page tracking

On 12/23/22 06:32, Ilya Leoshkevich wrote: +mmap_lock(); +p = pageflags_find(address, address); +mmap_unlock(); How does the code ensure that p is not freed here? +return p ? p->flags : 0; Yep, need to use g_free_rcu. +while (true) { +PageFlagsNode *p = pagefla

[PATCH 1/2] vdpa-dev: get iova range explicitly

From: Longpeng In commit a585fad26b ("vdpa: request iova_range only once") we remove GET_IOVA_RANGE form vhost_vdpa_init, the generic vdpa device will start without iova_range populated, so the device won't work. Let's call GET_IOVA_RANGE ioctl explicitly. Fixes: a585fad26b2e6ccc ("vdpa: request

[PATCH 2/2] vdpa: harden the error path if get_iova_range failed

From: Longpeng We should stop if the GET_IOVA_RANGE ioctl failed. Signed-off-by: Longpeng --- net/vhost-vdpa.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c index ffdc435d19..e65023d013 100644 --- a/net/vhost-vdpa.c +++ b/net/vho

[PATCH 0/2] Fix the init path of generic vhost-vdpa device

From: Longpeng The generic vhost-vdpa device and the commit a585fad26b ("vdpa: request iova_range only once") are merged in the same pull request, and the later would cause the generic vhost-vdpa device work improperly. Patch 1 fixes the problem and patch 2 hardens the error path of vdpa/net. L

Re: [PATCH v2 0/7] include/hw/pci include/hw/cxl: Clean up includes

On Fri, Dec 23, 2022 at 06:27:07AM +0100, Markus Armbruster wrote: > "Michael S. Tsirkin" writes: > > > On Thu, Dec 22, 2022 at 11:48:25AM +0100, Markus Armbruster wrote: > >> Bernhard Beschow writes: > >> > >> > Am 22. Dezember 2022 10:03:23 UTC schrieb Markus Armbruster > >> > : > >> >>Back

Re: [PATCH] scripts/coverity-scan/model.c: update address_space_*_cached

On 23/12/22 21:43, Vladimir Sementsov-Ogievskiy wrote: Make prototypes correspond to their origins. Also drop address_space_rw_cached() which doesn't exist anywhere in the code. Signed-off-by: Vladimir Sementsov-Ogievskiy --- scripts/coverity-scan/model.c | 15 +-- 1 file changed

[RFC PATCH 07/43] target/loongarch: Implement vneg

This patch includes; - VNEG.{B/H/W/D}. Signed-off-by: Song Gao --- target/loongarch/disas.c| 10 + target/loongarch/helper.h | 5 +++ target/loongarch/insn_trans/trans_lsx.c.inc | 16 target/loongarch/insns.decode | 7 targe

[RFC PATCH 06/43] target/loongarch: Implement vaddi/vsubi

This patch includes: - VADDI.{B/H/W/D}U; - VSUBI.{B/H/W/D}U. Signed-off-by: Song Gao --- target/loongarch/disas.c| 14 + target/loongarch/helper.h | 9 +++ target/loongarch/insn_trans/trans_lsx.c.inc | 21 +++ target/loongarch/insns.decode

[RFC PATCH 17/43] target/loongarch: Implement vdiv/vmod

This patch includes: - VDIV.{B/H/W/D}[U]; - VMOD.{B/H/W/D}[U]. Signed-off-by: Song Gao --- target/loongarch/disas.c| 17 +++ target/loongarch/helper.h | 17 +++ target/loongarch/insn_trans/trans_lsx.c.inc | 17 +++ target/loongarch/insns.decode

[RFC PATCH 18/43] target/loongarch: Implement vsat

This patch includes: - VSAT.{B/H/W/D}[U]. Signed-off-by: Song Gao --- target/loongarch/disas.c| 9 +++ target/loongarch/helper.h | 9 +++ target/loongarch/insn_trans/trans_lsx.c.inc | 9 +++ target/loongarch/insns.decode | 12 target/lo

[RFC PATCH 27/43] target/loongarch: Implement vsrlrn vsrarn

This patch includes: - VSRLRN.{B.H/H.W/W.D}; - VSRARN.{B.H/H.W/W.D}; - VSRLRNI.{B.H/H.W/W.D/D.Q}; - VSRARNI.{B.H/H.W/W.D/D.Q}. Signed-off-by: Song Gao --- target/loongarch/disas.c| 16 +++ target/loongarch/helper.h | 16 +++ target/loongarch/insn_trans/tra

[RFC PATCH 01/43] target/loongarch: Add vector data type vec_t

Signed-off-by: Song Gao --- linux-user/loongarch64/signal.c | 4 ++-- target/loongarch/cpu.c | 2 +- target/loongarch/cpu.h | 18 +- target/loongarch/gdbstub.c | 4 ++-- target/loongarch/machine.c | 2 +- 5 files changed, 23 insertions(+), 7 deletio

[RFC PATCH 23/43] target/loongarch: Implement vsll vsrl vsra vrotr

This patch includes: - VSLL[I].{B/H/W/D}; - VSRL[I].{B/H/W/D}; - VSRA[I].{B/H/W/D}; - VROTR[I].{B/H/W/D}. Signed-off-by: Song Gao --- target/loongarch/disas.c| 36 target/loongarch/helper.h | 36 target/loongarch/insn_trans/trans_lsx.c.inc | 36

[RFC PATCH 24/43] target/loongarch: Implement vsllwil vextl

This patch includes: - VSLLWIL.{H.B/W.H/D.W}; - VSLLWIL.{HU.BU/WU.HU/DU.WU}; - VEXTL.Q.D, VEXTL.QU.DU. Signed-off-by: Song Gao --- target/loongarch/disas.c| 9 +++ target/loongarch/helper.h | 9 +++ target/loongarch/insn_trans/trans_lsx.c.inc | 9 +++ tar

[RFC PATCH 22/43] target/loongarch: Implement LSX logic instructions

This patch includes: - V{AND/OR/XOR/NOR/ANDN/ORN}.V; - V{AND/OR/XOR/NOR}I.B. Signed-off-by: Song Gao --- target/loongarch/disas.c| 12 target/loongarch/helper.h | 12 target/loongarch/insn_trans/trans_lsx.c.inc | 12 target/loongarch/insns.dec

[RFC PATCH 14/43] target/loongarch: Implement vmax/vmin

This patch includes: - VMAX[I].{B/H/W/D}[U]; - VMIN[I].{B/H/W/D}[U]. Signed-off-by: Song Gao --- target/loongarch/disas.c| 33 +++ target/loongarch/helper.h | 34 +++ target/loongarch/insn_trans/trans_lsx.c.inc | 33 +++ target/loongarch/insns.decode

[RFC PATCH 36/43] target/loongarch: Implement vseq vsle vslt

This patch includes: - VSEQ[I].{B/H/W/D}; - VSLE[I].{B/H/W/D}[U]; - VSLT[I].{B/H/W/D/}[U]. Signed-off-by: Song Gao --- target/loongarch/disas.c| 43 +++ target/loongarch/helper.h | 43 +++ target/loongarch/insn_trans/trans_lsx.c.inc | 43 +++ target/loong

[RFC PATCH 11/43] target/loongarch: Implement vavg/vavgr

This patch includes: - VAVG.{B/H/W/D}[U]; - VAVGR.{B/H/W/D}[U]. Signed-off-by: Song Gao --- target/loongarch/disas.c| 17 +++ target/loongarch/helper.h | 17 +++ target/loongarch/insn_trans/trans_lsx.c.inc | 17 +++ target/loongarch/insns.decode

[RFC PATCH 05/43] target/loongarch: Implement vadd/vsub

This patch includes: - VADD.{B/H/W/D/Q}; - VSUB.{B/H/W/D/Q}. Signed-off-by: Song Gao --- target/loongarch/disas.c| 23 ++ target/loongarch/helper.h | 12 +++ target/loongarch/insn_trans/trans_lsx.c.inc | 23 ++ target/loongarch/insns.decode

[RFC PATCH 13/43] target/loongarch: Implement vadda

This patch includes: - VADDA.{B/H/W/D}. Signed-off-by: Song Gao --- target/loongarch/disas.c| 5 target/loongarch/helper.h | 5 target/loongarch/insn_trans/trans_lsx.c.inc | 5 target/loongarch/insns.decode | 5 target/l

[RFC PATCH 34/43] target/loongarch: Implement LSX fpu arith instructions

This patch includes: - VF{ADD/SUB/MUL/DIV}.{S/D}; - VF{MADD/MSUB/NMADD/NMSUB}.{S/D}; - VF{MAX/MIN}.{S/D}; - VF{MAXA/MINA}.{S/D}; - VFLOGB.{S/D}; - VFCLASS.{S/D}; - VF{SQRT/RECIP/RSQRT}.{S/D}. Signed-off-by: Song Gao --- target/loongarch/disas.c| 46 + target/loongarch/fp

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