Use tcg_gen_atomic_cmpxchg_i128 for the atomic case,
and tcg_gen_qemu_ld/st_i128 otherwise.
Signed-off-by: Richard Henderson
---
target/i386/helper.h | 4 ---
target/i386/tcg/mem_helper.c | 69
target/i386/tcg/translate.c | 44 --
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 48 -
1 file changed, 31 insertions(+), 17 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 28a4e6dc1d..1175540a2c 100644
--- a/target/i386/tcg/translat
Use tcg_gen_atomic_cmpxchg_i64 for the atomic case,
and tcg_gen_nonatomic_cmpxchg_i64 otherwise.
Signed-off-by: Richard Henderson
---
target/i386/helper.h | 2 --
target/i386/tcg/mem_helper.c | 57
target/i386/tcg/translate.c | 54 ++
Use the new common functions and avoid rolling our own helpers.
r~
Based-on: 2022074101.2069454-1-richard.hender...@linaro.org
("tcg: Support for Int128 with helpers")
Richard Henderson (3):
target/i386: Split out gen_cmpxchg8b, gen_cmpxchg16b
target/i386: Inline cmpxchg8b
target/i386:
On Fri, Nov 11, 2022 at 8:45 PM Philippe Mathieu-Daudé
wrote:
>
> From: Philippe Mathieu-Daudé
>
> GCC 8 added a -Wstringop-truncation warning:
>
> The -Wstringop-truncation warning added in GCC 8.0 via r254630 for
> bug 81117 is specifically intended to highlight likely unintended
> uses o
在 2022/11/8 16:42, Stefano Garzarella 写道:
On Tue, Nov 08, 2022 at 11:30:53AM +0800, Longpeng (Mike, Cloud
Infrastructure Service Product Dept.) wrote:
在 2022/11/8 10:42, Jason Wang 写道:
On Tue, Nov 8, 2022 at 8:42 AM Longpeng(Mike)
wrote:
From: Longpeng
Signed-off-by: Longpeng
---
do
在 2022/11/8 16:46, Stefano Garzarella 写道:
On Tue, Nov 08, 2022 at 08:41:56AM +0800, Longpeng(Mike) wrote:
From: Longpeng
The generic vDPA device doesn't support migration currently, so
mark it as unmigratable temporarily.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 1 +
1 file chang
The previous test cases for virtio-serial only tested initialization of
the device. I've included four new test cases: rx for virtconsole, tx
for virtconsole, rx for virtserialport, tx for virtserialport. It
follows the general pattern of virtio-net (i.e. chardev file descriptor
backend with a sock
Use the new common function and avoid rolling our own helper(s).
r~
Based-on: 2022074101.2069454-1-richard.hender...@linaro.org
("tcg: Support for Int128 with helpers")
Richard Henderson (1):
target/ppc: Use tcg_gen_atomic_cmpxchg_i128 for STQCX
target/ppc/helper.h | 2 -
target/pp
Note that the previous direct reference to reserve_val,
- tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
-? offsetof(CPUPPCState, reserve_val2)
-: offsetof(CPUPPCState, reserve_val)));
was incorrect because all references should have go
On 11/12/22 04:25, Alex Bennée wrote:
Document the intended use of current_cpu and discourage its use in new
HW emulation code. Once we have fully converted the tree we should
probably move this extern to another header.
Signed-off-by: Alex Bennée
---
include/hw/core/cpu.h | 14 ++
On 11/12/22 04:25, Alex Bennée wrote:
Some of the callbacks need a CPUState so extend the interface so we
can pass that down rather than relying on current_cpu hacks.
Signed-off-by: Alex Bennée
---
include/hw/isa/apm.h | 2 +-
hw/acpi/ich9.c | 1 -
hw/acpi/piix4.c | 2 +-
hw/i
On 11/12/22 04:25, Alex Bennée wrote:
+switch (attrs.requester_type) {
+case MTRT_MACHINE: /* MEMTX_IOPIC */
Not checking the id?
+case MTRT_PCI: /* PCI signalled MSI */
+break;
+default:
+qemu_log_mask(LOG_GUEST_ERROR, "%s: rejectin
On 11/12/22 04:25, Alex Bennée wrote:
On the real HW the IOAPIC is wired directly to the APIC and doesn't
really generate memory accesses on the main bus of the system. To
model this we can use the MTRT_MACHINE requester type and set the id
as a magic number to represent the IOAPIC as the source.
On 11/12/22 04:25, Alex Bennée wrote:
We will need this shortly for machine specific transactions for the PC
IOAPIC.
Signed-off-by: Alex Bennée
---
include/exec/memattrs.h | 8
1 file changed, 8 insertions(+)
Fold into patch 1? Anyway,
Reviewed-by: Richard Henderson
r~
On 11/12/22 04:25, Alex Bennée wrote:
This allows us to drop the current_cpu hack and properly model an
invalid access to the vapic.
Signed-off-by: Alex Bennée
---
hw/i386/kvmvapic.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
Reviewed-by: Richard Henderson
On 11/12/22 04:25, Alex Bennée wrote:
This is simulating a bus master writing data back into system memory.
Mark it as such.
Signed-off-by: Alex Bennée
---
hw/audio/intel-hda.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c
ind
On 11/12/22 04:25, Alex Bennée wrote:
diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c
index b185ee8de4..337090e16f 100644
--- a/target/i386/hax/hax-all.c
+++ b/target/i386/hax/hax-all.c
@@ -385,7 +385,7 @@ static int hax_handle_io(CPUArchState *env, uint32_t df,
uint16_t port,
On 11/12/22 04:25, Alex Bennée wrote:
Both of the TLB fill functions and the cpu_sparc_get_phys_page deal
with CPU based access. Use the new MEMTXATTRS_CPU constructor to
ensure the correct CPU id is filled in should it ever be needed by any
devices later.
Signed-off-by: Alex Bennée
---
target
On 11/12/22 04:25, Alex Bennée wrote:
Both of these functions deal with CPU based access (as is evidenced by
the secure check straight after). Use the new MEMTXATTRS_CPU
constructor to ensure the correct CPU id is filled in should it ever
be needed by any devices later.
Signed-off-by: Alex Benné
On 11/12/22 04:25, Alex Bennée wrote:
We can derive the correct CPU from CPUARMState so lets not rely on
current_cpu.
Signed-off-by: Alex Bennée
---
hw/arm/pxa2xx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 11/12/22 04:25, Alex Bennée wrote:
Although most KVM users will use the in-kernel GIC emulation it is
perfectly possible not to. In this case we need to ensure the
MemTxAttrs are correctly populated so the GIC can divine the source
CPU of the operation.
Reviewed-by: Richard Henderson
Signed-
On 11/12/22 04:25, Alex Bennée wrote:
@@ -2872,7 +2873,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs,
vaddr addr,
.in_secure = arm_is_secure(env),
.in_debug = true,
};
-GetPhysAddrResult res = {};
+GetPhysAddrResult res = { .f.attrs = MEMTXATTRS_CPU
On 11/12/22 04:25, Alex Bennée wrote:
There are a number of helpers for M-profile that deal with CPU
initiated access to the vector and stack areas. While it is unlikely
these coincided with memory mapped IO devices it is not inconceivable.
Embedded targets tend to attract all sorts of interestin
On 11/12/22 04:25, Alex Bennée wrote:
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 3745ac9723..4b6683f90d 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -2634,6 +2634,7 @@ static bool get_phys_addr_twostage(CPUARMState *env,
S1Translate *ptw,
s1_lgpgsz = result->f.lg_pag
Most of the changes are trivial. The bits test timeout has now been increased
to 200 seconds in order to accommodate slower systems and fewer unnecessary
failures. Removed of the reference to non-existent README file in docs. Some
minor corrections in the doc file.
CC: Thomas Huth
CC: Michael S.
On Fri, Nov 11, 2022 at 4:39 PM Ani Sinha wrote:
>
> On Fri, Nov 11, 2022 at 9:52 AM Ani Sinha wrote:
> >
> > On Thu, Nov 10, 2022 at 11:37 PM John Snow wrote:
> > >
> > > Hiya, on today's origin/master
> > > (2ccad61746ca7de5dd3e25146062264387e43bd4) I'm finding that "make
> > > check-avocado"
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.h| 6 ---
target/arm/helper-a64.c| 104 -
target/arm/translate-a64.c | 60 -
3 files changed, 35 insertions(+), 135 deletions(-)
diff --git a/target/arm/helper-a64.h b/ta
Use the new common function and avoid rolling our own helper(s).
r~
Based-on: 2022074101.2069454-1-richard.hender...@linaro.org
("tcg: Support for Int128 with helpers")
Richard Henderson (2):
target/arm: Use tcg_gen_atomic_cmpxchg_i128 for STXP
target/arm: Use tcg_gen_atomic_cmpxchg_i12
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.h| 2 --
target/arm/helper-a64.c| 43 ---
target/arm/translate-a64.c | 61 +++---
3 files changed, 18 insertions(+), 88 deletions(-)
diff --git a/target/arm/helper-a64.h b/
On 11/12/22 04:25, Alex Bennée wrote:
+/*
+ * Bus masters which don't specify any attributes will get this which
+ * indicates none of the attributes can be used.
+ */
+#define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) \
+{ .requester_type = MTRT_UNSPECIFIED })
+
+/*
+
From: Song Gao
Fix LoongArch check-tcg error:
TESThello on loongarch64
qemu-system-loongarch64: Some ROM regions are overlapping
These ROM regions might have been loaded by direct user request or by default.
They could be BIOS/firmware images, a guest kernel, initrd or some other file
loa
Since the fix has been sitting around on the list for a
few days, I thought I'd help get this merged before rc1.
r~
The following changes since commit 2ccad61746ca7de5dd3e25146062264387e43bd4:
Merge tag 'pull-tcg-20221109' of https://gitlab.com/rth7680/qemu into staging
(2022-11-09 13:26:45
On 11/11/2022 18:25, Alex Bennée wrote:
Both of the TLB fill functions and the cpu_sparc_get_phys_page deal
with CPU based access. Use the new MEMTXATTRS_CPU constructor to
ensure the correct CPU id is filled in should it ever be needed by any
devices later.
Signed-off-by: Alex Bennée
---
ta
On 10/11/2022 14:34, Peter Maydell wrote:
This patchset converts the TYPE_MOS6522 class and its subclasses to
use 3-phase reset. This is part of the work I'm doing to clean up some
of the reset-related code by getting rid of the
device_class_set_parent_reset() function, which is used by
legacy-r
On Sat, Nov 12, 2022 at 8:42 AM Atish Kumar Patra wrote:
>
>
>
> On Fri, Nov 11, 2022 at 4:39 PM Bin Meng wrote:
>>
>> On Sat, Nov 12, 2022 at 4:14 AM Atish Patra wrote:
>> >
>> > The imsic DT binding has changed and no longer require an ipi-id.
>>
>> requires
>>
>
> Sure. Will fix it.
>
>>
>> C
On Fri, Nov 11, 2022 at 4:39 PM Bin Meng wrote:
> On Sat, Nov 12, 2022 at 4:14 AM Atish Patra wrote:
> >
> > The imsic DT binding has changed and no longer require an ipi-id.
>
> requires
>
>
Sure. Will fix it.
> Could you please put a link here to the upstream imsic DT binding for
> reference
On Sat, Nov 12, 2022 at 4:14 AM Atish Patra wrote:
>
> The imsic DT binding has changed and no longer require an ipi-id.
requires
Could you please put a link here to the upstream imsic DT binding for reference?
> The latest IMSIC driver dynamically allocates ipi id if slow-ipi
> is not defined.
Hi Conor,
On Sat, Nov 12, 2022 at 8:31 AM Conor Dooley wrote:
>
> On Thu, Nov 10, 2022 at 12:18:44AM +0100, Philippe Mathieu-Daudé wrote:
> > Hi Conor,
> >
> > On 9/11/22 20:08, Conor Dooley wrote:
> > > From: Conor Dooley
> > >
> > > @@ -168,6 +170,10 @@ static void mchp_pfsoc_ioscb_realize(Dev
On Thu, Nov 10, 2022 at 12:18:44AM +0100, Philippe Mathieu-Daudé wrote:
> Hi Conor,
>
> On 9/11/22 20:08, Conor Dooley wrote:
> > From: Conor Dooley
> >
> > @@ -168,6 +170,10 @@ static void mchp_pfsoc_ioscb_realize(DeviceState *dev,
> > Error **errp)
> > "mchp.pfsoc.
On 11/11/22 6:54 PM, Igor Mammedov wrote:
On Fri, 11 Nov 2022 17:34:04 +0800
Gavin Shan wrote:
On 11/11/22 5:13 PM, Igor Mammedov wrote:
On Fri, 11 Nov 2022 07:47:16 +0100
Markus Armbruster wrote:
Gavin Shan writes:
On 11/11/22 11:05 AM, Zhenyu Zhang wrote:
Commit ffac16fab3 "hostmem: int
The imsic DT binding has changed and no longer require an ipi-id.
The latest IMSIC driver dynamically allocates ipi id if slow-ipi
is not defined.
Get rid of the unused dt property which may lead to confusion.
Signed-off-by: Atish Patra
---
hw/riscv/virt.c | 2 --
include/hw/riscv/virt.
On Fri, Nov 11, 2022 at 06:25:25PM +, Alex Bennée wrote:
> Both of these functions deal with CPU based access (as is evidenced by
> the secure check straight after). Use the new MEMTXATTRS_CPU
> constructor to ensure the correct CPU id is filled in should it ever
> be needed by any devices late
On 11/11/22 15:55, Alex Bennée wrote:
This should hopefully give is nice coverage information about what our
tests (or at least the subset we are running) have hit. Ideally we
would want a way to trigger coverage on tests likely to be affected by
the current commit.
IIUC per [*] this will not a
On Fri, 11 Nov 2022 at 10:29, Kevin Wolf wrote:
>
> The following changes since commit 2ccad61746ca7de5dd3e25146062264387e43bd4:
>
> Merge tag 'pull-tcg-20221109' of https://gitlab.com/rth7680/qemu into
> staging (2022-11-09 13:26:45 -0500)
>
> are available in the Git repository at:
>
> http
The previous reply email has an text format error, please ignore and
在 2022/11/11 3:00, Michael S. Tsirkin 写道:
On Sun, Oct 30, 2022 at 09:52:39PM +0800, huang...@chinatelecom.cn wrote:
From: Hyman Huang(黄勇)
Save the acked_features once it be configured by guest
virtio driver so it can't miss
在 2022/11/11 3:00, Michael S. Tsirkin 写道:
On Sun, Oct 30, 2022 at 09:52:39PM +0800, huang...@chinatelecom.cn wrote:
From: Hyman Huang(黄勇)
Save the acked_features once it be configured by guest
virtio driver so it can't miss any features.
Note that this patch also change the features saving
Am 11.11.22 um 19:28 schrieb Thomas Huth:
Fix typos (discovered with the 'codespell' utility).
Signed-off-by: Thomas Huth
---
hw/s390x/ipl.h | 2 +-
pc-bios/s390-ccw/cio.h | 2 +-
pc-bios/s390-ccw/iplb.h | 2 +-
target/s390x/cpu_models.h
Where appropriate initialise with MEMTXATTRS_CPU otherwise use
MEMTXATTRS_UNSPECIFIED instead of the null initialiser.
Signed-off-by: Alex Bennée
---
target/i386/cpu.h | 4 +++-
target/i386/hax/hax-all.c | 2 +-
target/i386/nvmm/nvmm-all.c | 2 +-
target/i386/sev.c | 2 +-
On the real HW the IOAPIC is wired directly to the APIC and doesn't
really generate memory accesses on the main bus of the system. To
model this we can use the MTRT_MACHINE requester type and set the id
as a magic number to represent the IOAPIC as the source.
Signed-off-by: Alex Bennée
Cc: Paolo
Document the intended use of current_cpu and discourage its use in new
HW emulation code. Once we have fully converted the tree we should
probably move this extern to another header.
Signed-off-by: Alex Bennée
---
include/hw/core/cpu.h | 14 ++
1 file changed, 14 insertions(+)
diff
Both of the TLB fill functions and the cpu_sparc_get_phys_page deal
with CPU based access. Use the new MEMTXATTRS_CPU constructor to
ensure the correct CPU id is filled in should it ever be needed by any
devices later.
Signed-off-by: Alex Bennée
---
target/sparc/mmu_helper.c | 6 +++---
1 file c
This allows us to correctly model invalid accesses to the interrupt
controller as well as avoiding the use of current_cpu hacks to find
the APIC structure. We have to ensure we check for MSI signals first
which shouldn't arrive from the CPU but are either triggered by PCI or
internal IOAPIC writes.
This is simulating a bus master writing data back into system memory.
Mark it as such.
Signed-off-by: Alex Bennée
---
hw/audio/intel-hda.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c
index f38117057b..95c28b315c 100644
--- a/hw/
We can derive the correct CPU from CPUARMState so lets not rely on
current_cpu.
Signed-off-by: Alex Bennée
---
hw/arm/pxa2xx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index 93dda83d7a..065392a8bc 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/
Some of the callbacks need a CPUState so extend the interface so we
can pass that down rather than relying on current_cpu hacks.
Signed-off-by: Alex Bennée
---
include/hw/isa/apm.h | 2 +-
hw/acpi/ich9.c | 1 -
hw/acpi/piix4.c | 2 +-
hw/isa/apm.c | 21 +
The point of qtest is to simulate how running code might interact with
the system. However because it's not a real system we have places in
the code which especially handle check qtest_enabled() before
referencing current_cpu. Now we can encode these details in the
MemTxAttrs lets do that so we can
Fix typos (discovered with the 'codespell' utility).
Signed-off-by: Thomas Huth
---
hw/s390x/ipl.h | 2 +-
pc-bios/s390-ccw/cio.h | 2 +-
pc-bios/s390-ccw/iplb.h | 2 +-
target/s390x/cpu_models.h | 4 ++--
hw/s390x/s390-pci-vfio.c
Now that MxTxAttrs encodes a CPU we should use that to figure it out.
This solves edge cases like accessing via gdbstub or qtest. As we
should only be processing accesses from CPU cores we can push the CPU
extraction logic out to the main access functions. If the access does
not come from a CPU we
get_physical_address works in the CPU context. Use the new
MEMTXATTRS_CPU constructor to ensure the correct CPU id is filled in
should it ever be needed by any devices later.
Currently the tlb_fill function isn't using the set with attributes
function so IO accesses from the softmmu slow-path will
Both of these functions deal with CPU based access (as is evidenced by
the secure check straight after). Use the new MEMTXATTRS_CPU
constructor to ensure the correct CPU id is filled in should it ever
be needed by any devices later.
Signed-off-by: Alex Bennée
---
target/microblaze/helper.c | 4 +
We will need this shortly for machine specific transactions for the PC
IOAPIC.
Signed-off-by: Alex Bennée
---
include/exec/memattrs.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index 8359fc448b..b92f11aaa4 100644
--- a/include/ex
Both arm_cpu_tlb_fill (for normal IO) and
arm_cpu_get_phys_page_attrs_debug (for debug access) come through
get_phys_addr which is setting the other memory attributes for the
transaction. As these are all by definition CPU accesses we can also
set the requested_type/index as appropriate.
We also h
This allows us to drop the current_cpu hack and properly model an
invalid access to the vapic.
Signed-off-by: Alex Bennée
---
hw/i386/kvmvapic.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
index 43f8a8f679..a76e
There are a number of helpers for M-profile that deal with CPU
initiated access to the vector and stack areas. While it is unlikely
these coincided with memory mapped IO devices it is not inconceivable.
Embedded targets tend to attract all sorts of interesting code and for
completeness we should ta
We currently have hacks across the hw/ to reference current_cpu to
work out what the current accessing CPU is. This breaks in some cases
including using gdbstub to access HW state. As we have MemTxAttrs to
describe details about the access lets extend it so CPU accesses can
be explicitly marked.
T
Although most KVM users will use the in-kernel GIC emulation it is
perfectly possible not to. In this case we need to ensure the
MemTxAttrs are correctly populated so the GIC can divine the source
CPU of the operation.
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
v3
- new for
Hi,
This series attempts to improve the modelling of non-CPU writes to
peripherals by expanding the MemTxAttrs to carry more details about
the requester. There are only 3 requester types, the CPU, the PCI bus
and the MACHINE. The last is intended for machine specific buses and
leaves the details o
As most HVF devices are done purely in software we need to make sure
we properly encode the source CPU in MemTxAttrs. This will allow the
device emulations to use those attributes rather than relying on
current_cpu (although current_cpu will still be correct in this case).
Signed-off-by: Alex Benn
This removes the hacks to deal with empty current_cpu.
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
v2
- update for new fields
- bool asserts
v3
- properly fail memory transactions from non-CPU sources
---
hw/timer/arm_mptimer.c | 49 +
On 11/11/22 15:55, Alex Bennée wrote:
This is useful when trying to bisect a particular failing test behind
a docker run. For example:
make docker-test-clang@fedora \
TARGET_LIST=arm-softmmu \
TEST_COMMAND="meson test qtest-arm/qos-test" \
J=9 V=1
Signed-off-by: Alex Bennée
Am 09.11.2022 um 17:00 hat Vladimir Sementsov-Ogievskiy geschrieben:
> In subject: individual
>
> On 11/8/22 15:37, Kevin Wolf wrote:
> > bdrv_reopen() and friends use subtree drains as a lazy way of covering
> > all the nodes they touch. Turns out that this lazy way is a lot more
> > complicated
Reviewed-by: Stefan Hajnoczi
On 11/11/2022 15.55, Alex Bennée wrote:
From: Stefan Weil
The docker probe uses "sudo -n" which can cause an e-mail with a security
warning
each time when configure is run. Therefore run docker probe only if either
docker
or podman are available.
That avoids the problematic "sudo -n" on buil
Am 09.11.2022 um 15:44 hat Vladimir Sementsov-Ogievskiy geschrieben:
> On 11/8/22 15:37, Kevin Wolf wrote:
> > drained_end_counter is unused now, nobody changes its value any more. It
> > can be removed.
> >
> > In cases where we had two almost identical functions that only differed
> > in whether
On 11/11/2022 15.53, Markus Armbruster wrote:
Thomas Huth writes:
The "query-command-line-options" command uses a hand-crafted list
of options that should be returned for the "machine" parameter.
This is pretty much out of sync with reality, for example settings
like "kvm_shadow_mem" or "accel
> From: Philippe Mathieu-Daudé
>
> GCC 8 added a -Wstringop-truncation warning:
>
> The -Wstringop-truncation warning added in GCC 8.0 via r254630 for
> bug 81117 is specifically intended to highlight likely unintended
> uses of the strncpy function that truncate the terminating NUL
> ch
Il ven 11 nov 2022, 15:03 Alex Bennée ha scritto:
>
> Paolo Bonzini writes:
>
> > On 11/11/22 13:26, Alex Bennée wrote:
> >> if (addr > 0xfff || !index) {
> >> switch (attrs.requester_type) {
> >> }
> >> MSIMessage msi = { .address = addr, .data = val };
> >>
Most of the changes are trivial. The bits test timeout has now been increased
to 110 seconds in order to accommodate slower systems and fewer unnecessary
failures. Removed of the reference to non-existent README file in docs. Some
minor corrections in the doc file.
CC: Thomas Huth
CC: Michael S.
This API allows the accelerators to prevent vcpus from issuing
new ioctls while execting a critical section marked with the
accel_ioctl_inhibit_begin/end functions.
Note that all functions submitting ioctls must mark where the
ioctl is being called with accel_{cpu_}ioctl_begin/end().
This API req
Using the new accel-blocker API, mark where ioctls are being called
in KVM. Next, we will implement the critical section that will take
care of performing memslots modifications atomically, therefore
preventing any new ioctl from running and allowing the running ones
to finish.
Signed-off-by: Davi
QEMU needs to perform memslots operations like merging and splitting,
and each operation requires more than a single ioctl.
Therefore if a vcpu is concurrently reading the same memslots,
it could end up reading something that was temporarly deleted.
For example, merging two memslots into one would
From: David Hildenbrand
If we update an existing memslot (e.g., resize, split), we temporarily
remove the memslot to re-add it immediately afterwards. These updates
are not atomic, especially not for KVM VCPU threads, such that we can
get spurious faults.
Let's inhibit most KVM ioctls while perf
From: Hanna Reitz
blk_get_aio_context() asserts that blk->ctx is always equal to the root
BDS's context (if there is a root BDS). Therefore,
blk_do_set_aio_context() must update blk->ctx immediately after the root
BDS's context has changed.
Without this patch, the next patch would break iotest
From: Hanna Reitz
We want to use bdrv_child_get_parent_aio_context() from
bdrv_parent_drained_{begin,end}_single(), both of which are "I/O or GS"
functions.
Prior to 3ed4f708fe1, all the implementations were I/O code anyway.
3ed4f708fe1 has put block jobs' AioContext field under the job mutex, s
From: Hanna Reitz
mirror_wait_for_free_in_flight_slot() is the only remaining user of
mirror_wait_for_any_operation(), so inline the latter into the former.
Signed-off-by: Hanna Reitz
Message-Id: <20221109165452.67927-3-hre...@redhat.com>
Reviewed-by: Kevin Wolf
Signed-off-by: Kevin Wolf
---
From: Hanna Reitz
There is a small gap in mirror_start_job() before putting the mirror
filter node into the block graph (bdrv_append() call) and the actual job
being created. Before the job is created, MirrorBDSOpaque.job is NULL.
It is possible that requests come in when bdrv_drained_end() is
From: Hanna Reitz
Waiting for all active writes to settle before daring to create a
background copying operation means that we will never do background
operations while the guest does anything (in write-blocking mode), and
therefore cannot converge. Yes, we also will not diverge, but actually
co
From: Hanna Reitz
bdrv_parent_drained_{begin,end}_single() are supposed to operate on the
parent, not on the child, so they should not attempt to get the context
to poll from the child but the parent instead. BDRV_POLL_WHILE(c->bs)
does get the context from the child, so we should replace it wit
From: Hanna Reitz
Have write requests happen to the source node right when we start a
mirror job. The mirror filter node may encounter MirrorBDSOpaque.job
being NULL, but this should not cause a segfault.
Signed-off-by: Hanna Reitz
Message-Id: <20221109165452.67927-6-hre...@redhat.com>
Reviewe
From: Hanna Reitz
Before this series, a mirror job in write-blocking mode would pause
issuing background requests while active requests are in flight. Thus,
if the source is constantly in use by active requests, no actual
progress can be made.
This series should have fixed that, making the mirr
The following changes since commit 2ccad61746ca7de5dd3e25146062264387e43bd4:
Merge tag 'pull-tcg-20221109' of https://gitlab.com/rth7680/qemu into staging
(2022-11-09 13:26:45 -0500)
are available in the Git repository at:
https://repo.or.cz/qemu/kevin.git tags/for-upstream
for you to fetc
From: Alberto Faria
The nvme-io_uring BlockDriver's path option must point at the character
device of an NVMe namespace, not at an image file.
Fixes: fd66dbd424f5 ("blkio: add libblkio block driver")
Suggested-by: Stefano Garzarella
Signed-off-by: Alberto Faria
Message-Id: <20221108142347.1322
From: Hanna Reitz
Test streaming a base image into the top image underneath two throttle
nodes. This was reported to make qemu 7.1 hang
(https://gitlab.com/qemu-project/qemu/-/issues/1215), so this serves as
a regression test.
Signed-off-by: Hanna Reitz
Message-Id: <20221110160921.33158-1-hre.
From: Alberto Faria
Setting it to true can cause the device size to be queried from libblkio
in otherwise fast paths, degrading performance. Set it to false and
require users to refresh the device size explicitly instead.
Fixes: 4c8f4fda0504 ("block/blkio: Tolerate device size changes")
Suggeste
Adding Michael's name to the list of bios bits maintainers so that all changes
and fixes into biosbits framework can go through his tree and he is notified.
Suggested-by: Michael S. Tsirkin
Signed-off-by: Ani Sinha
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS
This attempts to deal with the problem of login prompts not being
guaranteed to be terminated with a newline. The solution to this is to
peek at the incoming data looking to see if we see an up-coming match
before we fall back to the old readline() logic. The reason to mostly
rely on readline is be
This is useful when trying to bisect a particular failing test behind
a docker run. For example:
make docker-test-clang@fedora \
TARGET_LIST=arm-softmmu \
TEST_COMMAND="meson test qtest-arm/qos-test" \
J=9 V=1
Signed-off-by: Alex Bennée
---
v1
- fix s/target /target./
- CHECK_TA
From: Peter Maydell
On my machine, a debug build of QEMU takes about 260 seconds to
complete this test, so with the current timeout value of 180 seconds
it always times out. Double the timeout value to 360 so the test
definitely has enough time to complete.
Signed-off-by: Peter Maydell
Signed-
We welcome all sorts of patches.
Signed-off-by: Alex Bennée
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Paolo Bonzini
Message-Id: <20221012121152.1179051-3-alex.ben...@linaro.org>
---
docs/devel/submitting-a-patch.rst | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a
1 - 100 of 239 matches
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